2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2002-10-25 22:26:29 +04:00
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// $Id: logical16.cc,v 1.18 2002-10-25 18:26:28 sshwarts Exp $
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2001-04-10 06:20:02 +04:00
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// Copyright (C) 2001 MandrakeSoft S.A.
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2001-04-10 05:04:59 +04:00
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2001-05-24 22:46:34 +04:00
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#define NEED_CPU_REG_SHORTCUTS 1
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2001-04-10 05:04:59 +04:00
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#include "bochs.h"
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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#define LOG_THIS BX_CPU_THIS_PTR
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2001-04-10 05:04:59 +04:00
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::XOR_EwGw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op2_16, op1_16, result_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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2002-10-08 02:51:58 +04:00
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2002-10-03 22:12:40 +04:00
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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2002-10-08 02:51:58 +04:00
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asmXor16(result_16, op1_16, op2_16, flags32);
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setEFlagsOSZAPC(flags32);
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2002-10-03 22:12:40 +04:00
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#else
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2001-04-10 05:04:59 +04:00
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result_16 = op1_16 ^ op2_16;
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2002-10-03 22:12:40 +04:00
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#endif
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2002-09-30 07:37:42 +04:00
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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2002-10-03 22:12:40 +04:00
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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2002-10-08 02:51:58 +04:00
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asmXor16(result_16, op1_16, op2_16, flags32);
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setEFlagsOSZAPC(flags32);
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2002-10-03 22:12:40 +04:00
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#else
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2002-09-30 07:37:42 +04:00
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result_16 = op1_16 ^ op2_16;
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2002-10-03 22:12:40 +04:00
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#endif
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2002-10-25 22:26:29 +04:00
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Write_RMW_virtual_word(result_16);
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2002-09-30 07:37:42 +04:00
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}
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2001-04-10 05:04:59 +04:00
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2002-10-03 22:12:40 +04:00
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#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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2002-09-30 07:37:42 +04:00
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
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2002-10-03 22:12:40 +04:00
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#endif
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::XOR_GwEw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op1_16, op2_16, result_16;
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2002-10-08 02:51:58 +04:00
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unsigned nnn = i->nnn();
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2001-04-10 05:04:59 +04:00
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2002-10-08 02:51:58 +04:00
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op1_16 = BX_READ_16BIT_REG(nnn);
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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result_16 = op1_16 ^ op2_16;
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2001-04-10 05:04:59 +04:00
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2002-10-08 02:51:58 +04:00
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BX_WRITE_16BIT_REG(nnn, result_16);
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::XOR_AXIw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op1_16, op2_16, sum_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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op1_16 = AX;
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op2_16 = i->Iw();
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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sum_16 = op1_16 ^ op2_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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AX = sum_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_XOR16);
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::XOR_EwIw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op2_16, op1_16, result_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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op2_16 = i->Iw();
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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2001-04-10 05:04:59 +04:00
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result_16 = op1_16 ^ op2_16;
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2002-09-30 07:37:42 +04:00
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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result_16 = op1_16 ^ op2_16;
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2002-10-25 22:26:29 +04:00
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Write_RMW_virtual_word(result_16);
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2002-09-30 07:37:42 +04:00
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}
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::OR_EwIw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op2_16, op1_16, result_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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op2_16 = i->Iw();
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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2001-04-10 05:04:59 +04:00
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result_16 = op1_16 | op2_16;
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2002-09-30 07:37:42 +04:00
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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result_16 = op1_16 | op2_16;
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2002-10-25 22:26:29 +04:00
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Write_RMW_virtual_word(result_16);
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2002-09-30 07:37:42 +04:00
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}
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::NOT_Ew(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op1_16, result_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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2001-04-10 05:04:59 +04:00
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result_16 = ~op1_16;
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2002-09-30 07:37:42 +04:00
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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result_16 = ~op1_16;
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2002-10-25 22:26:29 +04:00
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Write_RMW_virtual_word(result_16);
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2002-09-30 07:37:42 +04:00
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}
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::OR_EwGw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op2_16, op1_16, result_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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2001-04-10 05:04:59 +04:00
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result_16 = op1_16 | op2_16;
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2002-09-30 07:37:42 +04:00
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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result_16 = op1_16 | op2_16;
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2002-10-25 22:26:29 +04:00
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Write_RMW_virtual_word(result_16);
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2002-09-30 07:37:42 +04:00
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}
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::OR_GwEw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op1_16, op2_16, result_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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2001-04-10 05:04:59 +04:00
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2002-10-03 22:12:40 +04:00
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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2002-10-08 02:51:58 +04:00
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asmOr16(result_16, op1_16, op2_16, flags32);
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setEFlagsOSZAPC(flags32);
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2002-10-03 22:12:40 +04:00
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#else
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2002-09-30 07:37:42 +04:00
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result_16 = op1_16 | op2_16;
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2002-10-03 22:12:40 +04:00
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#endif
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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BX_WRITE_16BIT_REG(i->nnn(), result_16);
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2001-04-10 05:04:59 +04:00
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2002-10-03 22:12:40 +04:00
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#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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2002-09-30 07:37:42 +04:00
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
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2002-10-03 22:12:40 +04:00
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#endif
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::OR_AXIw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2002-09-30 07:37:42 +04:00
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Bit16u op1_16, op2_16, sum_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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op1_16 = AX;
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op2_16 = i->Iw();
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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sum_16 = op1_16 | op2_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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AX = sum_16;
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2001-04-10 05:04:59 +04:00
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2002-09-30 07:37:42 +04:00
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_OR16);
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2001-04-10 05:04:59 +04:00
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}
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void
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2002-09-18 02:50:53 +04:00
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BX_CPU_C::AND_EwGw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit16u op2_16, op1_16, result_16;
|
|
|
|
|
|
|
|
op2_16 = BX_READ_16BIT_REG(i->nnn());
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|
|
|
|
|
|
|
if (i->modC0()) {
|
|
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
|
|
|
2002-09-23 21:59:18 +04:00
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-30 07:37:42 +04:00
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmAnd16(result_16, op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-23 02:22:16 +04:00
|
|
|
#else
|
2002-09-30 07:37:42 +04:00
|
|
|
result_16 = op1_16 & op2_16;
|
2002-09-28 05:48:18 +04:00
|
|
|
#endif
|
|
|
|
|
|
|
|
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
|
|
|
}
|
|
|
|
else {
|
2002-09-30 07:37:42 +04:00
|
|
|
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
|
|
|
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmAnd16(result_16, op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-30 07:37:42 +04:00
|
|
|
#else
|
|
|
|
result_16 = op1_16 & op2_16;
|
|
|
|
#endif
|
|
|
|
|
2002-10-25 22:26:29 +04:00
|
|
|
Write_RMW_virtual_word(result_16);
|
2002-09-28 05:48:18 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2002-09-18 02:50:53 +04:00
|
|
|
BX_CPU_C::AND_GwEw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit16u op1_16, op2_16, result_16;
|
|
|
|
|
|
|
|
op1_16 = BX_READ_16BIT_REG(i->nnn());
|
|
|
|
|
|
|
|
if (i->modC0()) {
|
|
|
|
op2_16 = BX_READ_16BIT_REG(i->rm());
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
|
|
|
|
}
|
|
|
|
|
2002-09-23 21:59:18 +04:00
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmAnd16(result_16, op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-23 02:22:16 +04:00
|
|
|
#else
|
2002-09-28 05:48:18 +04:00
|
|
|
result_16 = op1_16 & op2_16;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
BX_WRITE_16BIT_REG(i->nnn(), result_16);
|
|
|
|
|
|
|
|
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2002-09-18 02:50:53 +04:00
|
|
|
BX_CPU_C::AND_AXIw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit16u op1_16, op2_16, result_16;
|
|
|
|
|
|
|
|
op1_16 = AX;
|
|
|
|
op2_16 = i->Iw();
|
|
|
|
|
2002-09-23 21:59:18 +04:00
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmAnd16(result_16, op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-23 02:22:16 +04:00
|
|
|
#else
|
2002-09-28 05:48:18 +04:00
|
|
|
result_16 = op1_16 & op2_16;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
AX = result_16;
|
|
|
|
|
|
|
|
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2002-09-18 02:50:53 +04:00
|
|
|
BX_CPU_C::AND_EwIw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit16u op2_16, op1_16, result_16;
|
|
|
|
|
|
|
|
op2_16 = i->Iw();
|
|
|
|
|
|
|
|
if (i->modC0()) {
|
|
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
|
|
|
2002-09-23 21:59:18 +04:00
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-30 07:37:42 +04:00
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmAnd16(result_16, op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-23 02:22:16 +04:00
|
|
|
#else
|
2002-09-30 07:37:42 +04:00
|
|
|
result_16 = op1_16 & op2_16;
|
2002-09-28 05:48:18 +04:00
|
|
|
#endif
|
|
|
|
|
|
|
|
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
|
|
|
}
|
|
|
|
else {
|
2002-09-30 07:37:42 +04:00
|
|
|
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
|
|
|
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmAnd16(result_16, op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-30 07:37:42 +04:00
|
|
|
#else
|
|
|
|
result_16 = op1_16 & op2_16;
|
|
|
|
#endif
|
|
|
|
|
2002-10-25 22:26:29 +04:00
|
|
|
Write_RMW_virtual_word(result_16);
|
2002-09-28 05:48:18 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2002-09-18 02:50:53 +04:00
|
|
|
BX_CPU_C::TEST_EwGw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit16u op2_16, op1_16;
|
|
|
|
|
|
|
|
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
|
|
|
|
|
|
|
if (i->modC0()) {
|
|
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
|
|
}
|
|
|
|
|
2002-09-23 21:59:18 +04:00
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmTest16(op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-23 02:22:16 +04:00
|
|
|
#else
|
|
|
|
Bit16u result_16;
|
|
|
|
result_16 = op1_16 & op2_16;
|
|
|
|
|
|
|
|
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2002-09-18 02:50:53 +04:00
|
|
|
BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit16u op2_16, op1_16;
|
|
|
|
|
|
|
|
op1_16 = AX;
|
|
|
|
op2_16 = i->Iw();
|
|
|
|
|
2002-09-23 21:59:18 +04:00
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmTest16(op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-23 02:22:16 +04:00
|
|
|
#else
|
|
|
|
Bit16u result_16;
|
|
|
|
result_16 = op1_16 & op2_16;
|
|
|
|
|
|
|
|
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2002-09-18 02:50:53 +04:00
|
|
|
BX_CPU_C::TEST_EwIw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit16u op2_16, op1_16;
|
|
|
|
|
|
|
|
op2_16 = i->Iw();
|
|
|
|
|
|
|
|
if (i->modC0()) {
|
|
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
|
|
}
|
|
|
|
|
2002-09-23 21:59:18 +04:00
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
2002-09-23 02:22:16 +04:00
|
|
|
Bit32u flags32;
|
2002-10-08 02:51:58 +04:00
|
|
|
|
|
|
|
asmTest16(op1_16, op2_16, flags32);
|
|
|
|
setEFlagsOSZAPC(flags32);
|
2002-09-23 02:22:16 +04:00
|
|
|
#else
|
|
|
|
Bit16u result_16;
|
|
|
|
result_16 = op1_16 & op2_16;
|
|
|
|
|
|
|
|
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|