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Added more x86 specific asm() code to directly handle eflags return

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values for some common instructions (like test/and/cmp).  Only
  compiles in on x86 of course.
This commit is contained in:
Kevin Lawton 2002-09-22 22:22:16 +00:00
parent 4150ae197e
commit 6e7a2e91f2
7 changed files with 792 additions and 322 deletions
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147
bochs/cpu/arith16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith16.cc,v 1.16 2002-09-22 18:22:24 kevinlawton Exp $
// $Id: arith16.cc,v 1.17 2002-09-22 22:22:16 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -479,63 +479,103 @@ BX_CPU_C::SUB_AXIw(bxInstruction_c *i)
void
BX_CPU_C::CMP_EwGw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, diff_16;
Bit16u op2_16, op1_16;
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op2_16 is a register, RMAddr(i) is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn());
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpw %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit16u diff_16;
diff_16 = op1_16 - op2_16;
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
#endif
}
void
BX_CPU_C::CMP_GwEw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, diff_16;
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register, RMAddr(i) is an index of a register */
op1_16 = BX_READ_16BIT_REG(i->nnn());
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
/* op2_16 is a register or memory reference */
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpw %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit16u diff_16;
diff_16 = op1_16 - op2_16;
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
#endif
}
void
BX_CPU_C::CMP_AXIw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, diff_16;
Bit16u op1_16, op2_16;
op1_16 = AX;
op1_16 = AX;
op2_16 = i->Iw();
op2_16 = i->Iw();
diff_16 = op1_16 - op2_16;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpw %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit16u diff_16;
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
#endif
}
@ -737,23 +777,36 @@ BX_CPU_C::SUB_EwIw(bxInstruction_c *i)
void
BX_CPU_C::CMP_EwIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, diff_16;
Bit16u op2_16, op1_16;
op2_16 = i->Iw();
op2_16 = i->Iw();
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpw %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit16u diff_16;
diff_16 = op1_16 - op2_16;
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
#endif
}

148
bochs/cpu/arith32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith32.cc,v 1.18 2002-09-22 18:22:24 kevinlawton Exp $
// $Id: arith32.cc,v 1.19 2002-09-22 22:22:16 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -509,64 +509,103 @@ BX_CPU_C::SUB_EAXId(bxInstruction_c *i)
void
BX_CPU_C::CMP_EdGd(bxInstruction_c *i)
{
/* for 32 bit operand size mode */
Bit32u op2_32, op1_32, diff_32;
Bit32u op2_32, op1_32;
/* op2_32 is a register, RMAddr(i) is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
diff_32 = op1_32 - op2_32;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpl %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit32u diff_32;
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
#endif
}
void
BX_CPU_C::CMP_GdEd(bxInstruction_c *i)
{
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32, diff_32;
Bit32u op1_32, op2_32;
/* op1_32 is a register, RMAddr(i) is an index of a register */
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->nnn());
/* op2_32 is a register or memory reference */
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
diff_32 = op1_32 - op2_32;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpl %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit32u diff_32;
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
#endif
}
void
BX_CPU_C::CMP_EAXId(bxInstruction_c *i)
{
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32, diff_32;
Bit32u op1_32, op2_32;
op1_32 = EAX;
op1_32 = EAX;
op2_32 = i->Id();
op2_32 = i->Id();
diff_32 = op1_32 - op2_32;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpl %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit32u diff_32;
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
#endif
}
@ -800,23 +839,36 @@ BX_CPU_C::SUB_EdId(bxInstruction_c *i)
void
BX_CPU_C::CMP_EdId(bxInstruction_c *i)
{
/* for 32 bit operand size mode */
Bit32u op2_32, op1_32, diff_32;
Bit32u op2_32, op1_32;
op2_32 = i->Id();
op2_32 = i->Id();
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
diff_32 = op1_32 - op2_32;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpl %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit32u diff_32;
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
#endif
}

84
bochs/cpu/arith8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith8.cc,v 1.12 2002-09-22 18:22:24 kevinlawton Exp $
// $Id: arith8.cc,v 1.13 2002-09-22 22:22:16 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -409,47 +409,72 @@ BX_CPU_C::SUB_ALIb(bxInstruction_c *i)
void
BX_CPU_C::CMP_EbGb(bxInstruction_c *i)
{
Bit8u op2_8, op1_8, diff_8;
Bit8u op2_8, op1_8;
/* op2 is a register, RMAddr(i) is an index of a register */
op2_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op1_8 is a register or memory reference */
if (i->modC0()) {
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op1_8);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpb %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_8), "g" (op2_8)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit8u diff_8;
diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMP8);
#endif
}
void
BX_CPU_C::CMP_GbEb(bxInstruction_c *i)
{
Bit8u op1_8, op2_8, diff_8;
Bit8u op1_8, op2_8;
/* op1 is a register, RMAddr(i) is an index of a register */
op1_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op2 is a register or memory reference */
if (i->modC0()) {
op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpb %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_8), "g" (op2_8)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit8u diff_8;
diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMP8);
#endif
}
@ -457,16 +482,31 @@ BX_CPU_C::CMP_GbEb(bxInstruction_c *i)
void
BX_CPU_C::CMP_ALIb(bxInstruction_c *i)
{
Bit8u op1_8, op2_8, diff_8;
Bit8u op1_8, op2_8;
op1_8 = AL;
op2_8 = i->Ib();
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpb %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_8), "g" (op2_8)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit8u diff_8;
diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMP8);
#endif
}
@ -617,22 +657,36 @@ BX_CPU_C::SUB_EbIb(bxInstruction_c *i)
void
BX_CPU_C::CMP_EbIb(bxInstruction_c *i)
{
Bit8u op2_8, op1_8, diff_8;
Bit8u op2_8, op1_8;
op2_8 = i->Ib();
/* op1_8 is a register or memory reference */
if (i->modC0()) {
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op1_8);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"cmpb %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_8), "g" (op2_8)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit8u diff_8;
diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMP8);
#endif
}

5
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.72 2002-09-22 19:06:46 bdenney Exp $
// $Id: cpu.h,v 1.73 2002-09-22 22:22:16 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -446,6 +446,9 @@ typedef struct {
return 3 & (BX_CPU_THIS_PTR eflags.val32 >> 12); \
}
#define EFlagsOSZAPCMask 0x000008d5
#define EFlagsOSZAPMask 0x000008d4
} bx_flags_reg_t;

294
bochs/cpu/logical16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical16.cc,v 1.9 2002-09-20 03:52:58 kevinlawton Exp $
// $Id: logical16.cc,v 1.10 2002-09-22 22:22:16 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -278,130 +278,196 @@ BX_CPU_C::OR_AXIw(bxInstruction_c *i)
void
BX_CPU_C::AND_EwGw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, result_16;
Bit16u op2_16, op1_16, result_16;
op2_16 = BX_READ_16BIT_REG(i->nnn());
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
/* op2_16 is a register, op2_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn());
result_16 = op1_16 & op2_16;
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
Write_RMW_virtual_word(result_16);
}
result_16 = op1_16 & op2_16;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
Write_RMW_virtual_word(result_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andw %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
#endif
}
void
BX_CPU_C::AND_GwEw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, result_16;
Bit16u op1_16, op2_16, result_16;
op1_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->nnn());
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
/* op2_16 is a register or memory reference */
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
result_16 = op1_16 & op2_16;
result_16 = op1_16 & op2_16;
BX_WRITE_16BIT_REG(i->nnn(), result_16);
/* now write result back to destination */
BX_WRITE_16BIT_REG(i->nnn(), result_16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andw %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
#endif
}
void
BX_CPU_C::AND_AXIw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, sum_16;
Bit16u op1_16, op2_16, result_16;
op1_16 = AX;
op1_16 = AX;
op2_16 = i->Iw();
op2_16 = i->Iw();
sum_16 = op1_16 & op2_16;
result_16 = op1_16 & op2_16;
/* now write sum back to destination */
AX = sum_16;
AX = result_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_AND16);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andw %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
#endif
}
void
BX_CPU_C::AND_EwIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, result_16;
Bit16u op2_16, op1_16, result_16;
op2_16 = i->Iw();
op2_16 = i->Iw();
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
result_16 = op1_16 & op2_16;
result_16 = op1_16 & op2_16;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
Write_RMW_virtual_word(result_16);
}
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
Write_RMW_virtual_word(result_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andw %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
#endif
}
void
BX_CPU_C::TEST_EwGw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, result_16;
Bit16u op2_16, op1_16;
/* op2_16 is a register, op2_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op2_16 is a register, op2_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testw %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit16u result_16;
result_16 = op1_16 & op2_16;
result_16 = op1_16 & op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
#endif
}
@ -409,38 +475,70 @@ BX_CPU_C::TEST_EwGw(bxInstruction_c *i)
void
BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, result_16;
Bit16u op2_16, op1_16;
op1_16 = AX;
op1_16 = AX;
/* op2_16 is imm16 */
op2_16 = i->Iw();
/* op2_16 is imm16 */
op2_16 = i->Iw();
result_16 = op1_16 & op2_16;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testw %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit16u result_16;
result_16 = op1_16 & op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
#endif
}
void
BX_CPU_C::TEST_EwIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, result_16;
Bit16u op2_16, op1_16;
op2_16 = i->Iw();
/* op2_16 is imm16 */
op2_16 = i->Iw();
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testw %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit16u result_16;
result_16 = op1_16 & op2_16;
result_16 = op1_16 & op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
#endif
}

295
bochs/cpu/logical32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical32.cc,v 1.10 2002-09-20 03:52:58 kevinlawton Exp $
// $Id: logical32.cc,v 1.11 2002-09-22 22:22:16 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -283,130 +283,201 @@ BX_CPU_C::OR_EAXId(bxInstruction_c *i)
void
BX_CPU_C::AND_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
result_32 = op1_32 & op2_32;
result_32 = op1_32 & op2_32;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
Write_RMW_virtual_dword(result_32);
}
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
Write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
#endif
}
void
BX_CPU_C::AND_GdEd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, result_32;
Bit32u op1_32, op2_32, result_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->nnn());
/* op2_32 is a register or memory reference */
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
result_32 = op1_32 & op2_32;
result_32 = op1_32 & op2_32;
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
#endif
}
void
BX_CPU_C::AND_EAXId(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
Bit32u op1_32, op2_32, result_32;
op1_32 = EAX;
op1_32 = EAX;
op2_32 = i->Id();
op2_32 = i->Id();
sum_32 = op1_32 & op2_32;
result_32 = op1_32 & op2_32;
/* now write sum back to destination */
#if BX_SUPPORT_X86_64
RAX = sum_32;
RAX = result_32;
#else
EAX = sum_32;
EAX = result_32;
#endif
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_AND32);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
#endif
}
void
BX_CPU_C::AND_EdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id();
op2_32 = i->Id();
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
result_32 = op1_32 & op2_32;
result_32 = op1_32 & op2_32;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
Write_RMW_virtual_dword(result_32);
}
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
Write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
#endif
}
void
BX_CPU_C::TEST_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
Bit32u op2_32, op1_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
result_32 = op1_32 & op2_32;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testl %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit32u result_32;
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
#endif
}
@ -414,38 +485,72 @@ BX_CPU_C::TEST_EdGd(bxInstruction_c *i)
void
BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
Bit32u op2_32, op1_32;
/* op1 is EAX register */
op1_32 = EAX;
/* op1 is EAX register */
op1_32 = EAX;
/* op2 is imm32 */
op2_32 = i->Id();
/* op2 is imm32 */
op2_32 = i->Id();
result_32 = op1_32 & op2_32;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testl %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit32u result_32;
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
#endif
}
void
BX_CPU_C::TEST_EdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
Bit32u op2_32, op1_32;
/* op2 is imm32 */
op2_32 = i->Id();
/* op2 is imm32 */
op2_32 = i->Id();
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
result_32 = op1_32 & op2_32;
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testl %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit32u result_32;
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
#endif
}

141
bochs/cpu/logical8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical8.cc,v 1.10 2002-09-20 03:52:58 kevinlawton Exp $
// $Id: logical8.cc,v 1.11 2002-09-22 22:22:16 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -280,10 +280,8 @@ BX_CPU_C::AND_EbGb(bxInstruction_c *i)
{
Bit8u op2, op1, result;
/* op2 is a register, op2_addr is an index of a register */
op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op1 is a register or memory reference */
if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
@ -294,7 +292,6 @@ BX_CPU_C::AND_EbGb(bxInstruction_c *i)
result = op1 & op2;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result);
}
@ -302,7 +299,23 @@ BX_CPU_C::AND_EbGb(bxInstruction_c *i)
Write_RMW_virtual_byte(result);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result)
: "1" (op1), "g" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_AND8);
#endif
}
@ -313,40 +326,68 @@ BX_CPU_C::AND_GbEb(bxInstruction_c *i)
op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2);
}
result = op1 & op2;
/* now write result back to destination, which is a register */
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), result);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result)
: "1" (op1), "g" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_AND8);
#endif
}
void
BX_CPU_C::AND_ALIb(bxInstruction_c *i)
{
Bit8u op1, op2, sum;
Bit8u op1, op2, result;
op1 = AL;
op2 = i->Ib();
sum = op1 & op2;
result = op1 & op2;
/* now write sum back to destination, which is a register */
AL = sum;
AL = result;
SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_AND8);
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result)
: "1" (op1), "g" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_AND8);
#endif
}
@ -360,18 +401,15 @@ BX_CPU_C::AND_EbIb(bxInstruction_c *i)
op2 = i->Ib();
/* op1 is a register or memory reference */
if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
}
result = op1 & op2;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result);
}
@ -379,14 +417,30 @@ BX_CPU_C::AND_EbIb(bxInstruction_c *i)
Write_RMW_virtual_byte(result);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result)
: "1" (op1), "g" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_AND8);
#endif
}
void
BX_CPU_C::TEST_EbGb(bxInstruction_c *i)
{
Bit8u op2, op1, result;
Bit8u op2, op1;
/* op2 is a register, op2_addr is an index of a register */
op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
@ -400,16 +454,33 @@ BX_CPU_C::TEST_EbGb(bxInstruction_c *i)
read_virtual_byte(i->seg(), RMAddr(i), &op1);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testb %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1), "g" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit8u result;
result = op1 & op2;
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_TEST8);
#endif
}
void
BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
{
Bit8u op2, op1, result;
Bit8u op2, op1;
/* op1 is the AL register */
op1 = AL;
@ -417,9 +488,26 @@ BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
/* op2 is imm8 */
op2 = i->Ib();
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testb %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1), "g" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit8u result;
result = op1 & op2;
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_TEST8);
#endif
}
@ -427,7 +515,7 @@ BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
void
BX_CPU_C::TEST_EbIb(bxInstruction_c *i)
{
Bit8u op2, op1, result;
Bit8u op2, op1;
op2 = i->Ib();
@ -440,7 +528,24 @@ BX_CPU_C::TEST_EbIb(bxInstruction_c *i)
read_virtual_byte(i->seg(), RMAddr(i), &op1);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm (
"testb %2, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1), "g" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
Bit8u result;
result = op1 & op2;
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_TEST8);
#endif
}