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Bochs/bochs/cpu/fetchdecode64.cc

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Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/////////////////////////////////////////////////////////////////////////
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
// $Id: fetchdecode64.cc,v 1.18 2002-09-28 00:54:05 kevinlawton Exp $
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
//
// MandrakeSoft S.A.
// 43, rue d'Aboukir
// 75002 Paris - France
// http://www.linux-mandrake.com/
// http://www.mandrakesoft.com/
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
///////////////////////////
// prefix bytes
// opcode bytes
// modrm/sib
// address displacement
// immediate constant
///////////////////////////
// sign extended to osize:
// 6a push ib
// 6b imul gvevib
// 70..7f jo..jnle
// 83 G1 0..7 ADD..CMP Evib
// is 6b imul_gvevib sign extended? don't think
// I'm sign extending it properly in old decode/execute
//check all the groups. Make sure to add duplicates rather
// than error.
// mark instructions as changing control transfer, then
// don't always load from fetch_ptr, etc.
// cant use immediate as another because of Group3 where
// some have immediate and some don't, and those won't
// be picked up by logic until indirection.
// get attr and execute ptr at same time
// maybe move 16bit only i's like MOV_EwSw, MOV_SwEw
// to 32 bit modules.
// use 0F as a prefix too?
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
void BxResolveError(bxInstruction_c *);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
#if BX_DYNAMIC_TRANSLATION
// For 16-bit address mode, this matrix describes the registers
// used to formulate the offset, indexed by the RM field.
// This info is needed by the dynamic translation code for dataflow.
static unsigned BxMemRegsUsed16[8] = {
(1<<3) | (1<<6), // BX + SI
(1<<3) | (1<<7), // BX + DI
(1<<5) | (1<<6), // BP + SI
(1<<5) | (1<<7), // BP + DI
(1<<6), // SI
(1<<7), // DI
(1<<5), // BP
(1<<3) // BX
};
#endif
static BxExecutePtr_t BxResolve32Mod0[8] = {
&BX_CPU_C::Resolve32Mod0Rm0,
&BX_CPU_C::Resolve32Mod0Rm1,
&BX_CPU_C::Resolve32Mod0Rm2,
&BX_CPU_C::Resolve32Mod0Rm3,
NULL, // escape to 2-byte
- Added an instruction cache. Size is fixed for the moment, but if you hand edit cpu/cpu.h, and change BxICacheEntries, you can try different sizes. I'll make this more flexible with configure. For now, use "--enable-icache" with no parameters. - Modified fetchdecode.cc/fetchdecode64.cc just enough so that instructions which encode a direct address now use a memory resolution function which just sticks the immediate address into rm_addr. With cached instructions we need this.
2002-09-19 23:17:20 +04:00
&BX_CPU_C::Resolve32Mod0Rm5,
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
&BX_CPU_C::Resolve32Mod0Rm6,
&BX_CPU_C::Resolve32Mod0Rm7
};
static BxExecutePtr_t BxResolve32Mod1or2[8] = {
&BX_CPU_C::Resolve32Mod1or2Rm0,
&BX_CPU_C::Resolve32Mod1or2Rm1,
&BX_CPU_C::Resolve32Mod1or2Rm2,
&BX_CPU_C::Resolve32Mod1or2Rm3,
NULL, // escape to 2-byte
&BX_CPU_C::Resolve32Mod1or2Rm5,
&BX_CPU_C::Resolve32Mod1or2Rm6,
&BX_CPU_C::Resolve32Mod1or2Rm7
};
static BxExecutePtr_t BxResolve32Mod0Base[8] = {
&BX_CPU_C::Resolve32Mod0Base0,
&BX_CPU_C::Resolve32Mod0Base1,
&BX_CPU_C::Resolve32Mod0Base2,
&BX_CPU_C::Resolve32Mod0Base3,
&BX_CPU_C::Resolve32Mod0Base4,
&BX_CPU_C::Resolve32Mod0Base5,
&BX_CPU_C::Resolve32Mod0Base6,
&BX_CPU_C::Resolve32Mod0Base7,
};
static BxExecutePtr_t BxResolve32Mod1or2Base[8] = {
&BX_CPU_C::Resolve32Mod1or2Base0,
&BX_CPU_C::Resolve32Mod1or2Base1,
&BX_CPU_C::Resolve32Mod1or2Base2,
&BX_CPU_C::Resolve32Mod1or2Base3,
&BX_CPU_C::Resolve32Mod1or2Base4,
&BX_CPU_C::Resolve32Mod1or2Base5,
&BX_CPU_C::Resolve32Mod1or2Base6,
&BX_CPU_C::Resolve32Mod1or2Base7,
};
static BxExecutePtr_t BxResolve64Mod0[16] = {
&BX_CPU_C::Resolve64Mod0Rm0,
&BX_CPU_C::Resolve64Mod0Rm1,
&BX_CPU_C::Resolve64Mod0Rm2,
&BX_CPU_C::Resolve64Mod0Rm3,
NULL, // escape to 2-byte
&BX_CPU_C::Resolve64Mod0Rm5,
&BX_CPU_C::Resolve64Mod0Rm6,
&BX_CPU_C::Resolve64Mod0Rm7,
&BX_CPU_C::Resolve64Mod0Rm8,
&BX_CPU_C::Resolve64Mod0Rm9,
&BX_CPU_C::Resolve64Mod0Rm10,
&BX_CPU_C::Resolve64Mod0Rm11,
&BX_CPU_C::Resolve64Mod0Rm12,
&BX_CPU_C::Resolve64Mod0Rm13,
&BX_CPU_C::Resolve64Mod0Rm14,
&BX_CPU_C::Resolve64Mod0Rm15
};
static BxExecutePtr_t BxResolve64Mod1or2[16] = {
&BX_CPU_C::Resolve64Mod1or2Rm0,
&BX_CPU_C::Resolve64Mod1or2Rm1,
&BX_CPU_C::Resolve64Mod1or2Rm2,
&BX_CPU_C::Resolve64Mod1or2Rm3,
NULL, // escape to 2-byte
&BX_CPU_C::Resolve64Mod1or2Rm5,
&BX_CPU_C::Resolve64Mod1or2Rm6,
&BX_CPU_C::Resolve64Mod1or2Rm7,
&BX_CPU_C::Resolve64Mod1or2Rm8,
&BX_CPU_C::Resolve64Mod1or2Rm9,
&BX_CPU_C::Resolve64Mod1or2Rm10,
&BX_CPU_C::Resolve64Mod1or2Rm11,
&BX_CPU_C::Resolve64Mod1or2Rm12,
&BX_CPU_C::Resolve64Mod1or2Rm13,
&BX_CPU_C::Resolve64Mod1or2Rm14,
&BX_CPU_C::Resolve64Mod1or2Rm15
};
static BxExecutePtr_t BxResolve64Mod0Base[16] = {
&BX_CPU_C::Resolve64Mod0Base0,
&BX_CPU_C::Resolve64Mod0Base1,
&BX_CPU_C::Resolve64Mod0Base2,
&BX_CPU_C::Resolve64Mod0Base3,
&BX_CPU_C::Resolve64Mod0Base4,
&BX_CPU_C::Resolve64Mod0Base5,
&BX_CPU_C::Resolve64Mod0Base6,
&BX_CPU_C::Resolve64Mod0Base7,
&BX_CPU_C::Resolve64Mod0Base8,
&BX_CPU_C::Resolve64Mod0Base9,
&BX_CPU_C::Resolve64Mod0Base10,
&BX_CPU_C::Resolve64Mod0Base11,
&BX_CPU_C::Resolve64Mod0Base12,
&BX_CPU_C::Resolve64Mod0Base13,
&BX_CPU_C::Resolve64Mod0Base14,
&BX_CPU_C::Resolve64Mod0Base15,
};
static BxExecutePtr_t BxResolve64Mod1or2Base[16] = {
&BX_CPU_C::Resolve64Mod1or2Base0,
&BX_CPU_C::Resolve64Mod1or2Base1,
&BX_CPU_C::Resolve64Mod1or2Base2,
&BX_CPU_C::Resolve64Mod1or2Base3,
&BX_CPU_C::Resolve64Mod1or2Base4,
&BX_CPU_C::Resolve64Mod1or2Base5,
&BX_CPU_C::Resolve64Mod1or2Base6,
&BX_CPU_C::Resolve64Mod1or2Base7,
&BX_CPU_C::Resolve64Mod1or2Base8,
&BX_CPU_C::Resolve64Mod1or2Base9,
&BX_CPU_C::Resolve64Mod1or2Base10,
&BX_CPU_C::Resolve64Mod1or2Base11,
&BX_CPU_C::Resolve64Mod1or2Base12,
&BX_CPU_C::Resolve64Mod1or2Base13,
&BX_CPU_C::Resolve64Mod1or2Base14,
&BX_CPU_C::Resolve64Mod1or2Base15,
};
typedef struct BxOpcodeInfo_t {
Bit16u Attr;
BxExecutePtr_t ExecutePtr;
struct BxOpcodeInfo_t *AnotherArray;
} BxOpcodeInfo_t;
static BxOpcodeInfo_t BxOpcodeInfo64G1EbIb[8] = {
/* 0 */ { BxImmediate_Ib, &BX_CPU_C::ADD_EbIb },
/* 1 */ { BxImmediate_Ib, &BX_CPU_C::OR_EbIb },
/* 2 */ { BxImmediate_Ib, &BX_CPU_C::ADC_EbIb },
/* 3 */ { BxImmediate_Ib, &BX_CPU_C::SBB_EbIb },
/* 4 */ { BxImmediate_Ib, &BX_CPU_C::AND_EbIb },
/* 5 */ { BxImmediate_Ib, &BX_CPU_C::SUB_EbIb },
/* 6 */ { BxImmediate_Ib, &BX_CPU_C::XOR_EbIb },
/* 7 */ { BxImmediate_Ib, &BX_CPU_C::CMP_EbIb }
};
static BxOpcodeInfo_t BxOpcodeInfo64G1Ew[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ADD_EwIw },
/* 1 */ { 0, &BX_CPU_C::OR_EwIw },
/* 2 */ { 0, &BX_CPU_C::ADC_EwIw },
/* 3 */ { 0, &BX_CPU_C::SBB_EwIw },
/* 4 */ { 0, &BX_CPU_C::AND_EwIw },
/* 5 */ { 0, &BX_CPU_C::SUB_EwIw },
/* 6 */ { 0, &BX_CPU_C::XOR_EwIw },
/* 7 */ { 0, &BX_CPU_C::CMP_EwIw }
};
static BxOpcodeInfo_t BxOpcodeInfo64G1Ed[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ADD_EdId },
/* 1 */ { 0, &BX_CPU_C::OR_EdId },
/* 2 */ { 0, &BX_CPU_C::ADC_EdId },
/* 3 */ { 0, &BX_CPU_C::SBB_EdId },
/* 4 */ { 0, &BX_CPU_C::AND_EdId },
/* 5 */ { 0, &BX_CPU_C::SUB_EdId },
/* 6 */ { 0, &BX_CPU_C::XOR_EdId },
/* 7 */ { 0, &BX_CPU_C::CMP_EdId }
};
static BxOpcodeInfo_t BxOpcodeInfo64G1Eq[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ADD_EqId },
/* 1 */ { 0, &BX_CPU_C::OR_EqId },
/* 2 */ { 0, &BX_CPU_C::ADC_EqId },
/* 3 */ { 0, &BX_CPU_C::SBB_EqId },
/* 4 */ { 0, &BX_CPU_C::AND_EqId },
/* 5 */ { 0, &BX_CPU_C::SUB_EqId },
/* 6 */ { 0, &BX_CPU_C::XOR_EqId },
/* 7 */ { 0, &BX_CPU_C::CMP_EqId }
};
static BxOpcodeInfo_t BxOpcodeInfo64G2Eb[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ROL_Eb },
/* 1 */ { 0, &BX_CPU_C::ROR_Eb },
/* 2 */ { 0, &BX_CPU_C::RCL_Eb },
/* 3 */ { 0, &BX_CPU_C::RCR_Eb },
/* 4 */ { 0, &BX_CPU_C::SHL_Eb },
/* 5 */ { 0, &BX_CPU_C::SHR_Eb },
/* 6 */ { 0, &BX_CPU_C::SHL_Eb },
/* 7 */ { 0, &BX_CPU_C::SAR_Eb }
};
static BxOpcodeInfo_t BxOpcodeInfo64G2Ew[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ROL_Ew },
/* 1 */ { 0, &BX_CPU_C::ROR_Ew },
/* 2 */ { 0, &BX_CPU_C::RCL_Ew },
/* 3 */ { 0, &BX_CPU_C::RCR_Ew },
/* 4 */ { 0, &BX_CPU_C::SHL_Ew },
/* 5 */ { 0, &BX_CPU_C::SHR_Ew },
/* 6 */ { 0, &BX_CPU_C::SHL_Ew },
/* 7 */ { 0, &BX_CPU_C::SAR_Ew }
};
static BxOpcodeInfo_t BxOpcodeInfo64G2Ed[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ROL_Ed },
/* 1 */ { 0, &BX_CPU_C::ROR_Ed },
/* 2 */ { 0, &BX_CPU_C::RCL_Ed },
/* 3 */ { 0, &BX_CPU_C::RCR_Ed },
/* 4 */ { 0, &BX_CPU_C::SHL_Ed },
/* 5 */ { 0, &BX_CPU_C::SHR_Ed },
/* 6 */ { 0, &BX_CPU_C::SHL_Ed },
/* 7 */ { 0, &BX_CPU_C::SAR_Ed }
};
static BxOpcodeInfo_t BxOpcodeInfo64G2Eq[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ROL_Eq },
/* 1 */ { 0, &BX_CPU_C::ROR_Eq },
/* 2 */ { 0, &BX_CPU_C::RCL_Eq },
/* 3 */ { 0, &BX_CPU_C::RCR_Eq },
/* 4 */ { 0, &BX_CPU_C::SHL_Eq },
/* 5 */ { 0, &BX_CPU_C::SHR_Eq },
/* 6 */ { 0, &BX_CPU_C::SHL_Eq },
/* 7 */ { 0, &BX_CPU_C::SAR_Eq }
};
static BxOpcodeInfo_t BxOpcodeInfo64G3Eb[8] = {
/* 0 */ { BxImmediate_Ib, &BX_CPU_C::TEST_EbIb },
/* 1 */ { BxImmediate_Ib, &BX_CPU_C::TEST_EbIb },
/* 2 */ { 0, &BX_CPU_C::NOT_Eb },
/* 3 */ { 0, &BX_CPU_C::NEG_Eb },
/* 4 */ { 0, &BX_CPU_C::MUL_ALEb },
/* 5 */ { 0, &BX_CPU_C::IMUL_ALEb },
/* 6 */ { 0, &BX_CPU_C::DIV_ALEb },
/* 7 */ { 0, &BX_CPU_C::IDIV_ALEb }
};
static BxOpcodeInfo_t BxOpcodeInfo64G3Ew[8] = {
/* 0 */ { BxImmediate_Iw, &BX_CPU_C::TEST_EwIw },
/* 1 */ { BxImmediate_Iw, &BX_CPU_C::TEST_EwIw },
/* 2 */ { 0, &BX_CPU_C::NOT_Ew },
/* 3 */ { 0, &BX_CPU_C::NEG_Ew },
/* 4 */ { 0, &BX_CPU_C::MUL_AXEw },
/* 5 */ { 0, &BX_CPU_C::IMUL_AXEw },
/* 6 */ { 0, &BX_CPU_C::DIV_AXEw },
/* 7 */ { 0, &BX_CPU_C::IDIV_AXEw }
};
static BxOpcodeInfo_t BxOpcodeInfo64G3Ed[8] = {
/* 0 */ { BxImmediate_Iv, &BX_CPU_C::TEST_EdId },
/* 1 */ { BxImmediate_Iv, &BX_CPU_C::TEST_EdId },
/* 2 */ { 0, &BX_CPU_C::NOT_Ed },
/* 3 */ { 0, &BX_CPU_C::NEG_Ed },
/* 4 */ { 0, &BX_CPU_C::MUL_EAXEd },
/* 5 */ { 0, &BX_CPU_C::IMUL_EAXEd },
/* 6 */ { 0, &BX_CPU_C::DIV_EAXEd },
/* 7 */ { 0, &BX_CPU_C::IDIV_EAXEd }
};
static BxOpcodeInfo_t BxOpcodeInfo64G3Eq[8] = {
/* 0 */ { BxImmediate_Iv, &BX_CPU_C::TEST_EqId },
/* 1 */ { BxImmediate_Iv, &BX_CPU_C::TEST_EqId },
/* 2 */ { 0, &BX_CPU_C::NOT_Eq },
/* 3 */ { 0, &BX_CPU_C::NEG_Eq },
/* 4 */ { 0, &BX_CPU_C::MUL_RAXEq },
/* 5 */ { 0, &BX_CPU_C::IMUL_RAXEq },
/* 6 */ { 0, &BX_CPU_C::DIV_RAXEq },
/* 7 */ { 0, &BX_CPU_C::IDIV_RAXEq }
};
static BxOpcodeInfo_t BxOpcodeInfo64G4[8] = {
/* 0 */ { 0, &BX_CPU_C::INC_Eb },
/* 1 */ { 0, &BX_CPU_C::DEC_Eb },
/* 2 */ { 0, &BX_CPU_C::BxError },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { 0, &BX_CPU_C::BxError },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { 0, &BX_CPU_C::BxError },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t BxOpcodeInfo64G5w[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::INC_Ew },
/* 1 */ { 0, &BX_CPU_C::DEC_Ew },
/* 2 */ { 0, &BX_CPU_C::CALL_Ew }, // invalid??
/* 3 */ { 0, &BX_CPU_C::CALL16_Ep }, // invalid??
/* 4 */ { 0, &BX_CPU_C::JMP_Eq }, // invalid??
/* 5 */ { 0, &BX_CPU_C::JMP16_Ep }, // invalid??
/* 6 */ { 0, &BX_CPU_C::PUSH_Ew },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t BxOpcodeInfo64G5d[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::INC_Ed },
/* 1 */ { 0, &BX_CPU_C::DEC_Ed },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::CALL32_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::JMP32_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_Eq },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t BxOpcodeInfo64G5q[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::INC_Eq },
/* 1 */ { 0, &BX_CPU_C::DEC_Eq },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::CALL64_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::JMP64_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_Eq },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t BxOpcodeInfo64G6[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::SLDT_Ew },
/* 1 */ { 0, &BX_CPU_C::STR_Ew },
/* 2 */ { 0, &BX_CPU_C::LLDT_Ew },
/* 3 */ { 0, &BX_CPU_C::LTR_Ew },
/* 4 */ { 0, &BX_CPU_C::VERR_Ew },
/* 5 */ { 0, &BX_CPU_C::VERW_Ew },
/* 6 */ { 0, &BX_CPU_C::BxError },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t BxOpcodeInfo64G7[8] = {
/* 0 */ { 0, &BX_CPU_C::SGDT_Ms },
/* 1 */ { 0, &BX_CPU_C::SIDT_Ms },
/* 2 */ { 0, &BX_CPU_C::LGDT_Ms },
/* 3 */ { 0, &BX_CPU_C::LIDT_Ms },
/* 4 */ { 0, &BX_CPU_C::SMSW_Ew },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { 0, &BX_CPU_C::LMSW_Ew },
/* 7 */ { 0, &BX_CPU_C::INVLPG }
};
static BxOpcodeInfo_t BxOpcodeInfo64G8EvIb[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
/* 2 */ { 0, &BX_CPU_C::BxError },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { BxImmediate_Ib, &BX_CPU_C::BT_EvIb },
/* 5 */ { BxImmediate_Ib, &BX_CPU_C::BTS_EvIb },
/* 6 */ { BxImmediate_Ib, &BX_CPU_C::BTR_EvIb },
/* 7 */ { BxImmediate_Ib, &BX_CPU_C::BTC_EvIb }
};
static BxOpcodeInfo_t BxOpcodeInfo64G9[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::CMPXCHG8B },
/* 2 */ { 0, &BX_CPU_C::BxError },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { 0, &BX_CPU_C::BxError },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { 0, &BX_CPU_C::BxError },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t BxOpcodeInfo64G15[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
/* 2 */ { 0, &BX_CPU_C::BxError },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { 0, &BX_CPU_C::BxError },
/* 5 */ { 0, &BX_CPU_C::NOP }, // rfence
/* 6 */ { 0, &BX_CPU_C::NOP }, // mfence
/* 7 */ { 0, &BX_CPU_C::NOP } // sfence
};
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
#if BX_SUPPORT_MMX
static BxOpcodeInfo_t BxOpcodeInfoGAw[8] = { /* MMX */
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
/* 2 */ { BxImmediate_Ib, &BX_CPU_C::PSRLW_PqIb },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { BxImmediate_Ib, &BX_CPU_C::PSRAW_PqIb },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { BxImmediate_Ib, &BX_CPU_C::PSLLW_PqIb },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t BxOpcodeInfoGAd[8] = { /* MMX */
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
/* 2 */ { BxImmediate_Ib, &BX_CPU_C::PSRLD_PqIb },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { BxImmediate_Ib, &BX_CPU_C::PSRAD_PqIb },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { BxImmediate_Ib, &BX_CPU_C::PSLLD_PqIb },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t BxOpcodeInfoGAq[8] = { /* MMX */
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
/* 2 */ { BxImmediate_Ib, &BX_CPU_C::PSRLQ_PqIb },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { 0, &BX_CPU_C::BxError },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { BxImmediate_Ib, &BX_CPU_C::PSLLQ_PqIb },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
#endif
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
// 512 entries for 16bit mode
// 512 entries for 32bit mode
// 512 entries for 64bit mode
static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
// 512 entries for 16bit mode
/* 00 */ { BxAnother, &BX_CPU_C::ADD_EbGb },
/* 01 */ { BxAnother, &BX_CPU_C::ADD_EwGw },
/* 02 */ { BxAnother, &BX_CPU_C::ADD_GbEb },
/* 03 */ { BxAnother, &BX_CPU_C::ADD_GwEw },
/* 04 */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 */ { BxImmediate_Iv, &BX_CPU_C::ADD_AXIw },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 06 */ { 0, &BX_CPU_C::BxError },
/* 07 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 08 */ { BxAnother, &BX_CPU_C::OR_EbGb },
/* 09 */ { BxAnother, &BX_CPU_C::OR_EwGw },
/* 0A */ { BxAnother, &BX_CPU_C::OR_GbEb },
/* 0B */ { BxAnother, &BX_CPU_C::OR_GwEw },
/* 0C */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
/* 0D */ { BxImmediate_Iv, &BX_CPU_C::OR_AXIw },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 0E */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F */ { BxAnother, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 */ { BxAnother, &BX_CPU_C::ADC_EbGb },
/* 11 */ { BxAnother, &BX_CPU_C::ADC_EwGw },
/* 12 */ { BxAnother, &BX_CPU_C::ADC_GbEb },
/* 13 */ { BxAnother, &BX_CPU_C::ADC_GwEw },
/* 14 */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 */ { BxImmediate_Iv, &BX_CPU_C::ADC_AXIw },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 16 */ { 0, &BX_CPU_C::BxError },
/* 17 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 18 */ { BxAnother, &BX_CPU_C::SBB_EbGb },
/* 19 */ { BxAnother, &BX_CPU_C::SBB_EwGw },
/* 1A */ { BxAnother, &BX_CPU_C::SBB_GbEb },
/* 1B */ { BxAnother, &BX_CPU_C::SBB_GwEw },
/* 1C */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
/* 1D */ { BxImmediate_Iv, &BX_CPU_C::SBB_AXIw },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 1E */ { 0, &BX_CPU_C::BxError },
/* 1F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 20 */ { BxAnother, &BX_CPU_C::AND_EbGb },
/* 21 */ { BxAnother, &BX_CPU_C::AND_EwGw },
/* 22 */ { BxAnother, &BX_CPU_C::AND_GbEb },
/* 23 */ { BxAnother, &BX_CPU_C::AND_GwEw },
/* 24 */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
/* 25 */ { BxImmediate_Iv, &BX_CPU_C::AND_AXIw },
/* 26 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // ES:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 27 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 28 */ { BxAnother, &BX_CPU_C::SUB_EbGb },
/* 29 */ { BxAnother, &BX_CPU_C::SUB_EwGw },
/* 2A */ { BxAnother, &BX_CPU_C::SUB_GbEb },
/* 2B */ { BxAnother, &BX_CPU_C::SUB_GwEw },
/* 2C */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
/* 2D */ { BxImmediate_Iv, &BX_CPU_C::SUB_AXIw },
/* 2E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // CS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 2F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 30 */ { BxAnother, &BX_CPU_C::XOR_EbGb },
/* 31 */ { BxAnother, &BX_CPU_C::XOR_EwGw },
/* 32 */ { BxAnother, &BX_CPU_C::XOR_GbEb },
/* 33 */ { BxAnother, &BX_CPU_C::XOR_GwEw },
/* 34 */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
/* 35 */ { BxImmediate_Iv, &BX_CPU_C::XOR_AXIw },
/* 36 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // SS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 37 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 38 */ { BxAnother, &BX_CPU_C::CMP_EbGb },
/* 39 */ { BxAnother, &BX_CPU_C::CMP_EwGw },
/* 3A */ { BxAnother, &BX_CPU_C::CMP_GbEb },
/* 3B */ { BxAnother, &BX_CPU_C::CMP_GwEw },
/* 3C */ { BxImmediate_Ib, &BX_CPU_C::CMP_ALIb },
/* 3D */ { BxImmediate_Iv, &BX_CPU_C::CMP_AXIw },
/* 3E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // DS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 3F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 40 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 41 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 42 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 43 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 44 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 45 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 46 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 47 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 48 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 49 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4A */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4B */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4C */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4D */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4F */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 50 */ { 0, &BX_CPU_C::PUSH_RX },
/* 51 */ { 0, &BX_CPU_C::PUSH_RX },
/* 52 */ { 0, &BX_CPU_C::PUSH_RX },
/* 53 */ { 0, &BX_CPU_C::PUSH_RX },
/* 54 */ { 0, &BX_CPU_C::PUSH_RX },
/* 55 */ { 0, &BX_CPU_C::PUSH_RX },
/* 56 */ { 0, &BX_CPU_C::PUSH_RX },
/* 57 */ { 0, &BX_CPU_C::PUSH_RX },
/* 58 */ { 0, &BX_CPU_C::POP_RX },
/* 59 */ { 0, &BX_CPU_C::POP_RX },
/* 5A */ { 0, &BX_CPU_C::POP_RX },
/* 5B */ { 0, &BX_CPU_C::POP_RX },
/* 5C */ { 0, &BX_CPU_C::POP_RX },
/* 5D */ { 0, &BX_CPU_C::POP_RX },
/* 5E */ { 0, &BX_CPU_C::POP_RX },
/* 5F */ { 0, &BX_CPU_C::POP_RX },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 60 */ { 0, &BX_CPU_C::BxError },
/* 61 */ { 0, &BX_CPU_C::BxError },
/* 62 */ { 0, &BX_CPU_C::BxError },
#warning PRT: op=63 This needs checking on real hardware. Manual says 16 bit version leaves upper 48 bits unchanged
/* 63 */ { BxAnother, &BX_CPU_C::MOVSX_GwEw }, //
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 64 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // FS:
/* 65 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // GS:
/* 66 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // OS:
/* 67 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // AS:
/* 68 */ { BxImmediate_Iv, &BX_CPU_C::PUSH_Iw },
/* 69 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::IMUL_GwEwIw },
/* 6A */ { BxImmediate_Ib_SE, &BX_CPU_C::PUSH_Iw },
/* 6B */ { BxAnother | BxImmediate_Ib_SE, &BX_CPU_C::IMUL_GwEwIw },
/* 6C */ { BxRepeatable, &BX_CPU_C::INSB_YbDX },
/* 6D */ { BxRepeatable, &BX_CPU_C::INSW_YvDX },
/* 6E */ { BxRepeatable, &BX_CPU_C::OUTSB_DXXb },
/* 6F */ { BxRepeatable, &BX_CPU_C::OUTSW_DXXv },
Got rid of the KPL64Hacks macro. The fixes below eliminated it. Created 64-bit versions of some branch instructions and changed fetchdecode64.cc to use them instead. This keeps the #ifdef pollution down for 32-bit code and made fixing them easier. They needed to clear the upper bits of RIP for 16-bit operand sizes. They also should not have had a protection limit check in them, especially since that field is still 32-bit in cpu.h, so there's no way to set nominal 64-bit values. The 32-bit versions were also not honoring the upper 32-bits of RIP. LOOPNE64_Jb LOOPE64_Jb LOOP64_Jb JCXZ64_Jb Changed all occurances of JCC_Jw/JCC_Jd in fetchdecode64.cc to use JCC_Jq, which was coded already. Both JMP_Jq and JCC_Jq are now fixed w.r.t. 16-bit opsizes and upper RIP bit clearing.
2002-09-27 11:01:02 +04:00
/* 70 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 71 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 72 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 73 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 74 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 75 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 76 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 77 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 78 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 79 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7A */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7B */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7C */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7D */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7E */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7F */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 80 */ { BxAnother | BxGroup1, NULL, BxOpcodeInfo64G1EbIb },
/* 81 */ { BxAnother | BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfo64G1Ew },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 82 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 83 */ { BxAnother | BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfo64G1Ew },
/* 84 */ { BxAnother, &BX_CPU_C::TEST_EbGb },
/* 85 */ { BxAnother, &BX_CPU_C::TEST_EwGw },
/* 86 */ { BxAnother, &BX_CPU_C::XCHG_EbGb },
/* 87 */ { BxAnother, &BX_CPU_C::XCHG_EwGw },
/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
/* 89 */ { BxAnother, &BX_CPU_C::MOV_EwGw },
/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
/* 8B */ { BxAnother, &BX_CPU_C::MOV_GwEw },
/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
/* 8D */ { BxAnother, &BX_CPU_C::LEA_GwM },
/* 8E */ { BxAnother, &BX_CPU_C::MOV_SwEw },
/* 8F */ { BxAnother, &BX_CPU_C::POP_Ew },
/* 90 */ { 0, &BX_CPU_C::NOP },
/* 91 */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 92 */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 93 */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 94 */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 95 */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 96 */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 97 */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 98 */ { 0, &BX_CPU_C::CBW },
/* 99 */ { 0, &BX_CPU_C::CWD },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 9A */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 9B */ { 0, &BX_CPU_C::FWAIT },
/* 9C */ { 0, &BX_CPU_C::PUSHF_Fv },
/* 9D */ { 0, &BX_CPU_C::POPF_Fv },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 9E */ { 0, &BX_CPU_C::BxError },
/* 9F */ { 0, &BX_CPU_C::BxError },
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
/* A0 */ { BxImmediate_O, &BX_CPU_C::MOV_ALOq },
/* A1 */ { BxImmediate_O, &BX_CPU_C::MOV_AXOq },
/* A2 */ { BxImmediate_O, &BX_CPU_C::MOV_OqAL },
/* A3 */ { BxImmediate_O, &BX_CPU_C::MOV_OqAX },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* A4 */ { BxRepeatable, &BX_CPU_C::MOVSB_XbYb },
/* A5 */ { BxRepeatable, &BX_CPU_C::MOVSW_XvYv },
/* A6 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSB_XbYb },
/* A7 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSW_XvYv },
/* A8 */ { BxImmediate_Ib, &BX_CPU_C::TEST_ALIb },
/* A9 */ { BxImmediate_Iv, &BX_CPU_C::TEST_AXIw },
/* AA */ { BxRepeatable, &BX_CPU_C::STOSB_YbAL },
/* AB */ { BxRepeatable, &BX_CPU_C::STOSW_YveAX },
/* AC */ { BxRepeatable, &BX_CPU_C::LODSB_ALXb },
/* AD */ { BxRepeatable, &BX_CPU_C::LODSW_eAXXv },
/* AE */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASB_ALXb },
/* AF */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASW_eAXXv },
/* B0 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B1 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B2 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B3 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B4 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B5 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B6 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B7 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B8 */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* B9 */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* BA */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* BB */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* BC */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* BD */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* BE */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* BF */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* C0 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfo64G2Eb },
/* C1 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfo64G2Ew },
/* C2 */ { BxImmediate_Iw, &BX_CPU_C::RETnear16_Iw },
/* C3 */ { 0, &BX_CPU_C::RETnear16 },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* C4 */ { 0, &BX_CPU_C::BxError },
/* C5 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* C6 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::MOV_EbIb },
/* C7 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::MOV_EwIw },
/* C8 */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
/* C9 */ { 0, &BX_CPU_C::LEAVE64 },
/* CA */ { BxImmediate_Iw, &BX_CPU_C::RETfar16_Iw },
/* CB */ { 0, &BX_CPU_C::RETfar16 },
/* CC */ { 0, &BX_CPU_C::INT3 },
/* CD */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* CE */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* CF */ { 0, &BX_CPU_C::IRET16 },
/* D0 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Eb },
/* D1 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Ew },
/* D2 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Eb },
/* D3 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Ew },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* D4 */ { 0, &BX_CPU_C::BxError },
/* D5 */ { 0, &BX_CPU_C::BxError },
/* D6 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* D7 */ { 0, &BX_CPU_C::XLAT },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* D8 */ { BxAnotherFPU, &BX_CPU_C::ESC0 },
/* D9 */ { BxAnotherFPU, &BX_CPU_C::ESC1 },
/* DA */ { BxAnotherFPU, &BX_CPU_C::ESC2 },
/* DB */ { BxAnotherFPU, &BX_CPU_C::ESC3 },
/* DC */ { BxAnotherFPU, &BX_CPU_C::ESC4 },
/* DD */ { BxAnotherFPU, &BX_CPU_C::ESC5 },
/* DE */ { BxAnotherFPU, &BX_CPU_C::ESC6 },
/* DF */ { BxAnotherFPU, &BX_CPU_C::ESC7 },
Got rid of the KPL64Hacks macro. The fixes below eliminated it. Created 64-bit versions of some branch instructions and changed fetchdecode64.cc to use them instead. This keeps the #ifdef pollution down for 32-bit code and made fixing them easier. They needed to clear the upper bits of RIP for 16-bit operand sizes. They also should not have had a protection limit check in them, especially since that field is still 32-bit in cpu.h, so there's no way to set nominal 64-bit values. The 32-bit versions were also not honoring the upper 32-bits of RIP. LOOPNE64_Jb LOOPE64_Jb LOOP64_Jb JCXZ64_Jb Changed all occurances of JCC_Jw/JCC_Jd in fetchdecode64.cc to use JCC_Jq, which was coded already. Both JMP_Jq and JCC_Jq are now fixed w.r.t. 16-bit opsizes and upper RIP bit clearing.
2002-09-27 11:01:02 +04:00
/* E0 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPNE64_Jb },
/* E1 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPE64_Jb },
/* E2 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOP64_Jb },
/* E3 */ { BxImmediate_BrOff8, &BX_CPU_C::JCXZ64_Jb },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* E4 */ { BxImmediate_Ib, &BX_CPU_C::IN_ALIb },
/* E5 */ { BxImmediate_Ib, &BX_CPU_C::IN_eAXIb },
/* E6 */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAL },
/* E7 */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbeAX },
/* E8 */ { BxImmediate_BrOff16, &BX_CPU_C::CALL_Aw },
/* E9 */ { BxImmediate_BrOff16, &BX_CPU_C::JMP_Jq },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* EA */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* EB */ { BxImmediate_BrOff8, &BX_CPU_C::JMP_Jq },
/* EC */ { 0, &BX_CPU_C::IN_ALDX },
/* ED */ { 0, &BX_CPU_C::IN_eAXDX },
/* EE */ { 0, &BX_CPU_C::OUT_DXAL },
/* EF */ { 0, &BX_CPU_C::OUT_DXeAX },
/* F0 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // LOCK
/* F1 */ { 0, &BX_CPU_C::INT1 },
/* F2 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REPNE/REPNZ
/* F3 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REP, REPE/REPZ
/* F4 */ { 0, &BX_CPU_C::HLT },
/* F5 */ { 0, &BX_CPU_C::CMC },
/* F6 */ { BxAnother | BxGroup3, NULL, BxOpcodeInfo64G3Eb },
/* F7 */ { BxAnother | BxGroup3, NULL, BxOpcodeInfo64G3Ew },
/* F8 */ { 0, &BX_CPU_C::CLC },
/* F9 */ { 0, &BX_CPU_C::STC },
/* FA */ { 0, &BX_CPU_C::CLI },
/* FB */ { 0, &BX_CPU_C::STI },
/* FC */ { 0, &BX_CPU_C::CLD },
/* FD */ { 0, &BX_CPU_C::STD },
/* FE */ { BxAnother | BxGroup4, NULL, BxOpcodeInfo64G4 },
/* FF */ { BxAnother | BxGroup5, NULL, BxOpcodeInfo64G5w },
/* 0F 00 */ { BxAnother | BxGroup6, NULL, BxOpcodeInfo64G6 },
/* 0F 01 */ { BxAnother | BxGroup7, NULL, BxOpcodeInfo64G7 },
/* 0F 02 */ { BxAnother, &BX_CPU_C::LAR_GvEw },
/* 0F 03 */ { BxAnother, &BX_CPU_C::LSL_GvEw },
/* 0F 04 */ { 0, &BX_CPU_C::BxError },
Implemented SYSCALL and SYSRET as part of x86-64 emulation. Since the SYSCALL replaces the LOADALL instruction, it is incompatible with earlier CPU types. At moment, the SYSCALL is only enabled by x86-64 emulation, but the code can be incorporated in IA32 only emulations. Instructions added: 0F 05 SYSCALL (replaces LOADALL) 0F 07 SYSRET (new) TODO: restructure #if ... so that it can be used by non x86-64 emulations.
2002-09-25 16:54:41 +04:00
/* 0F 05 */ { 0, &BX_CPU_C::SYSCALL },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 06 */ { 0, &BX_CPU_C::CLTS },
Implemented SYSCALL and SYSRET as part of x86-64 emulation. Since the SYSCALL replaces the LOADALL instruction, it is incompatible with earlier CPU types. At moment, the SYSCALL is only enabled by x86-64 emulation, but the code can be incorporated in IA32 only emulations. Instructions added: 0F 05 SYSCALL (replaces LOADALL) 0F 07 SYSRET (new) TODO: restructure #if ... so that it can be used by non x86-64 emulations.
2002-09-25 16:54:41 +04:00
/* 0F 07 */ { 0, &BX_CPU_C::SYSRET },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 08 */ { 0, &BX_CPU_C::INVD },
/* 0F 09 */ { 0, &BX_CPU_C::WBINVD },
/* 0F 0A */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 0B */ { 0, &BX_CPU_C::UndefinedOpcode }, /* UD2 opcode */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 0C */ { 0, &BX_CPU_C::BxError },
- from Peter Tattam: change prefetch instructions to nops instead of undefined
2002-09-23 18:25:29 +04:00
/* 0F 0D */ { BxAnother, &BX_CPU_C::NOP }, // PREFETCH L1
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 0E */ { 0, &BX_CPU_C::BxError },
/* 0F 0F */ { 0, &BX_CPU_C::BxError },
/* 0F 10 */ { 0, &BX_CPU_C::BxError },
/* 0F 11 */ { 0, &BX_CPU_C::BxError },
/* 0F 12 */ { 0, &BX_CPU_C::BxError },
/* 0F 13 */ { 0, &BX_CPU_C::BxError },
/* 0F 14 */ { 0, &BX_CPU_C::BxError },
/* 0F 15 */ { 0, &BX_CPU_C::BxError },
/* 0F 16 */ { 0, &BX_CPU_C::BxError },
/* 0F 17 */ { 0, &BX_CPU_C::BxError },
/* 0F 18 */ { BxAnother, &BX_CPU_C::NOP }, // PREFETCH
/* 0F 19 */ { 0, &BX_CPU_C::BxError },
/* 0F 1A */ { 0, &BX_CPU_C::BxError },
/* 0F 1B */ { 0, &BX_CPU_C::BxError },
/* 0F 1C */ { 0, &BX_CPU_C::BxError },
/* 0F 1D */ { 0, &BX_CPU_C::BxError },
/* 0F 1E */ { 0, &BX_CPU_C::BxError },
/* 0F 1F */ { 0, &BX_CPU_C::BxError },
/* 0F 20 */ { BxAnother, &BX_CPU_C::MOV_RdCd },
/* 0F 21 */ { BxAnother, &BX_CPU_C::MOV_RdDd },
/* 0F 22 */ { BxAnother, &BX_CPU_C::MOV_CdRd },
/* 0F 23 */ { BxAnother, &BX_CPU_C::MOV_DdRd },
/* 0F 24 */ { BxAnother, &BX_CPU_C::MOV_RdTd },
/* 0F 25 */ { 0, &BX_CPU_C::BxError },
/* 0F 26 */ { BxAnother, &BX_CPU_C::MOV_TdRd },
/* 0F 27 */ { 0, &BX_CPU_C::BxError },
/* 0F 28 */ { 0, &BX_CPU_C::BxError },
/* 0F 29 */ { 0, &BX_CPU_C::BxError },
/* 0F 2A */ { 0, &BX_CPU_C::BxError },
/* 0F 2B */ { 0, &BX_CPU_C::BxError },
/* 0F 2C */ { 0, &BX_CPU_C::BxError },
/* 0F 2D */ { 0, &BX_CPU_C::BxError },
/* 0F 2E */ { 0, &BX_CPU_C::BxError },
/* 0F 2F */ { 0, &BX_CPU_C::BxError },
/* 0F 30 */ { 0, &BX_CPU_C::WRMSR },
/* 0F 31 */ { 0, &BX_CPU_C::RDTSC },
/* 0F 32 */ { 0, &BX_CPU_C::RDMSR },
/* 0F 33 */ { 0, &BX_CPU_C::BxError },
/* 0F 34 */ { 0, &BX_CPU_C::BxError },
/* 0F 35 */ { 0, &BX_CPU_C::BxError },
/* 0F 36 */ { 0, &BX_CPU_C::BxError },
/* 0F 37 */ { 0, &BX_CPU_C::BxError },
/* 0F 38 */ { 0, &BX_CPU_C::BxError },
/* 0F 39 */ { 0, &BX_CPU_C::BxError },
/* 0F 3A */ { 0, &BX_CPU_C::BxError },
/* 0F 3B */ { 0, &BX_CPU_C::BxError },
/* 0F 3C */ { 0, &BX_CPU_C::BxError },
/* 0F 3D */ { 0, &BX_CPU_C::BxError },
/* 0F 3E */ { 0, &BX_CPU_C::BxError },
/* 0F 3F */ { 0, &BX_CPU_C::BxError },
/* 0F 40 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 41 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 42 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 43 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 44 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 45 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 46 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 47 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 48 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 49 */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 4A */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 4B */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 4C */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 4D */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 4E */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 4F */ { BxAnother, &BX_CPU_C::CMOV_GwEw },
/* 0F 50 */ { 0, &BX_CPU_C::BxError },
/* 0F 51 */ { 0, &BX_CPU_C::BxError },
/* 0F 52 */ { 0, &BX_CPU_C::BxError },
/* 0F 53 */ { 0, &BX_CPU_C::BxError },
/* 0F 54 */ { 0, &BX_CPU_C::BxError },
/* 0F 55 */ { 0, &BX_CPU_C::BxError },
/* 0F 56 */ { 0, &BX_CPU_C::BxError },
/* 0F 57 */ { 0, &BX_CPU_C::BxError },
/* 0F 58 */ { 0, &BX_CPU_C::BxError },
/* 0F 59 */ { 0, &BX_CPU_C::BxError },
/* 0F 5A */ { 0, &BX_CPU_C::BxError },
/* 0F 5B */ { 0, &BX_CPU_C::BxError },
/* 0F 5C */ { 0, &BX_CPU_C::BxError },
/* 0F 5D */ { 0, &BX_CPU_C::BxError },
/* 0F 5E */ { 0, &BX_CPU_C::BxError },
/* 0F 5F */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 60 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLBW_PqQd }, /* MMX */
/* 0F 61 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLWD_PqQd }, /* MMX */
/* 0F 62 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLDQ_PqQd }, /* MMX */
/* 0F 63 */ { BxAnotherMMX, &BX_CPU_C::PACKSSWB_PqQq }, /* MMX */
/* 0F 64 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTB_PqQq }, /* MMX */
/* 0F 65 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTW_PqQq }, /* MMX */
/* 0F 66 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTD_PqQq }, /* MMX */
/* 0F 67 */ { BxAnotherMMX, &BX_CPU_C::PACKUSWB_PqQq }, /* MMX */
/* 0F 68 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHBW_PqQq }, /* MMX */
/* 0F 69 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHWD_PqQq }, /* MMX */
/* 0F 6A */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHDQ_PqQq }, /* MMX */
/* 0F 6B */ { BxAnotherMMX, &BX_CPU_C::PACKSSDW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 6C */ { 0, &BX_CPU_C::BxError },
/* 0F 6D */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 6E */ { BxAnotherMMX, &BX_CPU_C::MOVD_PqEd }, /* MMX */
/* 0F 6F */ { BxAnotherMMX, &BX_CPU_C::MOVQ_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 70 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
#if BX_SUPPORT_MMX
/* 0F 71 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAw },
/* 0F 72 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAd },
/* 0F 73 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAq },
#else
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 71 */ { 0, &BX_CPU_C::BxError },
/* 0F 72 */ { 0, &BX_CPU_C::BxError },
/* 0F 73 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
#endif
/* 0F 74 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQB_PqQq }, /* MMX */
/* 0F 75 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQW_PqQq }, /* MMX */
/* 0F 76 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQD_PqQq }, /* MMX */
/* 0F 77 */ { 0, &BX_CPU_C::EMMS }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 78 */ { 0, &BX_CPU_C::BxError },
/* 0F 79 */ { 0, &BX_CPU_C::BxError },
/* 0F 7A */ { 0, &BX_CPU_C::BxError },
/* 0F 7B */ { 0, &BX_CPU_C::BxError },
/* 0F 7C */ { 0, &BX_CPU_C::BxError },
/* 0F 7D */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 7E */ { BxAnotherMMX, &BX_CPU_C::MOVD_EdPd }, /* MMX */
/* 0F 7F */ { BxAnotherMMX, &BX_CPU_C::MOVQ_QqPq }, /* MMX */
Got rid of the KPL64Hacks macro. The fixes below eliminated it. Created 64-bit versions of some branch instructions and changed fetchdecode64.cc to use them instead. This keeps the #ifdef pollution down for 32-bit code and made fixing them easier. They needed to clear the upper bits of RIP for 16-bit operand sizes. They also should not have had a protection limit check in them, especially since that field is still 32-bit in cpu.h, so there's no way to set nominal 64-bit values. The 32-bit versions were also not honoring the upper 32-bits of RIP. LOOPNE64_Jb LOOPE64_Jb LOOP64_Jb JCXZ64_Jb Changed all occurances of JCC_Jw/JCC_Jd in fetchdecode64.cc to use JCC_Jq, which was coded already. Both JMP_Jq and JCC_Jq are now fixed w.r.t. 16-bit opsizes and upper RIP bit clearing.
2002-09-27 11:01:02 +04:00
/* 0F 80 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 81 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 82 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 83 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 84 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 85 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 86 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 87 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 88 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 89 */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 8A */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 8B */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 8C */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 8D */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 8E */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
/* 0F 8F */ { BxImmediate_BrOff16, &BX_CPU_C::JCC_Jq },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 90 */ { BxAnother, &BX_CPU_C::SETO_Eb },
/* 0F 91 */ { BxAnother, &BX_CPU_C::SETNO_Eb },
/* 0F 92 */ { BxAnother, &BX_CPU_C::SETB_Eb },
/* 0F 93 */ { BxAnother, &BX_CPU_C::SETNB_Eb },
/* 0F 94 */ { BxAnother, &BX_CPU_C::SETZ_Eb },
/* 0F 95 */ { BxAnother, &BX_CPU_C::SETNZ_Eb },
/* 0F 96 */ { BxAnother, &BX_CPU_C::SETBE_Eb },
/* 0F 97 */ { BxAnother, &BX_CPU_C::SETNBE_Eb },
/* 0F 98 */ { BxAnother, &BX_CPU_C::SETS_Eb },
/* 0F 99 */ { BxAnother, &BX_CPU_C::SETNS_Eb },
/* 0F 9A */ { BxAnother, &BX_CPU_C::SETP_Eb },
/* 0F 9B */ { BxAnother, &BX_CPU_C::SETNP_Eb },
/* 0F 9C */ { BxAnother, &BX_CPU_C::SETL_Eb },
/* 0F 9D */ { BxAnother, &BX_CPU_C::SETNL_Eb },
/* 0F 9E */ { BxAnother, &BX_CPU_C::SETLE_Eb },
/* 0F 9F */ { BxAnother, &BX_CPU_C::SETNLE_Eb },
/* 0F A0 */ { 0, &BX_CPU_C::PUSH_FS },
/* 0F A1 */ { 0, &BX_CPU_C::POP_FS },
/* 0F A2 */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EvGv },
/* 0F A4 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
/* 0F A5 */ { BxAnother, &BX_CPU_C::SHLD_EwGw },
/* 0F A6 */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
/* 0F A7 */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
/* 0F A8 */ { 0, &BX_CPU_C::PUSH_GS },
/* 0F A9 */ { 0, &BX_CPU_C::POP_GS },
/* 0F AA */ { 0, &BX_CPU_C::RSM },
/* 0F AB */ { BxAnother, &BX_CPU_C::BTS_EvGv },
/* 0F AC */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
/* 0F AD */ { BxAnother, &BX_CPU_C::SHRD_EwGw },
/* 0F AE */ { BxAnother | BxGroup15, NULL, BxOpcodeInfo64G15 },
/* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GwEw },
/* 0F B0 */ { BxAnother, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 */ { BxAnother, &BX_CPU_C::CMPXCHG_EwGw },
/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
/* 0F B3 */ { BxAnother, &BX_CPU_C::BTR_EvGv },
/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GwEb },
/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GwEw },
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
/* 0F B9 */ { 0, &BX_CPU_C::BxError },
/* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
/* 0F BB */ { BxAnother, &BX_CPU_C::BTC_EvGv },
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GvEv },
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GvEv },
/* 0F BE */ { BxAnother, &BX_CPU_C::MOVSX_GwEb },
/* 0F BF */ { BxAnother, &BX_CPU_C::MOVSX_GwEw },
/* 0F C0 */ { BxAnother, &BX_CPU_C::XADD_EbGb },
/* 0F C1 */ { BxAnother, &BX_CPU_C::XADD_EwGw },
/* 0F C2 */ { 0, &BX_CPU_C::BxError },
- from Peter Tattam: add missing instruction MOVNTI to decode table
2002-09-25 07:32:12 +04:00
/* 0F C3 */ { 0, &BX_CPU_C::BxError }, // movnti not impl for word size.
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F C4 */ { 0, &BX_CPU_C::BxError },
/* 0F C5 */ { 0, &BX_CPU_C::BxError },
/* 0F C6 */ { 0, &BX_CPU_C::BxError },
/* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9 },
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX },
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX },
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX },
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX },
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP },
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP },
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI },
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI },
/* 0F D0 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D1 */ { BxAnotherMMX, &BX_CPU_C::PSRLW_PqQq }, /* MMX */
/* 0F D2 */ { BxAnotherMMX, &BX_CPU_C::PSRLD_PqQq }, /* MMX */
/* 0F D3 */ { BxAnotherMMX, &BX_CPU_C::PSRLQ_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F D4 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D5 */ { BxAnotherMMX, &BX_CPU_C::PMULLW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F D6 */ { 0, &BX_CPU_C::BxError },
/* 0F D7 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D8 */ { BxAnotherMMX, &BX_CPU_C::PSUBUSB_PqQq }, /* MMX */
/* 0F D9 */ { BxAnotherMMX, &BX_CPU_C::PSUBUSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F DA */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F DB */ { BxAnotherMMX, &BX_CPU_C::PAND_PqQq }, /* MMX */
/* 0F DC */ { BxAnotherMMX, &BX_CPU_C::PADDUSB_PqQq }, /* MMX */
/* 0F DD */ { BxAnotherMMX, &BX_CPU_C::PADDUSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F DE */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F DF */ { BxAnotherMMX, &BX_CPU_C::PANDN_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E0 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E1 */ { BxAnotherMMX, &BX_CPU_C::PSRAW_PqQq }, /* MMX */
/* 0F E2 */ { BxAnotherMMX, &BX_CPU_C::PSRAD_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E3 */ { 0, &BX_CPU_C::BxError },
/* 0F E4 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E5 */ { BxAnotherMMX, &BX_CPU_C::PMULHW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E6 */ { 0, &BX_CPU_C::BxError },
/* 0F E7 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E8 */ { BxAnotherMMX, &BX_CPU_C::PSUBSB_PqQq }, /* MMX */
/* 0F E9 */ { BxAnotherMMX, &BX_CPU_C::PSUBSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F EA */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F EB */ { BxAnotherMMX, &BX_CPU_C::POR_PqQq }, /* MMX */
/* 0F EC */ { BxAnotherMMX, &BX_CPU_C::PADDSB_PqQq }, /* MMX */
/* 0F ED */ { BxAnotherMMX, &BX_CPU_C::PADDSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F EE */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F EF */ { BxAnotherMMX, &BX_CPU_C::PXOR_PqQq }, /* MMX */
/* 0F F0 */ { 0, &BX_CPU_C::BxError },
/* 0F F1 */ { BxAnotherMMX, &BX_CPU_C::PSLLW_PqQq }, /* MMX */
/* 0F F2 */ { BxAnotherMMX, &BX_CPU_C::PSLLD_PqQq }, /* MMX */
/* 0F F3 */ { BxAnotherMMX, &BX_CPU_C::PSLLQ_PqQq }, /* MMX */
/* 0F F4 */ { 0, &BX_CPU_C::BxError },
/* 0F F5 */ { BxAnotherMMX, &BX_CPU_C::PMADDWD_PqQq }, /* MMX */
/* 0F F6 */ { 0, &BX_CPU_C::BxError },
/* 0F F7 */ { 0, &BX_CPU_C::BxError },
/* 0F F8 */ { BxAnotherMMX, &BX_CPU_C::PSUBB_PqQq }, /* MMX */
/* 0F F9 */ { BxAnotherMMX, &BX_CPU_C::PSUBW_PqQq }, /* MMX */
/* 0F FA */ { BxAnotherMMX, &BX_CPU_C::PSUBD_PqQq }, /* MMX */
/* 0F FB */ { 0, &BX_CPU_C::BxError },
/* 0F FC */ { BxAnotherMMX, &BX_CPU_C::PADDB_PqQq }, /* MMX */
/* 0F FD */ { BxAnotherMMX, &BX_CPU_C::PADDW_PqQq }, /* MMX */
/* 0F FE */ { BxAnotherMMX, &BX_CPU_C::PADDD_PqQq }, /* MMX */
/* 0F FF */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
// 512 entries for 32bit mod
/* 00 */ { BxAnother, &BX_CPU_C::ADD_EbGb },
/* 01 */ { BxAnother, &BX_CPU_C::ADD_EdGd },
/* 02 */ { BxAnother, &BX_CPU_C::ADD_GbEb },
/* 03 */ { BxAnother, &BX_CPU_C::ADD_GdEd },
/* 04 */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 */ { BxImmediate_Iv, &BX_CPU_C::ADD_EAXId },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 06 */ { 0, &BX_CPU_C::BxError },
/* 07 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 08 */ { BxAnother, &BX_CPU_C::OR_EbGb },
/* 09 */ { BxAnother, &BX_CPU_C::OR_EdGd },
/* 0A */ { BxAnother, &BX_CPU_C::OR_GbEb },
/* 0B */ { BxAnother, &BX_CPU_C::OR_GdEd },
/* 0C */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
/* 0D */ { BxImmediate_Iv, &BX_CPU_C::OR_EAXId },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 0E */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F */ { BxAnother, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 */ { BxAnother, &BX_CPU_C::ADC_EbGb },
/* 11 */ { BxAnother, &BX_CPU_C::ADC_EdGd },
/* 12 */ { BxAnother, &BX_CPU_C::ADC_GbEb },
/* 13 */ { BxAnother, &BX_CPU_C::ADC_GdEd },
/* 14 */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 */ { BxImmediate_Iv, &BX_CPU_C::ADC_EAXId },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 16 */ { 0, &BX_CPU_C::BxError },
/* 17 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 18 */ { BxAnother, &BX_CPU_C::SBB_EbGb },
/* 19 */ { BxAnother, &BX_CPU_C::SBB_EdGd },
/* 1A */ { BxAnother, &BX_CPU_C::SBB_GbEb },
/* 1B */ { BxAnother, &BX_CPU_C::SBB_GdEd },
/* 1C */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
/* 1D */ { BxImmediate_Iv, &BX_CPU_C::SBB_EAXId },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 1E */ { 0, &BX_CPU_C::BxError },
/* 1F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 20 */ { BxAnother, &BX_CPU_C::AND_EbGb },
/* 21 */ { BxAnother, &BX_CPU_C::AND_EdGd },
/* 22 */ { BxAnother, &BX_CPU_C::AND_GbEb },
/* 23 */ { BxAnother, &BX_CPU_C::AND_GdEd },
/* 24 */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
/* 25 */ { BxImmediate_Iv, &BX_CPU_C::AND_EAXId },
/* 26 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // ES:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 27 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 28 */ { BxAnother, &BX_CPU_C::SUB_EbGb },
/* 29 */ { BxAnother, &BX_CPU_C::SUB_EdGd },
/* 2A */ { BxAnother, &BX_CPU_C::SUB_GbEb },
/* 2B */ { BxAnother, &BX_CPU_C::SUB_GdEd },
/* 2C */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
/* 2D */ { BxImmediate_Iv, &BX_CPU_C::SUB_EAXId },
/* 2E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // CS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 2F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 30 */ { BxAnother, &BX_CPU_C::XOR_EbGb },
/* 31 */ { BxAnother, &BX_CPU_C::XOR_EdGd },
/* 32 */ { BxAnother, &BX_CPU_C::XOR_GbEb },
/* 33 */ { BxAnother, &BX_CPU_C::XOR_GdEd },
/* 34 */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
/* 35 */ { BxImmediate_Iv, &BX_CPU_C::XOR_EAXId },
/* 36 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // SS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 37 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 38 */ { BxAnother, &BX_CPU_C::CMP_EbGb },
/* 39 */ { BxAnother, &BX_CPU_C::CMP_EdGd },
/* 3A */ { BxAnother, &BX_CPU_C::CMP_GbEb },
/* 3B */ { BxAnother, &BX_CPU_C::CMP_GdEd },
/* 3C */ { BxImmediate_Ib, &BX_CPU_C::CMP_ALIb },
/* 3D */ { BxImmediate_Iv, &BX_CPU_C::CMP_EAXId },
/* 3E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // DS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 3F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 40 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 41 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 42 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 43 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 44 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 45 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 46 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 47 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 48 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 49 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4A */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4B */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4C */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4D */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4F */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 50 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 51 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 52 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 53 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 54 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 55 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 56 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 57 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 58 */ { 0, &BX_CPU_C::POP_RRX },
/* 59 */ { 0, &BX_CPU_C::POP_RRX },
/* 5A */ { 0, &BX_CPU_C::POP_RRX },
/* 5B */ { 0, &BX_CPU_C::POP_RRX },
/* 5C */ { 0, &BX_CPU_C::POP_RRX },
/* 5D */ { 0, &BX_CPU_C::POP_RRX },
/* 5E */ { 0, &BX_CPU_C::POP_RRX },
/* 5F */ { 0, &BX_CPU_C::POP_RRX },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 60 */ { 0, &BX_CPU_C::BxError },
/* 61 */ { 0, &BX_CPU_C::BxError },
/* 62 */ { 0, &BX_CPU_C::BxError },
#warning PRT: This needs checking on real hardware. Manual says 32 bit version zero extends result
/* 63 */ { BxAnother, &BX_CPU_C::MOV_GdEd },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 64 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // FS:
/* 65 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // GS:
/* 66 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // OS:
/* 67 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // AS:
/* 68 */ { BxImmediate_Iv, &BX_CPU_C::PUSH64_Id },
/* 69 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::IMUL_GdEdId },
/* 6A */ { BxImmediate_Ib_SE, &BX_CPU_C::PUSH64_Id },
/* 6B */ { BxAnother | BxImmediate_Ib_SE, &BX_CPU_C::IMUL_GdEdId },
/* 6C */ { BxRepeatable, &BX_CPU_C::INSB_YbDX },
/* 6D */ { BxRepeatable, &BX_CPU_C::INSW_YvDX },
/* 6E */ { BxRepeatable, &BX_CPU_C::OUTSB_DXXb },
/* 6F */ { BxRepeatable, &BX_CPU_C::OUTSW_DXXv },
Got rid of the KPL64Hacks macro. The fixes below eliminated it. Created 64-bit versions of some branch instructions and changed fetchdecode64.cc to use them instead. This keeps the #ifdef pollution down for 32-bit code and made fixing them easier. They needed to clear the upper bits of RIP for 16-bit operand sizes. They also should not have had a protection limit check in them, especially since that field is still 32-bit in cpu.h, so there's no way to set nominal 64-bit values. The 32-bit versions were also not honoring the upper 32-bits of RIP. LOOPNE64_Jb LOOPE64_Jb LOOP64_Jb JCXZ64_Jb Changed all occurances of JCC_Jw/JCC_Jd in fetchdecode64.cc to use JCC_Jq, which was coded already. Both JMP_Jq and JCC_Jq are now fixed w.r.t. 16-bit opsizes and upper RIP bit clearing.
2002-09-27 11:01:02 +04:00
/* 70 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 71 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 72 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 73 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 74 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 75 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 76 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 77 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 78 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 79 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7A */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7B */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7C */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7D */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7E */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7F */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 80 */ { BxAnother | BxGroup1, NULL, BxOpcodeInfo64G1EbIb },
/* 81 */ { BxAnother | BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfo64G1Ed },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 82 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 83 */ { BxAnother | BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfo64G1Ed },
/* 84 */ { BxAnother, &BX_CPU_C::TEST_EbGb },
/* 85 */ { BxAnother, &BX_CPU_C::TEST_EdGd },
/* 86 */ { BxAnother, &BX_CPU_C::XCHG_EbGb },
/* 87 */ { BxAnother, &BX_CPU_C::XCHG_EdGd },
/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
/* 89 */ { BxAnother, &BX_CPU_C::MOV_EdGd },
/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
/* 8B */ { BxAnother, &BX_CPU_C::MOV_GdEd },
/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
/* 8D */ { BxAnother, &BX_CPU_C::LEA_GdM },
/* 8E */ { BxAnother, &BX_CPU_C::MOV_SwEw },
/* 8F */ { BxAnother, &BX_CPU_C::POP_Eq },
/* 90 */ { 0, &BX_CPU_C::NOP },
/* 91 */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 92 */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 93 */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 94 */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 95 */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 96 */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 97 */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 98 */ { 0, &BX_CPU_C::CWDE },
/* 99 */ { 0, &BX_CPU_C::CDQ },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 9A */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 9B */ { 0, &BX_CPU_C::FWAIT },
/* 9C */ { 0, &BX_CPU_C::PUSHF_Fv },
/* 9D */ { 0, &BX_CPU_C::POPF_Fv },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 9E */ { 0, &BX_CPU_C::BxError },
/* 9F */ { 0, &BX_CPU_C::BxError },
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
/* A0 */ { BxImmediate_O, &BX_CPU_C::MOV_ALOq },
/* A1 */ { BxImmediate_O, &BX_CPU_C::MOV_EAXOq },
/* A2 */ { BxImmediate_O, &BX_CPU_C::MOV_OqAL },
/* A3 */ { BxImmediate_O, &BX_CPU_C::MOV_OqEAX },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* A4 */ { BxRepeatable, &BX_CPU_C::MOVSB_XbYb },
/* A5 */ { BxRepeatable, &BX_CPU_C::MOVSW_XvYv },
/* A6 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSB_XbYb },
/* A7 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSW_XvYv },
/* A8 */ { BxImmediate_Ib, &BX_CPU_C::TEST_ALIb },
/* A9 */ { BxImmediate_Iv, &BX_CPU_C::TEST_EAXId },
/* AA */ { BxRepeatable, &BX_CPU_C::STOSB_YbAL },
/* AB */ { BxRepeatable, &BX_CPU_C::STOSW_YveAX },
/* AC */ { BxRepeatable, &BX_CPU_C::LODSB_ALXb },
/* AD */ { BxRepeatable, &BX_CPU_C::LODSW_eAXXv },
/* AE */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASB_ALXb },
/* AF */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASW_eAXXv },
/* B0 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B1 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B2 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B3 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B4 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B5 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B6 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B7 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B8 */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* B9 */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* BA */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* BB */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* BC */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* BD */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* BE */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* BF */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* C0 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfo64G2Eb },
/* C1 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfo64G2Ed },
/* C2 */ { BxImmediate_Iw, &BX_CPU_C::RETnear64_Iw },
/* C3 */ { 0, &BX_CPU_C::RETnear64 },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* C4 */ { 0, &BX_CPU_C::BxError },
/* C5 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* C6 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::MOV_EbIb },
/* C7 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::MOV_EdId },
/* C8 */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
/* C9 */ { 0, &BX_CPU_C::LEAVE64 },
/* CA */ { BxImmediate_Iw, &BX_CPU_C::RETfar64_Iw },
/* CB */ { 0, &BX_CPU_C::RETfar64 },
/* CC */ { 0, &BX_CPU_C::INT3 },
/* CD */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* CE */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* CF */ { 0, &BX_CPU_C::IRET64 },
/* D0 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Eb },
/* D1 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Ed },
/* D2 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Eb },
/* D3 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Ed },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* D4 */ { 0, &BX_CPU_C::BxError },
/* D5 */ { 0, &BX_CPU_C::BxError },
/* D6 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* D7 */ { 0, &BX_CPU_C::XLAT },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* D8 */ { BxAnotherFPU, &BX_CPU_C::ESC0 },
/* D9 */ { BxAnotherFPU, &BX_CPU_C::ESC1 },
/* DA */ { BxAnotherFPU, &BX_CPU_C::ESC2 },
/* DB */ { BxAnotherFPU, &BX_CPU_C::ESC3 },
/* DC */ { BxAnotherFPU, &BX_CPU_C::ESC4 },
/* DD */ { BxAnotherFPU, &BX_CPU_C::ESC5 },
/* DE */ { BxAnotherFPU, &BX_CPU_C::ESC6 },
/* DF */ { BxAnotherFPU, &BX_CPU_C::ESC7 },
Got rid of the KPL64Hacks macro. The fixes below eliminated it. Created 64-bit versions of some branch instructions and changed fetchdecode64.cc to use them instead. This keeps the #ifdef pollution down for 32-bit code and made fixing them easier. They needed to clear the upper bits of RIP for 16-bit operand sizes. They also should not have had a protection limit check in them, especially since that field is still 32-bit in cpu.h, so there's no way to set nominal 64-bit values. The 32-bit versions were also not honoring the upper 32-bits of RIP. LOOPNE64_Jb LOOPE64_Jb LOOP64_Jb JCXZ64_Jb Changed all occurances of JCC_Jw/JCC_Jd in fetchdecode64.cc to use JCC_Jq, which was coded already. Both JMP_Jq and JCC_Jq are now fixed w.r.t. 16-bit opsizes and upper RIP bit clearing.
2002-09-27 11:01:02 +04:00
/* E0 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPNE64_Jb },
/* E1 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPE64_Jb },
/* E2 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOP64_Jb },
/* E3 */ { BxImmediate_BrOff8, &BX_CPU_C::JCXZ64_Jb },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* E4 */ { BxImmediate_Ib, &BX_CPU_C::IN_ALIb },
/* E5 */ { BxImmediate_Ib, &BX_CPU_C::IN_eAXIb },
/* E6 */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAL },
/* E7 */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbeAX },
/* E8 */ { BxImmediate_BrOff32, &BX_CPU_C::CALL_Aq },
/* E9 */ { BxImmediate_BrOff32, &BX_CPU_C::JMP_Jq },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* EA */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* EB */ { BxImmediate_BrOff8, &BX_CPU_C::JMP_Jq },
/* EC */ { 0, &BX_CPU_C::IN_ALDX },
/* ED */ { 0, &BX_CPU_C::IN_eAXDX },
/* EE */ { 0, &BX_CPU_C::OUT_DXAL },
/* EF */ { 0, &BX_CPU_C::OUT_DXeAX },
/* F0 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // LOCK:
/* F1 */ { 0, &BX_CPU_C::INT1 },
/* F2 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REPNE/REPNZ
/* F3 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REP,REPE/REPZ
/* F4 */ { 0, &BX_CPU_C::HLT },
/* F5 */ { 0, &BX_CPU_C::CMC },
/* F6 */ { BxAnother | BxGroup3, NULL, BxOpcodeInfo64G3Eb },
/* F7 */ { BxAnother | BxGroup3, NULL, BxOpcodeInfo64G3Ed },
/* F8 */ { 0, &BX_CPU_C::CLC },
/* F9 */ { 0, &BX_CPU_C::STC },
/* FA */ { 0, &BX_CPU_C::CLI },
/* FB */ { 0, &BX_CPU_C::STI },
/* FC */ { 0, &BX_CPU_C::CLD },
/* FD */ { 0, &BX_CPU_C::STD },
/* FE */ { BxAnother | BxGroup4, NULL, BxOpcodeInfo64G4 },
/* FF */ { BxAnother | BxGroup5, NULL, BxOpcodeInfo64G5d },
/* 0F 00 */ { BxAnother | BxGroup6, NULL, BxOpcodeInfo64G6 },
/* 0F 01 */ { BxAnother | BxGroup7, NULL, BxOpcodeInfo64G7 },
/* 0F 02 */ { BxAnother, &BX_CPU_C::LAR_GvEw },
/* 0F 03 */ { BxAnother, &BX_CPU_C::LSL_GvEw },
/* 0F 04 */ { 0, &BX_CPU_C::BxError },
Implemented SYSCALL and SYSRET as part of x86-64 emulation. Since the SYSCALL replaces the LOADALL instruction, it is incompatible with earlier CPU types. At moment, the SYSCALL is only enabled by x86-64 emulation, but the code can be incorporated in IA32 only emulations. Instructions added: 0F 05 SYSCALL (replaces LOADALL) 0F 07 SYSRET (new) TODO: restructure #if ... so that it can be used by non x86-64 emulations.
2002-09-25 16:54:41 +04:00
/* 0F 05 */ { 0, &BX_CPU_C::SYSCALL },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 06 */ { 0, &BX_CPU_C::CLTS },
Implemented SYSCALL and SYSRET as part of x86-64 emulation. Since the SYSCALL replaces the LOADALL instruction, it is incompatible with earlier CPU types. At moment, the SYSCALL is only enabled by x86-64 emulation, but the code can be incorporated in IA32 only emulations. Instructions added: 0F 05 SYSCALL (replaces LOADALL) 0F 07 SYSRET (new) TODO: restructure #if ... so that it can be used by non x86-64 emulations.
2002-09-25 16:54:41 +04:00
/* 0F 07 */ { 0, &BX_CPU_C::SYSRET },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 08 */ { 0, &BX_CPU_C::INVD },
/* 0F 09 */ { 0, &BX_CPU_C::WBINVD },
/* 0F 0A */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 0B */ { 0, &BX_CPU_C::UndefinedOpcode }, /* UD2 opcode */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 0C */ { 0, &BX_CPU_C::BxError },
- from Peter Tattam: change prefetch instructions to nops instead of undefined
2002-09-23 18:25:29 +04:00
/* 0F 0D */ { BxAnother, &BX_CPU_C::NOP }, // PREFETCH L1
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 0E */ { 0, &BX_CPU_C::BxError },
/* 0F 0F */ { 0, &BX_CPU_C::BxError },
/* 0F 10 */ { 0, &BX_CPU_C::BxError },
/* 0F 11 */ { 0, &BX_CPU_C::BxError },
/* 0F 12 */ { 0, &BX_CPU_C::BxError },
/* 0F 13 */ { 0, &BX_CPU_C::BxError },
/* 0F 14 */ { 0, &BX_CPU_C::BxError },
/* 0F 15 */ { 0, &BX_CPU_C::BxError },
/* 0F 16 */ { 0, &BX_CPU_C::BxError },
/* 0F 17 */ { 0, &BX_CPU_C::BxError },
/* 0F 18 */ { BxAnother, &BX_CPU_C::NOP }, // PREFETCH
/* 0F 19 */ { 0, &BX_CPU_C::BxError },
/* 0F 1A */ { 0, &BX_CPU_C::BxError },
/* 0F 1B */ { 0, &BX_CPU_C::BxError },
/* 0F 1C */ { 0, &BX_CPU_C::BxError },
/* 0F 1D */ { 0, &BX_CPU_C::BxError },
/* 0F 1E */ { 0, &BX_CPU_C::BxError },
/* 0F 1F */ { 0, &BX_CPU_C::BxError },
/* 0F 20 */ { BxAnother, &BX_CPU_C::MOV_RdCd },
/* 0F 21 */ { BxAnother, &BX_CPU_C::MOV_RdDd },
/* 0F 22 */ { BxAnother, &BX_CPU_C::MOV_CdRd },
/* 0F 23 */ { BxAnother, &BX_CPU_C::MOV_DdRd },
/* 0F 24 */ { BxAnother, &BX_CPU_C::MOV_RdTd },
/* 0F 25 */ { 0, &BX_CPU_C::BxError },
/* 0F 26 */ { BxAnother, &BX_CPU_C::MOV_TdRd },
/* 0F 27 */ { 0, &BX_CPU_C::BxError },
/* 0F 28 */ { 0, &BX_CPU_C::BxError },
/* 0F 29 */ { 0, &BX_CPU_C::BxError },
/* 0F 2A */ { 0, &BX_CPU_C::BxError },
/* 0F 2B */ { 0, &BX_CPU_C::BxError },
/* 0F 2C */ { 0, &BX_CPU_C::BxError },
/* 0F 2D */ { 0, &BX_CPU_C::BxError },
/* 0F 2E */ { 0, &BX_CPU_C::BxError },
/* 0F 2F */ { 0, &BX_CPU_C::BxError },
/* 0F 30 */ { 0, &BX_CPU_C::WRMSR },
/* 0F 31 */ { 0, &BX_CPU_C::RDTSC },
/* 0F 32 */ { 0, &BX_CPU_C::RDMSR },
/* 0F 33 */ { 0, &BX_CPU_C::BxError },
/* 0F 34 */ { 0, &BX_CPU_C::BxError },
/* 0F 35 */ { 0, &BX_CPU_C::BxError },
/* 0F 36 */ { 0, &BX_CPU_C::BxError },
/* 0F 37 */ { 0, &BX_CPU_C::BxError },
/* 0F 38 */ { 0, &BX_CPU_C::BxError },
/* 0F 39 */ { 0, &BX_CPU_C::BxError },
/* 0F 3A */ { 0, &BX_CPU_C::BxError },
/* 0F 3B */ { 0, &BX_CPU_C::BxError },
/* 0F 3C */ { 0, &BX_CPU_C::BxError },
/* 0F 3D */ { 0, &BX_CPU_C::BxError },
/* 0F 3E */ { 0, &BX_CPU_C::BxError },
/* 0F 3F */ { 0, &BX_CPU_C::BxError },
/* 0F 40 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 41 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 42 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 43 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 44 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 45 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 46 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 47 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 48 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 49 */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 4A */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 4B */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 4C */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 4D */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 4E */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 4F */ { BxAnother, &BX_CPU_C::CMOV_GdEd },
/* 0F 50 */ { 0, &BX_CPU_C::BxError },
/* 0F 51 */ { 0, &BX_CPU_C::BxError },
/* 0F 52 */ { 0, &BX_CPU_C::BxError },
/* 0F 53 */ { 0, &BX_CPU_C::BxError },
/* 0F 54 */ { 0, &BX_CPU_C::BxError },
/* 0F 55 */ { 0, &BX_CPU_C::BxError },
/* 0F 56 */ { 0, &BX_CPU_C::BxError },
/* 0F 57 */ { 0, &BX_CPU_C::BxError },
/* 0F 58 */ { 0, &BX_CPU_C::BxError },
/* 0F 59 */ { 0, &BX_CPU_C::BxError },
/* 0F 5A */ { 0, &BX_CPU_C::BxError },
/* 0F 5B */ { 0, &BX_CPU_C::BxError },
/* 0F 5C */ { 0, &BX_CPU_C::BxError },
/* 0F 5D */ { 0, &BX_CPU_C::BxError },
/* 0F 5E */ { 0, &BX_CPU_C::BxError },
/* 0F 5F */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 60 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLBW_PqQd }, /* MMX */
/* 0F 61 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLWD_PqQd }, /* MMX */
/* 0F 62 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLDQ_PqQd }, /* MMX */
/* 0F 63 */ { BxAnotherMMX, &BX_CPU_C::PACKSSWB_PqQq }, /* MMX */
/* 0F 64 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTB_PqQq }, /* MMX */
/* 0F 65 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTW_PqQq }, /* MMX */
/* 0F 66 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTD_PqQq }, /* MMX */
/* 0F 67 */ { BxAnotherMMX, &BX_CPU_C::PACKUSWB_PqQq }, /* MMX */
/* 0F 68 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHBW_PqQq }, /* MMX */
/* 0F 69 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHWD_PqQq }, /* MMX */
/* 0F 6A */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHDQ_PqQq }, /* MMX */
/* 0F 6B */ { BxAnotherMMX, &BX_CPU_C::PACKSSDW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 6C */ { 0, &BX_CPU_C::BxError },
/* 0F 6D */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 6E */ { BxAnotherMMX, &BX_CPU_C::MOVD_PqEd }, /* MMX */
/* 0F 6F */ { BxAnotherMMX, &BX_CPU_C::MOVQ_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 70 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
#if BX_SUPPORT_MMX
/* 0F 71 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAw },
/* 0F 72 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAd },
/* 0F 73 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAq },
#else
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 71 */ { 0, &BX_CPU_C::BxError },
/* 0F 72 */ { 0, &BX_CPU_C::BxError },
/* 0F 73 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
#endif
/* 0F 74 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQB_PqQq }, /* MMX */
/* 0F 75 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQW_PqQq }, /* MMX */
/* 0F 76 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQD_PqQq }, /* MMX */
/* 0F 77 */ { 0, &BX_CPU_C::EMMS }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 78 */ { 0, &BX_CPU_C::BxError },
/* 0F 79 */ { 0, &BX_CPU_C::BxError },
/* 0F 7A */ { 0, &BX_CPU_C::BxError },
/* 0F 7B */ { 0, &BX_CPU_C::BxError },
/* 0F 7C */ { 0, &BX_CPU_C::BxError },
/* 0F 7D */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 7E */ { BxAnotherMMX, &BX_CPU_C::MOVD_EdPd }, /* MMX */
/* 0F 7F */ { BxAnotherMMX, &BX_CPU_C::MOVQ_QqPq }, /* MMX */
Got rid of the KPL64Hacks macro. The fixes below eliminated it. Created 64-bit versions of some branch instructions and changed fetchdecode64.cc to use them instead. This keeps the #ifdef pollution down for 32-bit code and made fixing them easier. They needed to clear the upper bits of RIP for 16-bit operand sizes. They also should not have had a protection limit check in them, especially since that field is still 32-bit in cpu.h, so there's no way to set nominal 64-bit values. The 32-bit versions were also not honoring the upper 32-bits of RIP. LOOPNE64_Jb LOOPE64_Jb LOOP64_Jb JCXZ64_Jb Changed all occurances of JCC_Jw/JCC_Jd in fetchdecode64.cc to use JCC_Jq, which was coded already. Both JMP_Jq and JCC_Jq are now fixed w.r.t. 16-bit opsizes and upper RIP bit clearing.
2002-09-27 11:01:02 +04:00
/* 0F 80 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 81 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 82 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 83 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 84 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 85 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 86 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 87 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 88 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 89 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8A */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8B */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8C */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8D */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8E */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8F */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 90 */ { BxAnother, &BX_CPU_C::SETO_Eb },
/* 0F 91 */ { BxAnother, &BX_CPU_C::SETNO_Eb },
/* 0F 92 */ { BxAnother, &BX_CPU_C::SETB_Eb },
/* 0F 93 */ { BxAnother, &BX_CPU_C::SETNB_Eb },
/* 0F 94 */ { BxAnother, &BX_CPU_C::SETZ_Eb },
/* 0F 95 */ { BxAnother, &BX_CPU_C::SETNZ_Eb },
/* 0F 96 */ { BxAnother, &BX_CPU_C::SETBE_Eb },
/* 0F 97 */ { BxAnother, &BX_CPU_C::SETNBE_Eb },
/* 0F 98 */ { BxAnother, &BX_CPU_C::SETS_Eb },
/* 0F 99 */ { BxAnother, &BX_CPU_C::SETNS_Eb },
/* 0F 9A */ { BxAnother, &BX_CPU_C::SETP_Eb },
/* 0F 9B */ { BxAnother, &BX_CPU_C::SETNP_Eb },
/* 0F 9C */ { BxAnother, &BX_CPU_C::SETL_Eb },
/* 0F 9D */ { BxAnother, &BX_CPU_C::SETNL_Eb },
/* 0F 9E */ { BxAnother, &BX_CPU_C::SETLE_Eb },
/* 0F 9F */ { BxAnother, &BX_CPU_C::SETNLE_Eb },
/* 0F A0 */ { 0, &BX_CPU_C::PUSH64_FS },
/* 0F A1 */ { 0, &BX_CPU_C::POP64_FS },
/* 0F A2 */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EvGv },
/* 0F A4 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHLD_EdGd },
/* 0F A5 */ { BxAnother, &BX_CPU_C::SHLD_EdGd },
/* 0F A6 */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
/* 0F A7 */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
/* 0F A8 */ { 0, &BX_CPU_C::PUSH64_GS },
/* 0F A9 */ { 0, &BX_CPU_C::POP64_GS },
/* 0F AA */ { 0, &BX_CPU_C::RSM },
/* 0F AB */ { BxAnother, &BX_CPU_C::BTS_EvGv },
/* 0F AC */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHRD_EdGd },
/* 0F AD */ { BxAnother, &BX_CPU_C::SHRD_EdGd },
/* 0F AE */ { BxAnother | BxGroup15, NULL, BxOpcodeInfo64G15 },
/* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GdEd },
/* 0F B0 */ { BxAnother, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 */ { BxAnother, &BX_CPU_C::CMPXCHG_EdGd },
/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
/* 0F B3 */ { BxAnother, &BX_CPU_C::BTR_EvGv },
/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GdEb },
/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GdEw },
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
/* 0F B9 */ { 0, &BX_CPU_C::BxError },
/* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
/* 0F BB */ { BxAnother, &BX_CPU_C::BTC_EvGv },
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GvEv },
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GvEv },
/* 0F BE */ { BxAnother, &BX_CPU_C::MOVSX_GdEb },
/* 0F BF */ { BxAnother, &BX_CPU_C::MOVSX_GdEw },
/* 0F C0 */ { BxAnother, &BX_CPU_C::XADD_EbGb },
/* 0F C1 */ { BxAnother, &BX_CPU_C::XADD_EdGd },
/* 0F C2 */ { 0, &BX_CPU_C::BxError },
- from Peter Tattam: add missing instruction MOVNTI to decode table
2002-09-25 07:32:12 +04:00
/* 0F C3 */ { BxAnother, &BX_CPU_C::MOV_EdGd }, // movnti
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F C4 */ { 0, &BX_CPU_C::BxError },
/* 0F C5 */ { 0, &BX_CPU_C::BxError },
/* 0F C6 */ { 0, &BX_CPU_C::BxError },
/* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9 },
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX },
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX },
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX },
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX },
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP },
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP },
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI },
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI },
/* 0F D0 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D1 */ { BxAnotherMMX, &BX_CPU_C::PSRLW_PqQq }, /* MMX */
/* 0F D2 */ { BxAnotherMMX, &BX_CPU_C::PSRLD_PqQq }, /* MMX */
/* 0F D3 */ { BxAnotherMMX, &BX_CPU_C::PSRLQ_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F D4 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D5 */ { BxAnotherMMX, &BX_CPU_C::PMULLW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F D6 */ { 0, &BX_CPU_C::BxError },
/* 0F D7 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D8 */ { BxAnotherMMX, &BX_CPU_C::PSUBUSB_PqQq }, /* MMX */
/* 0F D9 */ { BxAnotherMMX, &BX_CPU_C::PSUBUSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F DA */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F DB */ { BxAnotherMMX, &BX_CPU_C::PAND_PqQq }, /* MMX */
/* 0F DC */ { BxAnotherMMX, &BX_CPU_C::PADDUSB_PqQq }, /* MMX */
/* 0F DD */ { BxAnotherMMX, &BX_CPU_C::PADDUSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F DE */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F DF */ { BxAnotherMMX, &BX_CPU_C::PANDN_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E0 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E1 */ { BxAnotherMMX, &BX_CPU_C::PSRAW_PqQq }, /* MMX */
/* 0F E2 */ { BxAnotherMMX, &BX_CPU_C::PSRAD_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E3 */ { 0, &BX_CPU_C::BxError },
/* 0F E4 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E5 */ { BxAnotherMMX, &BX_CPU_C::PMULHW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E6 */ { 0, &BX_CPU_C::BxError },
/* 0F E7 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E8 */ { BxAnotherMMX, &BX_CPU_C::PSUBSB_PqQq }, /* MMX */
/* 0F E9 */ { BxAnotherMMX, &BX_CPU_C::PSUBSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F EA */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F EB */ { BxAnotherMMX, &BX_CPU_C::POR_PqQq }, /* MMX */
/* 0F EC */ { BxAnotherMMX, &BX_CPU_C::PADDSB_PqQq }, /* MMX */
/* 0F ED */ { BxAnotherMMX, &BX_CPU_C::PADDSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F EE */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F EF */ { BxAnotherMMX, &BX_CPU_C::PXOR_PqQq }, /* MMX */
/* 0F F0 */ { 0, &BX_CPU_C::BxError },
/* 0F F1 */ { BxAnotherMMX, &BX_CPU_C::PSLLW_PqQq }, /* MMX */
/* 0F F2 */ { BxAnotherMMX, &BX_CPU_C::PSLLD_PqQq }, /* MMX */
/* 0F F3 */ { BxAnotherMMX, &BX_CPU_C::PSLLQ_PqQq }, /* MMX */
/* 0F F4 */ { 0, &BX_CPU_C::BxError },
/* 0F F5 */ { BxAnotherMMX, &BX_CPU_C::PMADDWD_PqQq }, /* MMX */
/* 0F F6 */ { 0, &BX_CPU_C::BxError },
/* 0F F7 */ { 0, &BX_CPU_C::BxError },
/* 0F F8 */ { BxAnotherMMX, &BX_CPU_C::PSUBB_PqQq }, /* MMX */
/* 0F F9 */ { BxAnotherMMX, &BX_CPU_C::PSUBW_PqQq }, /* MMX */
/* 0F FA */ { BxAnotherMMX, &BX_CPU_C::PSUBD_PqQq }, /* MMX */
/* 0F FB */ { 0, &BX_CPU_C::BxError },
/* 0F FC */ { BxAnotherMMX, &BX_CPU_C::PADDB_PqQq }, /* MMX */
/* 0F FD */ { BxAnotherMMX, &BX_CPU_C::PADDW_PqQq }, /* MMX */
/* 0F FE */ { BxAnotherMMX, &BX_CPU_C::PADDD_PqQq }, /* MMX */
/* 0F FF */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
// 512 entries for 64bit mod
/* 00 */ { BxAnother, &BX_CPU_C::ADD_EbGb },
/* 01 */ { BxAnother, &BX_CPU_C::ADD_EqGq },
/* 02 */ { BxAnother, &BX_CPU_C::ADD_GbEb },
/* 03 */ { BxAnother, &BX_CPU_C::ADD_GqEq },
/* 04 */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 */ { BxImmediate_Iv, &BX_CPU_C::ADD_RAXId },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 06 */ { 0, &BX_CPU_C::BxError },
/* 07 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 08 */ { BxAnother, &BX_CPU_C::OR_EbGb },
/* 09 */ { BxAnother, &BX_CPU_C::OR_EqGq },
/* 0A */ { BxAnother, &BX_CPU_C::OR_GbEb },
/* 0B */ { BxAnother, &BX_CPU_C::OR_GqEq },
/* 0C */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
/* 0D */ { BxImmediate_Iv, &BX_CPU_C::OR_RAXId },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 0E */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F */ { BxAnother, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 */ { BxAnother, &BX_CPU_C::ADC_EbGb },
/* 11 */ { BxAnother, &BX_CPU_C::ADC_EqGq },
/* 12 */ { BxAnother, &BX_CPU_C::ADC_GbEb },
/* 13 */ { BxAnother, &BX_CPU_C::ADC_GqEq },
/* 14 */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 */ { BxImmediate_Iv, &BX_CPU_C::ADC_RAXId },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 16 */ { 0, &BX_CPU_C::BxError },
/* 17 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 18 */ { BxAnother, &BX_CPU_C::SBB_EbGb },
/* 19 */ { BxAnother, &BX_CPU_C::SBB_EqGq },
/* 1A */ { BxAnother, &BX_CPU_C::SBB_GbEb },
/* 1B */ { BxAnother, &BX_CPU_C::SBB_GqEq },
/* 1C */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
/* 1D */ { BxImmediate_Iv, &BX_CPU_C::SBB_RAXId },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 1E */ { 0, &BX_CPU_C::BxError },
/* 1F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 20 */ { BxAnother, &BX_CPU_C::AND_EbGb },
/* 21 */ { BxAnother, &BX_CPU_C::AND_EqGq },
/* 22 */ { BxAnother, &BX_CPU_C::AND_GbEb },
/* 23 */ { BxAnother, &BX_CPU_C::AND_GqEq },
/* 24 */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
/* 25 */ { BxImmediate_Iv, &BX_CPU_C::AND_RAXId },
/* 26 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // ES:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 27 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 28 */ { BxAnother, &BX_CPU_C::SUB_EbGb },
/* 29 */ { BxAnother, &BX_CPU_C::SUB_EqGq },
/* 2A */ { BxAnother, &BX_CPU_C::SUB_GbEb },
/* 2B */ { BxAnother, &BX_CPU_C::SUB_GqEq },
/* 2C */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
/* 2D */ { BxImmediate_Iv, &BX_CPU_C::SUB_RAXId },
/* 2E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // CS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 2F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 30 */ { BxAnother, &BX_CPU_C::XOR_EbGb },
/* 31 */ { BxAnother, &BX_CPU_C::XOR_EqGq },
/* 32 */ { BxAnother, &BX_CPU_C::XOR_GbEb },
/* 33 */ { BxAnother, &BX_CPU_C::XOR_GqEq },
/* 34 */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
/* 35 */ { BxImmediate_Iv, &BX_CPU_C::XOR_RAXId },
/* 36 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // SS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 37 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 38 */ { BxAnother, &BX_CPU_C::CMP_EbGb },
/* 39 */ { BxAnother, &BX_CPU_C::CMP_EqGq },
/* 3A */ { BxAnother, &BX_CPU_C::CMP_GbEb },
/* 3B */ { BxAnother, &BX_CPU_C::CMP_GqEq },
/* 3C */ { BxImmediate_Ib, &BX_CPU_C::CMP_ALIb },
/* 3D */ { BxImmediate_Iv, &BX_CPU_C::CMP_RAXId },
/* 3E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // DS:
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 3F */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 40 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 41 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 42 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 43 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 44 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 45 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 46 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 47 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 48 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 49 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4A */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4B */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4C */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4D */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4E */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 4F */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REX:
/* 50 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 51 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 52 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 53 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 54 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 55 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 56 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 57 */ { 0, &BX_CPU_C::PUSH_RRX },
/* 58 */ { 0, &BX_CPU_C::POP_RRX },
/* 59 */ { 0, &BX_CPU_C::POP_RRX },
/* 5A */ { 0, &BX_CPU_C::POP_RRX },
/* 5B */ { 0, &BX_CPU_C::POP_RRX },
/* 5C */ { 0, &BX_CPU_C::POP_RRX },
/* 5D */ { 0, &BX_CPU_C::POP_RRX },
/* 5E */ { 0, &BX_CPU_C::POP_RRX },
/* 5F */ { 0, &BX_CPU_C::POP_RRX },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 60 */ { 0, &BX_CPU_C::BxError },
/* 61 */ { 0, &BX_CPU_C::BxError },
/* 62 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 63 */ { BxAnother, &BX_CPU_C::MOVSX_GqEd },
/* 64 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // FS:
/* 65 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // GS:
/* 66 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // OS:
/* 67 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // AS:
/* 68 */ { BxImmediate_Iv, &BX_CPU_C::PUSH64_Id },
/* 69 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::IMUL_GqEqId },
/* 6A */ { BxImmediate_Ib_SE, &BX_CPU_C::PUSH64_Id },
/* 6B */ { BxAnother | BxImmediate_Ib_SE, &BX_CPU_C::IMUL_GqEqId },
/* 6C */ { BxRepeatable, &BX_CPU_C::INSB_YbDX },
/* 6D */ { BxRepeatable, &BX_CPU_C::INSW_YvDX },
/* 6E */ { BxRepeatable, &BX_CPU_C::OUTSB_DXXb },
/* 6F */ { BxRepeatable, &BX_CPU_C::OUTSW_DXXv },
/* 70 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 71 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 72 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 73 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 74 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 75 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 76 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 77 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 78 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 79 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7A */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7B */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7C */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7D */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7E */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 7F */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
/* 80 */ { BxAnother | BxGroup1, NULL, BxOpcodeInfo64G1EbIb },
/* 81 */ { BxAnother | BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfo64G1Eq },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 82 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 83 */ { BxAnother | BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfo64G1Eq },
/* 84 */ { BxAnother, &BX_CPU_C::TEST_EbGb },
/* 85 */ { BxAnother, &BX_CPU_C::TEST_EqGq },
/* 86 */ { BxAnother, &BX_CPU_C::XCHG_EbGb },
/* 87 */ { BxAnother, &BX_CPU_C::XCHG_EqGq },
/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
/* 89 */ { BxAnother, &BX_CPU_C::MOV_EqGq },
/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
/* 8B */ { BxAnother, &BX_CPU_C::MOV_GqEq },
/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
/* 8D */ { BxAnother, &BX_CPU_C::LEA_GqM },
/* 8E */ { BxAnother, &BX_CPU_C::MOV_SwEw },
/* 8F */ { BxAnother, &BX_CPU_C::POP_Eq },
/* 90 */ { 0, &BX_CPU_C::NOP },
/* 91 */ { 0, &BX_CPU_C::XCHG_RRXRAX },
/* 92 */ { 0, &BX_CPU_C::XCHG_RRXRAX },
/* 93 */ { 0, &BX_CPU_C::XCHG_RRXRAX },
/* 94 */ { 0, &BX_CPU_C::XCHG_RRXRAX },
/* 95 */ { 0, &BX_CPU_C::XCHG_RRXRAX },
/* 96 */ { 0, &BX_CPU_C::XCHG_RRXRAX },
/* 97 */ { 0, &BX_CPU_C::XCHG_RRXRAX },
/* 98 */ { 0, &BX_CPU_C::CDQE },
/* 99 */ { 0, &BX_CPU_C::CQO },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 9A */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 9B */ { 0, &BX_CPU_C::FWAIT },
/* 9C */ { 0, &BX_CPU_C::PUSHF_Fv },
/* 9D */ { 0, &BX_CPU_C::POPF_Fv },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* 9E */ { 0, &BX_CPU_C::BxError },
/* 9F */ { 0, &BX_CPU_C::BxError },
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
/* A0 */ { BxImmediate_O, &BX_CPU_C::MOV_ALOq },
/* A1 */ { BxImmediate_O, &BX_CPU_C::MOV_RAXOq },
/* A2 */ { BxImmediate_O, &BX_CPU_C::MOV_OqAL },
/* A3 */ { BxImmediate_O, &BX_CPU_C::MOV_OqRAX },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* A4 */ { BxRepeatable, &BX_CPU_C::MOVSB_XbYb },
/* A5 */ { BxRepeatable, &BX_CPU_C::MOVSW_XvYv },
/* A6 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSB_XbYb },
/* A7 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSW_XvYv },
/* A8 */ { BxImmediate_Ib, &BX_CPU_C::TEST_ALIb },
/* A9 */ { BxImmediate_Iv, &BX_CPU_C::TEST_RAXId },
/* AA */ { BxRepeatable, &BX_CPU_C::STOSB_YbAL },
/* AB */ { BxRepeatable, &BX_CPU_C::STOSW_YveAX },
/* AC */ { BxRepeatable, &BX_CPU_C::LODSB_ALXb },
/* AD */ { BxRepeatable, &BX_CPU_C::LODSW_eAXXv },
/* AE */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASB_ALXb },
/* AF */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASW_eAXXv },
/* B0 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B1 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B2 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B3 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
/* B4 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B5 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B6 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B7 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RHIb },
/* B8 */ { BxImmediate_Iq, &BX_CPU_C::MOV_RRXIq },
/* B9 */ { BxImmediate_Iq, &BX_CPU_C::MOV_RRXIq },
/* BA */ { BxImmediate_Iq, &BX_CPU_C::MOV_RRXIq },
/* BB */ { BxImmediate_Iq, &BX_CPU_C::MOV_RRXIq },
/* BC */ { BxImmediate_Iq, &BX_CPU_C::MOV_RRXIq },
/* BD */ { BxImmediate_Iq, &BX_CPU_C::MOV_RRXIq },
/* BE */ { BxImmediate_Iq, &BX_CPU_C::MOV_RRXIq },
/* BF */ { BxImmediate_Iq, &BX_CPU_C::MOV_RRXIq },
/* C0 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfo64G2Eb },
/* C1 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfo64G2Eq },
/* C2 */ { BxImmediate_Iw, &BX_CPU_C::RETnear64_Iw },
/* C3 */ { 0, &BX_CPU_C::RETnear64 },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* C4 */ { 0, &BX_CPU_C::BxError },
/* C5 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* C6 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::MOV_EbIb },
/* C7 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::MOV_EqId },
/* C8 */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
/* C9 */ { 0, &BX_CPU_C::LEAVE64 },
/* CA */ { BxImmediate_Iw, &BX_CPU_C::RETfar32_Iw },
/* CB */ { 0, &BX_CPU_C::RETfar64 },
/* CC */ { 0, &BX_CPU_C::INT3 },
/* CD */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* CE */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* CF */ { 0, &BX_CPU_C::IRET64 },
/* D0 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Eb },
/* D1 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Eq },
/* D2 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Eb },
/* D3 */ { BxAnother | BxGroup2, NULL, BxOpcodeInfo64G2Eq },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* D4 */ { 0, &BX_CPU_C::BxError },
/* D5 */ { 0, &BX_CPU_C::BxError },
/* D6 */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* D7 */ { 0, &BX_CPU_C::XLAT },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* D8 */ { BxAnotherFPU, &BX_CPU_C::ESC0 },
/* D9 */ { BxAnotherFPU, &BX_CPU_C::ESC1 },
/* DA */ { BxAnotherFPU, &BX_CPU_C::ESC2 },
/* DB */ { BxAnotherFPU, &BX_CPU_C::ESC3 },
/* DC */ { BxAnotherFPU, &BX_CPU_C::ESC4 },
/* DD */ { BxAnotherFPU, &BX_CPU_C::ESC5 },
/* DE */ { BxAnotherFPU, &BX_CPU_C::ESC6 },
/* DF */ { BxAnotherFPU, &BX_CPU_C::ESC7 },
Got rid of the KPL64Hacks macro. The fixes below eliminated it. Created 64-bit versions of some branch instructions and changed fetchdecode64.cc to use them instead. This keeps the #ifdef pollution down for 32-bit code and made fixing them easier. They needed to clear the upper bits of RIP for 16-bit operand sizes. They also should not have had a protection limit check in them, especially since that field is still 32-bit in cpu.h, so there's no way to set nominal 64-bit values. The 32-bit versions were also not honoring the upper 32-bits of RIP. LOOPNE64_Jb LOOPE64_Jb LOOP64_Jb JCXZ64_Jb Changed all occurances of JCC_Jw/JCC_Jd in fetchdecode64.cc to use JCC_Jq, which was coded already. Both JMP_Jq and JCC_Jq are now fixed w.r.t. 16-bit opsizes and upper RIP bit clearing.
2002-09-27 11:01:02 +04:00
/* E0 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPNE64_Jb },
/* E1 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPE64_Jb },
/* E2 */ { BxImmediate_BrOff8, &BX_CPU_C::LOOP64_Jb },
/* E3 */ { BxImmediate_BrOff8, &BX_CPU_C::JCXZ64_Jb },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* E4 */ { BxImmediate_Ib, &BX_CPU_C::IN_ALIb },
/* E5 */ { BxImmediate_Ib, &BX_CPU_C::IN_eAXIb },
/* E6 */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAL },
/* E7 */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbeAX },
/* E8 */ { BxImmediate_BrOff32, &BX_CPU_C::CALL_Aq },
/* E9 */ { BxImmediate_BrOff32, &BX_CPU_C::JMP_Jq },
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 19:29:51 +04:00
/* EA */ { 0, &BX_CPU_C::BxError },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* EB */ { BxImmediate_BrOff8, &BX_CPU_C::JMP_Jq },
/* EC */ { 0, &BX_CPU_C::IN_ALDX },
/* ED */ { 0, &BX_CPU_C::IN_eAXDX },
/* EE */ { 0, &BX_CPU_C::OUT_DXAL },
/* EF */ { 0, &BX_CPU_C::OUT_DXeAX },
/* F0 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // LOCK:
/* F1 */ { 0, &BX_CPU_C::INT1 },
/* F2 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REPNE/REPNZ
/* F3 */ { BxPrefix | BxAnother, &BX_CPU_C::BxError }, // REP,REPE/REPZ
/* F4 */ { 0, &BX_CPU_C::HLT },
/* F5 */ { 0, &BX_CPU_C::CMC },
/* F6 */ { BxAnother | BxGroup3, NULL, BxOpcodeInfo64G3Eb },
/* F7 */ { BxAnother | BxGroup3, NULL, BxOpcodeInfo64G3Eq },
/* F8 */ { 0, &BX_CPU_C::CLC },
/* F9 */ { 0, &BX_CPU_C::STC },
/* FA */ { 0, &BX_CPU_C::CLI },
/* FB */ { 0, &BX_CPU_C::STI },
/* FC */ { 0, &BX_CPU_C::CLD },
/* FD */ { 0, &BX_CPU_C::STD },
/* FE */ { BxAnother | BxGroup4, NULL, BxOpcodeInfo64G4 },
/* FF */ { BxAnother | BxGroup5, NULL, BxOpcodeInfo64G5q },
/* 0F 00 */ { BxAnother | BxGroup6, NULL, BxOpcodeInfo64G6 },
/* 0F 01 */ { BxAnother | BxGroup7, NULL, BxOpcodeInfo64G7 },
/* 0F 02 */ { BxAnother, &BX_CPU_C::LAR_GvEw },
/* 0F 03 */ { BxAnother, &BX_CPU_C::LSL_GvEw },
/* 0F 04 */ { 0, &BX_CPU_C::BxError },
Implemented SYSCALL and SYSRET as part of x86-64 emulation. Since the SYSCALL replaces the LOADALL instruction, it is incompatible with earlier CPU types. At moment, the SYSCALL is only enabled by x86-64 emulation, but the code can be incorporated in IA32 only emulations. Instructions added: 0F 05 SYSCALL (replaces LOADALL) 0F 07 SYSRET (new) TODO: restructure #if ... so that it can be used by non x86-64 emulations.
2002-09-25 16:54:41 +04:00
/* 0F 05 */ { 0, &BX_CPU_C::SYSCALL },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 06 */ { 0, &BX_CPU_C::CLTS },
Implemented SYSCALL and SYSRET as part of x86-64 emulation. Since the SYSCALL replaces the LOADALL instruction, it is incompatible with earlier CPU types. At moment, the SYSCALL is only enabled by x86-64 emulation, but the code can be incorporated in IA32 only emulations. Instructions added: 0F 05 SYSCALL (replaces LOADALL) 0F 07 SYSRET (new) TODO: restructure #if ... so that it can be used by non x86-64 emulations.
2002-09-25 16:54:41 +04:00
/* 0F 07 */ { 0, &BX_CPU_C::SYSRET },
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 08 */ { 0, &BX_CPU_C::INVD },
/* 0F 09 */ { 0, &BX_CPU_C::WBINVD },
/* 0F 0A */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 0B */ { 0, &BX_CPU_C::UndefinedOpcode }, /* UD2 opcode */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 0C */ { 0, &BX_CPU_C::BxError },
- from Peter Tattam: change prefetch instructions to nops instead of undefined
2002-09-23 18:25:29 +04:00
/* 0F 0D */ { BxAnother, &BX_CPU_C::NOP }, // PREFETCH L1
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 0E */ { 0, &BX_CPU_C::BxError },
/* 0F 0F */ { 0, &BX_CPU_C::BxError },
/* 0F 10 */ { 0, &BX_CPU_C::BxError },
/* 0F 11 */ { 0, &BX_CPU_C::BxError },
/* 0F 12 */ { 0, &BX_CPU_C::BxError },
/* 0F 13 */ { 0, &BX_CPU_C::BxError },
/* 0F 14 */ { 0, &BX_CPU_C::BxError },
/* 0F 15 */ { 0, &BX_CPU_C::BxError },
/* 0F 16 */ { 0, &BX_CPU_C::BxError },
/* 0F 17 */ { 0, &BX_CPU_C::BxError },
/* 0F 18 */ { BxAnother, &BX_CPU_C::NOP }, // PREFETCH
/* 0F 19 */ { 0, &BX_CPU_C::BxError },
/* 0F 1A */ { 0, &BX_CPU_C::BxError },
/* 0F 1B */ { 0, &BX_CPU_C::BxError },
/* 0F 1C */ { 0, &BX_CPU_C::BxError },
/* 0F 1D */ { 0, &BX_CPU_C::BxError },
/* 0F 1E */ { 0, &BX_CPU_C::BxError },
/* 0F 1F */ { 0, &BX_CPU_C::BxError },
/* 0F 20 */ { BxAnother, &BX_CPU_C::MOV_RqCq },
/* 0F 21 */ { BxAnother, &BX_CPU_C::MOV_RqDq },
/* 0F 22 */ { BxAnother, &BX_CPU_C::MOV_CqRq },
/* 0F 23 */ { BxAnother, &BX_CPU_C::MOV_DqRq },
/* 0F 24 */ { 0, &BX_CPU_C::BxError },
/* 0F 25 */ { 0, &BX_CPU_C::BxError },
/* 0F 26 */ { 0, &BX_CPU_C::BxError },
/* 0F 27 */ { 0, &BX_CPU_C::BxError },
/* 0F 28 */ { 0, &BX_CPU_C::BxError },
/* 0F 29 */ { 0, &BX_CPU_C::BxError },
/* 0F 2A */ { 0, &BX_CPU_C::BxError },
/* 0F 2B */ { 0, &BX_CPU_C::BxError },
/* 0F 2C */ { 0, &BX_CPU_C::BxError },
/* 0F 2D */ { 0, &BX_CPU_C::BxError },
/* 0F 2E */ { 0, &BX_CPU_C::BxError },
/* 0F 2F */ { 0, &BX_CPU_C::BxError },
/* 0F 30 */ { 0, &BX_CPU_C::WRMSR },
/* 0F 31 */ { 0, &BX_CPU_C::RDTSC },
/* 0F 32 */ { 0, &BX_CPU_C::RDMSR },
/* 0F 33 */ { 0, &BX_CPU_C::BxError },
/* 0F 34 */ { 0, &BX_CPU_C::BxError },
/* 0F 35 */ { 0, &BX_CPU_C::BxError },
/* 0F 36 */ { 0, &BX_CPU_C::BxError },
/* 0F 37 */ { 0, &BX_CPU_C::BxError },
/* 0F 38 */ { 0, &BX_CPU_C::BxError },
/* 0F 39 */ { 0, &BX_CPU_C::BxError },
/* 0F 3A */ { 0, &BX_CPU_C::BxError },
/* 0F 3B */ { 0, &BX_CPU_C::BxError },
/* 0F 3C */ { 0, &BX_CPU_C::BxError },
/* 0F 3D */ { 0, &BX_CPU_C::BxError },
/* 0F 3E */ { 0, &BX_CPU_C::BxError },
/* 0F 3F */ { 0, &BX_CPU_C::BxError },
/* 0F 40 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 41 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 42 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 43 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 44 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 45 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 46 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 47 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 48 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 49 */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 4A */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 4B */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 4C */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 4D */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 4E */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 4F */ { BxAnother, &BX_CPU_C::CMOV_GqEq },
/* 0F 50 */ { 0, &BX_CPU_C::BxError },
/* 0F 51 */ { 0, &BX_CPU_C::BxError },
/* 0F 52 */ { 0, &BX_CPU_C::BxError },
/* 0F 53 */ { 0, &BX_CPU_C::BxError },
/* 0F 54 */ { 0, &BX_CPU_C::BxError },
/* 0F 55 */ { 0, &BX_CPU_C::BxError },
/* 0F 56 */ { 0, &BX_CPU_C::BxError },
/* 0F 57 */ { 0, &BX_CPU_C::BxError },
/* 0F 58 */ { 0, &BX_CPU_C::BxError },
/* 0F 59 */ { 0, &BX_CPU_C::BxError },
/* 0F 5A */ { 0, &BX_CPU_C::BxError },
/* 0F 5B */ { 0, &BX_CPU_C::BxError },
/* 0F 5C */ { 0, &BX_CPU_C::BxError },
/* 0F 5D */ { 0, &BX_CPU_C::BxError },
/* 0F 5E */ { 0, &BX_CPU_C::BxError },
/* 0F 5F */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 60 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLBW_PqQd }, /* MMX */
/* 0F 61 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLWD_PqQd }, /* MMX */
/* 0F 62 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKLDQ_PqQd }, /* MMX */
/* 0F 63 */ { BxAnotherMMX, &BX_CPU_C::PACKSSWB_PqQq }, /* MMX */
/* 0F 64 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTB_PqQq }, /* MMX */
/* 0F 65 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTW_PqQq }, /* MMX */
/* 0F 66 */ { BxAnotherMMX, &BX_CPU_C::PCMPGTD_PqQq }, /* MMX */
/* 0F 67 */ { BxAnotherMMX, &BX_CPU_C::PACKUSWB_PqQq }, /* MMX */
/* 0F 68 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHBW_PqQq }, /* MMX */
/* 0F 69 */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHWD_PqQq }, /* MMX */
/* 0F 6A */ { BxAnotherMMX, &BX_CPU_C::PUNPCKHDQ_PqQq }, /* MMX */
/* 0F 6B */ { BxAnotherMMX, &BX_CPU_C::PACKSSDW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 6C */ { 0, &BX_CPU_C::BxError },
/* 0F 6D */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 6E */ { BxAnotherMMX, &BX_CPU_C::MOVD_PqEd }, /* MMX */
/* 0F 6F */ { BxAnotherMMX, &BX_CPU_C::MOVQ_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 70 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
#if BX_SUPPORT_MMX
/* 0F 71 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAw },
/* 0F 72 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAd },
/* 0F 73 */ { BxAnother | BxGroupA, NULL, BxOpcodeInfoGAq },
#else
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 71 */ { 0, &BX_CPU_C::BxError },
/* 0F 72 */ { 0, &BX_CPU_C::BxError },
/* 0F 73 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
#endif
/* 0F 74 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQB_PqQq }, /* MMX */
/* 0F 75 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQW_PqQq }, /* MMX */
/* 0F 76 */ { BxAnotherMMX, &BX_CPU_C::PCMPEQD_PqQq }, /* MMX */
/* 0F 77 */ { 0, &BX_CPU_C::EMMS }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 78 */ { 0, &BX_CPU_C::BxError },
/* 0F 79 */ { 0, &BX_CPU_C::BxError },
/* 0F 7A */ { 0, &BX_CPU_C::BxError },
/* 0F 7B */ { 0, &BX_CPU_C::BxError },
/* 0F 7C */ { 0, &BX_CPU_C::BxError },
/* 0F 7D */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F 7E */ { BxAnotherMMX, &BX_CPU_C::MOVD_EdPd }, /* MMX */
/* 0F 7F */ { BxAnotherMMX, &BX_CPU_C::MOVQ_QqPq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F 80 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 81 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 82 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 83 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 84 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 85 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 86 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 87 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 88 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 89 */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8A */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8B */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8C */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8D */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8E */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 8F */ { BxImmediate_BrOff32, &BX_CPU_C::JCC_Jq },
/* 0F 90 */ { BxAnother, &BX_CPU_C::SETO_Eb },
/* 0F 91 */ { BxAnother, &BX_CPU_C::SETNO_Eb },
/* 0F 92 */ { BxAnother, &BX_CPU_C::SETB_Eb },
/* 0F 93 */ { BxAnother, &BX_CPU_C::SETNB_Eb },
/* 0F 94 */ { BxAnother, &BX_CPU_C::SETZ_Eb },
/* 0F 95 */ { BxAnother, &BX_CPU_C::SETNZ_Eb },
/* 0F 96 */ { BxAnother, &BX_CPU_C::SETBE_Eb },
/* 0F 97 */ { BxAnother, &BX_CPU_C::SETNBE_Eb },
/* 0F 98 */ { BxAnother, &BX_CPU_C::SETS_Eb },
/* 0F 99 */ { BxAnother, &BX_CPU_C::SETNS_Eb },
/* 0F 9A */ { BxAnother, &BX_CPU_C::SETP_Eb },
/* 0F 9B */ { BxAnother, &BX_CPU_C::SETNP_Eb },
/* 0F 9C */ { BxAnother, &BX_CPU_C::SETL_Eb },
/* 0F 9D */ { BxAnother, &BX_CPU_C::SETNL_Eb },
/* 0F 9E */ { BxAnother, &BX_CPU_C::SETLE_Eb },
/* 0F 9F */ { BxAnother, &BX_CPU_C::SETNLE_Eb },
/* 0F A0 */ { 0, &BX_CPU_C::PUSH64_FS },
/* 0F A1 */ { 0, &BX_CPU_C::POP64_FS },
/* 0F A2 */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EvGv },
/* 0F A4 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHLD_EqGq },
/* 0F A5 */ { BxAnother, &BX_CPU_C::SHLD_EqGq },
/* 0F A6 */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
/* 0F A7 */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
/* 0F A8 */ { 0, &BX_CPU_C::PUSH64_GS },
/* 0F A9 */ { 0, &BX_CPU_C::POP64_GS },
/* 0F AA */ { 0, &BX_CPU_C::RSM },
/* 0F AB */ { BxAnother, &BX_CPU_C::BTS_EvGv },
/* 0F AC */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHRD_EqGq },
/* 0F AD */ { BxAnother, &BX_CPU_C::SHRD_EqGq },
/* 0F AE */ { BxAnother | BxGroup15, NULL, BxOpcodeInfo64G15 },
/* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GqEq },
/* 0F B0 */ { BxAnother, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 */ { BxAnother, &BX_CPU_C::CMPXCHG_EqGq },
/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
/* 0F B3 */ { BxAnother, &BX_CPU_C::BTR_EvGv },
/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GqEb },
/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GqEw },
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
/* 0F B9 */ { 0, &BX_CPU_C::BxError },
/* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
/* 0F BB */ { BxAnother, &BX_CPU_C::BTC_EvGv },
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GvEv },
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GvEv },
/* 0F BE */ { BxAnother, &BX_CPU_C::MOVSX_GqEb },
/* 0F BF */ { BxAnother, &BX_CPU_C::MOVSX_GqEw },
/* 0F C0 */ { BxAnother, &BX_CPU_C::XADD_EbGb },
/* 0F C1 */ { BxAnother, &BX_CPU_C::XADD_EqGq },
/* 0F C2 */ { 0, &BX_CPU_C::BxError },
- from Peter Tattam: add missing instruction MOVNTI to decode table
2002-09-25 07:32:12 +04:00
/* 0F C3 */ { BxAnother, &BX_CPU_C::MOV_EqGq }, // movnti
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F C4 */ { 0, &BX_CPU_C::BxError },
/* 0F C5 */ { 0, &BX_CPU_C::BxError },
/* 0F C6 */ { 0, &BX_CPU_C::BxError },
/* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9 },
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_RAX },
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_RCX },
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_RDX },
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_RBX },
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_RSP },
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_RBP },
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_RSI },
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_RDI },
/* 0F D0 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D1 */ { BxAnotherMMX, &BX_CPU_C::PSRLW_PqQq }, /* MMX */
/* 0F D2 */ { BxAnotherMMX, &BX_CPU_C::PSRLD_PqQq }, /* MMX */
/* 0F D3 */ { BxAnotherMMX, &BX_CPU_C::PSRLQ_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F D4 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D5 */ { BxAnotherMMX, &BX_CPU_C::PMULLW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F D6 */ { 0, &BX_CPU_C::BxError },
/* 0F D7 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F D8 */ { BxAnotherMMX, &BX_CPU_C::PSUBUSB_PqQq }, /* MMX */
/* 0F D9 */ { BxAnotherMMX, &BX_CPU_C::PSUBUSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F DA */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F DB */ { BxAnotherMMX, &BX_CPU_C::PAND_PqQq }, /* MMX */
/* 0F DC */ { BxAnotherMMX, &BX_CPU_C::PADDUSB_PqQq }, /* MMX */
/* 0F DD */ { BxAnotherMMX, &BX_CPU_C::PADDUSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F DE */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F DF */ { BxAnotherMMX, &BX_CPU_C::PANDN_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E0 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E1 */ { BxAnotherMMX, &BX_CPU_C::PSRAW_PqQq }, /* MMX */
/* 0F E2 */ { BxAnotherMMX, &BX_CPU_C::PSRAD_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E3 */ { 0, &BX_CPU_C::BxError },
/* 0F E4 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E5 */ { BxAnotherMMX, &BX_CPU_C::PMULHW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F E6 */ { 0, &BX_CPU_C::BxError },
/* 0F E7 */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F E8 */ { BxAnotherMMX, &BX_CPU_C::PSUBSB_PqQq }, /* MMX */
/* 0F E9 */ { BxAnotherMMX, &BX_CPU_C::PSUBSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F EA */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F EB */ { BxAnotherMMX, &BX_CPU_C::POR_PqQq }, /* MMX */
/* 0F EC */ { BxAnotherMMX, &BX_CPU_C::PADDSB_PqQq }, /* MMX */
/* 0F ED */ { BxAnotherMMX, &BX_CPU_C::PADDSW_PqQq }, /* MMX */
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
/* 0F EE */ { 0, &BX_CPU_C::BxError },
Added MMX opcodes to x86-64 mode Fixed problem with fetching extra byte in ESCx opcodes if FPU is disabled
2002-09-27 13:56:40 +04:00
/* 0F EF */ { BxAnotherMMX, &BX_CPU_C::PXOR_PqQq }, /* MMX */
/* 0F F0 */ { 0, &BX_CPU_C::BxError },
/* 0F F1 */ { BxAnotherMMX, &BX_CPU_C::PSLLW_PqQq }, /* MMX */
/* 0F F2 */ { BxAnotherMMX, &BX_CPU_C::PSLLD_PqQq }, /* MMX */
/* 0F F3 */ { BxAnotherMMX, &BX_CPU_C::PSLLQ_PqQq }, /* MMX */
/* 0F F4 */ { 0, &BX_CPU_C::BxError },
/* 0F F5 */ { BxAnotherMMX, &BX_CPU_C::PMADDWD_PqQq }, /* MMX */
/* 0F F6 */ { 0, &BX_CPU_C::BxError },
/* 0F F7 */ { 0, &BX_CPU_C::BxError },
/* 0F F8 */ { BxAnotherMMX, &BX_CPU_C::PSUBB_PqQq }, /* MMX */
/* 0F F9 */ { BxAnotherMMX, &BX_CPU_C::PSUBW_PqQq }, /* MMX */
/* 0F FA */ { BxAnotherMMX, &BX_CPU_C::PSUBD_PqQq }, /* MMX */
/* 0F FB */ { 0, &BX_CPU_C::BxError },
/* 0F FC */ { BxAnotherMMX, &BX_CPU_C::PADDB_PqQq }, /* MMX */
/* 0F FD */ { BxAnotherMMX, &BX_CPU_C::PADDW_PqQq }, /* MMX */
/* 0F FE */ { BxAnotherMMX, &BX_CPU_C::PADDD_PqQq }, /* MMX */
/* 0F FF */ { 0, &BX_CPU_C::BxError }
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
};
unsigned
- Added an instruction cache. Size is fixed for the moment, but if you hand edit cpu/cpu.h, and change BxICacheEntries, you can try different sizes. I'll make this more flexible with configure. For now, use "--enable-icache" with no parameters. - Modified fetchdecode.cc/fetchdecode64.cc just enough so that instructions which encode a direct address now use a memory resolution function which just sticks the immediate address into rm_addr. With cached instructions we need this.
2002-09-19 23:17:20 +04:00
BX_CPU_C::fetchDecode64(Bit8u *iptr, bxInstruction_c *instruction,
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
unsigned remain)
{
// remain must be at least 1
unsigned b1, b2, ilen=1, attr;
unsigned imm_mode, offset, rex_r,rex_x,rex_b;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
unsigned rm, mod, nnn;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
offset = 512*1;
rex_r = 0;
rex_x = 0;
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
rex_b = 0;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = NULL;
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->initMetaInfo(
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
BX_SEG_REG_NULL,
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
/*os32*/ 1, // operand size 32 override defaults to 1
/*as32*/ 1, // address size 32 override defaults to 1
/*os64*/ 0, // operand size 64 override defaults to 0
/*as64*/ 1, // address size 64 override defaults to 1
Converted all the remaining available separate fields in bxInstruction_c to bitfields. bxInstruction_c is now 24 bytes, including 4 for the memory addr resolution function pointer, and 4 for the execution function pointer (16 + 4 + 4). Coded more accessors, to abstract access from most code.
2002-09-18 12:00:43 +04:00
/*extend8bit*/ 0,
/*repUsed*/ 0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
fetch_b1:
b1 = *iptr++;
another_byte:
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
//offset = (instruction->os32L()+instruction->os_64 <<1) << 9; // * 512
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
//BX_DEBUG (("op: 0x%02x offset: 0x%04x",b1,offset));
Converted all the remaining available separate fields in bxInstruction_c to bitfields. bxInstruction_c is now 24 bytes, including 4 for the memory addr resolution function pointer, and 4 for the execution function pointer (16 + 4 + 4). Coded more accessors, to abstract access from most code.
2002-09-18 12:00:43 +04:00
attr = BxOpcodeInfo64[b1+offset].Attr;
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
if (attr & BxAnother) {
if (attr & BxPrefix) {
switch (b1) {
case 0x66: // OpSize
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_OS(CPU_ID);
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (!instruction->os64L()) {
instruction->setOs32B(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
offset = 0;
}
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
case 0x67: // AddrSize
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_AS(CPU_ID);
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->setAs64B(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
case 0x40:
case 0x41:
case 0x42:
case 0x43:
case 0x44:
case 0x45:
case 0x46:
case 0x47:
case 0x48:
case 0x49:
case 0x4A:
case 0x4B:
case 0x4C:
case 0x4D:
case 0x4E:
case 0x4F:
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_EXTEND8B(CPU_ID);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->assertExtend8bit();
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
//BX_DEBUG (("REX byte = %02x",b1));
if (b1 & 0x8) {
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->assertOs64();
instruction->assertOs32();
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
offset = 512*2;
//BX_DEBUG ((" 64bit")):
}
if (b1 & 0x4) {
rex_r = 8;
//BX_DEBUG((" reg+8"));
}
if (b1 & 0x2) {
rex_x = 8;
//BX_DEBUG((" index+8"));
}
if (b1 & 0x1) {
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
rex_b = 8;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
//BX_DEBUG((" base+8"));
}
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
case 0xf2: // REPNE/REPNZ
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_REPNE(CPU_ID);
instruction->setRepUsed(b1 & 3);
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case 0xf3: // REP/REPE/REPZ
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_REP(CPU_ID);
Converted all the remaining available separate fields in bxInstruction_c to bitfields. bxInstruction_c is now 24 bytes, including 4 for the memory addr resolution function pointer, and 4 for the execution function pointer (16 + 4 + 4). Coded more accessors, to abstract access from most code.
2002-09-18 12:00:43 +04:00
instruction->setRepUsed(b1 & 3);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
case 0x2e: // CS:
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_CS(CPU_ID);
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->setSeg(BX_SEG_REG_CS);
Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead of (1 & (val32>>N)), and added a getB_?F() accessor for special cases which need a strict binary value (exactly 0 or 1). Most code only needed a value for logical comparison. I modified the special cases which do need a binary number for shifting and comparison between flags, to use the special getB_?F() accessor. Cleaned up memory.cc functions a little, now that all accesses are within a single page. Fixed a (not very likely encountered) bug in fetchdecode.cc (and fetchdecode64.cc) where a 2-byte opcode starting with a prefix starts at the last offset on a page. There were no checks on the segment overrides for a boundary condition. I added them. The eflags enhancements added just a tiny bit of performance.
2002-09-22 22:22:24 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case 0x26: // ES:
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_ES(CPU_ID);
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->setSeg(BX_SEG_REG_ES);
Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead of (1 & (val32>>N)), and added a getB_?F() accessor for special cases which need a strict binary value (exactly 0 or 1). Most code only needed a value for logical comparison. I modified the special cases which do need a binary number for shifting and comparison between flags, to use the special getB_?F() accessor. Cleaned up memory.cc functions a little, now that all accesses are within a single page. Fixed a (not very likely encountered) bug in fetchdecode.cc (and fetchdecode64.cc) where a 2-byte opcode starting with a prefix starts at the last offset on a page. There were no checks on the segment overrides for a boundary condition. I added them. The eflags enhancements added just a tiny bit of performance.
2002-09-22 22:22:24 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case 0x36: // SS:
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_SS(CPU_ID);
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->setSeg(BX_SEG_REG_SS);
Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead of (1 & (val32>>N)), and added a getB_?F() accessor for special cases which need a strict binary value (exactly 0 or 1). Most code only needed a value for logical comparison. I modified the special cases which do need a binary number for shifting and comparison between flags, to use the special getB_?F() accessor. Cleaned up memory.cc functions a little, now that all accesses are within a single page. Fixed a (not very likely encountered) bug in fetchdecode.cc (and fetchdecode64.cc) where a 2-byte opcode starting with a prefix starts at the last offset on a page. There were no checks on the segment overrides for a boundary condition. I added them. The eflags enhancements added just a tiny bit of performance.
2002-09-22 22:22:24 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case 0x3e: // DS:
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_DS(CPU_ID);
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->setSeg(BX_SEG_REG_DS);
Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead of (1 & (val32>>N)), and added a getB_?F() accessor for special cases which need a strict binary value (exactly 0 or 1). Most code only needed a value for logical comparison. I modified the special cases which do need a binary number for shifting and comparison between flags, to use the special getB_?F() accessor. Cleaned up memory.cc functions a little, now that all accesses are within a single page. Fixed a (not very likely encountered) bug in fetchdecode.cc (and fetchdecode64.cc) where a 2-byte opcode starting with a prefix starts at the last offset on a page. There were no checks on the segment overrides for a boundary condition. I added them. The eflags enhancements added just a tiny bit of performance.
2002-09-22 22:22:24 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case 0x64: // FS:
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_FS(CPU_ID);
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->setSeg(BX_SEG_REG_FS);
Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead of (1 & (val32>>N)), and added a getB_?F() accessor for special cases which need a strict binary value (exactly 0 or 1). Most code only needed a value for logical comparison. I modified the special cases which do need a binary number for shifting and comparison between flags, to use the special getB_?F() accessor. Cleaned up memory.cc functions a little, now that all accesses are within a single page. Fixed a (not very likely encountered) bug in fetchdecode.cc (and fetchdecode64.cc) where a 2-byte opcode starting with a prefix starts at the last offset on a page. There were no checks on the segment overrides for a boundary condition. I added them. The eflags enhancements added just a tiny bit of performance.
2002-09-22 22:22:24 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case 0x65: // GS:
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_GS(CPU_ID);
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->setSeg(BX_SEG_REG_GS);
Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead of (1 & (val32>>N)), and added a getB_?F() accessor for special cases which need a strict binary value (exactly 0 or 1). Most code only needed a value for logical comparison. I modified the special cases which do need a binary number for shifting and comparison between flags, to use the special getB_?F() accessor. Cleaned up memory.cc functions a little, now that all accesses are within a single page. Fixed a (not very likely encountered) bug in fetchdecode.cc (and fetchdecode64.cc) where a 2-byte opcode starting with a prefix starts at the last offset on a page. There were no checks on the segment overrides for a boundary condition. I added them. The eflags enhancements added just a tiny bit of performance.
2002-09-22 22:22:24 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case 0xf0: // LOCK:
Committed patches/patch-bochs-instrumentation from Stanislav. Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc, and cpu.cc since the original patches, so I did some patch integration by hand. Check the placement of the macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE() in cpu.cc to make sure I go them right. Also, I changed the parameters to BX_INSTR_OPCODE() to update them to the new code. I put some comments before each of these to help determine if the placement is right. These macros are only compiled in if you are gathering instrumentation data from bochs, so they shouldn't effect others.
2002-09-28 04:54:05 +04:00
BX_INSTR_PREFIX_LOCK(CPU_ID);
Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead of (1 & (val32>>N)), and added a getB_?F() accessor for special cases which need a strict binary value (exactly 0 or 1). Most code only needed a value for logical comparison. I modified the special cases which do need a binary number for shifting and comparison between flags, to use the special getB_?F() accessor. Cleaned up memory.cc functions a little, now that all accesses are within a single page. Fixed a (not very likely encountered) bug in fetchdecode.cc (and fetchdecode64.cc) where a 2-byte opcode starting with a prefix starts at the last offset on a page. There were no checks on the segment overrides for a boundary condition. I added them. The eflags enhancements added just a tiny bit of performance.
2002-09-22 22:22:24 +04:00
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
default:
BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1));
Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead of (1 & (val32>>N)), and added a getB_?F() accessor for special cases which need a strict binary value (exactly 0 or 1). Most code only needed a value for logical comparison. I modified the special cases which do need a binary number for shifting and comparison between flags, to use the special getB_?F() accessor. Cleaned up memory.cc functions a little, now that all accesses are within a single page. Fixed a (not very likely encountered) bug in fetchdecode.cc (and fetchdecode64.cc) where a 2-byte opcode starting with a prefix starts at the last offset on a page. There were no checks on the segment overrides for a boundary condition. I added them. The eflags enhancements added just a tiny bit of performance.
2002-09-22 22:22:24 +04:00
return(0);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
}
}
// opcode requires another byte
if (ilen < remain) {
ilen++;
b2 = *iptr++;
if (b1 == 0x0f) {
// 2-byte prefix
b1 = 0x100 | b2;
goto another_byte;
}
}
else
return(0);
// Parse mod-nnn-rm and related bytes
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
mod = b2 & 0xc0;
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
nnn = ((b2 >> 3) & 0x07) | rex_r;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
rm = b2 & 0x07;
instruction->modRMForm.modRMData = (b2<<20);
instruction->modRMForm.modRMData |= mod;
instruction->modRMForm.modRMData |= (nnn<<8);
if (mod == 0xc0) { // mod == 11b
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
rm |= rex_b;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.modRMData |= rm;
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
instruction->metaInfo |= (1<<22); // (modC0)
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
goto modrm_done;
}
if (rm != 4) {
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
rm |= rex_b;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
}
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.modRMData |= rm;
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (instruction->as64L()) {
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
// 64-bit addressing modes; note that mod==11b handled above
if (rm != 4) { // no s-i-b byte
#if BX_DYNAMIC_TRANSLATION
instruction->DTMemRegsUsed = 1<<rm; // except for mod=00b rm=100b
#endif
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (mod == 0x00) { // mod == 00b
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve64Mod0[rm];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0[rm];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_SEG_REG_DS);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
if (rm == 5) {
if ((ilen+3) < remain) {
Bit32u imm32u;
imm32u = *iptr++;
imm32u |= (*iptr++) << 8;
imm32u |= (*iptr++) << 16;
imm32u |= (*iptr++) << 24;
ilen += 4;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.displ32u = imm32u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
#if BX_DYNAMIC_TRANSLATION
instruction->DTMemRegsUsed = 0;
#endif
goto modrm_done;
}
else {
return(0);
}
}
// mod==00b, rm!=4, rm!=5
goto modrm_done;
}
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (mod == 0x40) { // mod == 01b
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve64Mod1or2[rm];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01_rm32[rm]);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
get_8bit_displ_1:
if (ilen < remain) {
// 8 sign extended to 32
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.displ32u = (Bit8s) *iptr++;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen++;
goto modrm_done;
}
else {
return(0);
}
}
// (mod == 0x80) mod == 10b
instruction->ResolveModrm = BxResolve64Mod1or2[rm];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod10_rm32[rm]);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
get_32bit_displ_1:
if ((ilen+3) < remain) {
Bit32u imm32u;
imm32u = *iptr++;
imm32u |= (*iptr++) << 8;
imm32u |= (*iptr++) << 16;
imm32u |= (*iptr++) << 24;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.displ32u = imm32u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 4;
goto modrm_done;
}
else {
return(0);
}
}
else { // mod!=11b, rm==4, s-i-b byte follows
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
unsigned sib, base, index, scale;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
if (ilen < remain) {
sib = *iptr++;
ilen++;
}
else {
return(0);
}
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
base = (sib & 0x07) | rex_b; sib >>= 3;
index = (sib & 0x07) | rex_x; sib >>= 3;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
scale = sib;
instruction->modRMForm.modRMData |= (base<<12);
instruction->modRMForm.modRMData |= (index<<16);
instruction->modRMForm.modRMData |= (scale<<4);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
#if BX_DYNAMIC_TRANSLATION
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (instruction->modRMForm.index == 0x04) // 100b
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->DTMemRegsUsed = 0;
else
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->DTMemRegsUsed = 1<<instruction->modRMForm.index;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
#endif
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (mod == 0x00) { // mod==00b, rm==4
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve64Mod0Base[base];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0Base[base];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (base == 0x05) {
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
goto get_32bit_displ_1;
}
// mod==00b, rm==4, base!=5
#if BX_DYNAMIC_TRANSLATION
instruction->DTMemRegsUsed |= 1<<base;
#endif
goto modrm_done;
}
#if BX_DYNAMIC_TRANSLATION
// for remaining 32bit cases
instruction->DTMemRegsUsed |= 1<<base;
#endif
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (mod == 0x40) { // mod==01b, rm==4
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve64Mod1or2Base[base];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
goto get_8bit_displ_1;
}
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
// (mod == 0x80), mod==10b, rm==4
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve64Mod1or2Base[base];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
goto get_32bit_displ_1;
}
}
else {
// 32-bit addressing modes; note that mod==11b handled above
if (rm != 4) { // no s-i-b byte
#if BX_DYNAMIC_TRANSLATION
instruction->DTMemRegsUsed = 1<<rm; // except for mod=00b rm=100b
#endif
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (mod == 0x00) { // mod == 00b
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve32Mod0[rm];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0[rm];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_SEG_REG_DS);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
if (rm == 5) {
if ((ilen+3) < remain) {
Bit32u imm32u;
imm32u = *iptr++;
imm32u |= (*iptr++) << 8;
imm32u |= (*iptr++) << 16;
imm32u |= (*iptr++) << 24;
- Added an instruction cache. Size is fixed for the moment, but if you hand edit cpu/cpu.h, and change BxICacheEntries, you can try different sizes. I'll make this more flexible with configure. For now, use "--enable-icache" with no parameters. - Modified fetchdecode.cc/fetchdecode64.cc just enough so that instructions which encode a direct address now use a memory resolution function which just sticks the immediate address into rm_addr. With cached instructions we need this.
2002-09-19 23:17:20 +04:00
//RMAddr(instruction) = imm32u;
instruction->modRMForm.displ32u = imm32u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 4;
#if BX_DYNAMIC_TRANSLATION
instruction->DTMemRegsUsed = 0;
#endif
goto modrm_done;
}
else {
return(0);
}
}
// mod==00b, rm!=4, rm!=5
goto modrm_done;
}
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (mod == 0x40) { // mod == 01b
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve32Mod1or2[rm];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01_rm32[rm]);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
get_8bit_displ:
if (ilen < remain) {
// 8 sign extended to 32
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.displ32u = (Bit8s) *iptr++;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen++;
goto modrm_done;
}
else {
return(0);
}
}
// (mod == 0x80) mod == 10b
instruction->ResolveModrm = BxResolve32Mod1or2[rm];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod10_rm32[rm]);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
get_32bit_displ:
if ((ilen+3) < remain) {
Bit32u imm32u;
imm32u = *iptr++;
imm32u |= (*iptr++) << 8;
imm32u |= (*iptr++) << 16;
imm32u |= (*iptr++) << 24;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.displ32u = imm32u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 4;
goto modrm_done;
}
else {
return(0);
}
}
else { // mod!=11b, rm==4, s-i-b byte follows
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
unsigned sib, base, index, scale;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
if (ilen < remain) {
sib = *iptr++;
ilen++;
}
else {
return(0);
}
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
base = (sib & 0x07) | rex_b; sib >>= 3;
index = (sib & 0x07) | rex_x; sib >>= 3;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
scale = sib;
instruction->modRMForm.modRMData |= (base<<12);
instruction->modRMForm.modRMData |= (index<<16);
instruction->modRMForm.modRMData |= (scale<<4);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
#if BX_DYNAMIC_TRANSLATION
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (instruction->modRMForm.index == 0x04) // 100b
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->DTMemRegsUsed = 0;
else
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->DTMemRegsUsed = 1<<instruction->modRMForm.index;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
#endif
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (mod == 0x00) { // mod==00b, rm==4
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve32Mod0Base[base];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0Base[base];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (base == 0x05) {
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
goto get_32bit_displ;
}
// mod==00b, rm==4, base!=5
#if BX_DYNAMIC_TRANSLATION
instruction->DTMemRegsUsed |= 1<<base;
#endif
goto modrm_done;
}
#if BX_DYNAMIC_TRANSLATION
// for remaining 32bit cases
instruction->DTMemRegsUsed |= 1<<base;
#endif
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
if (mod == 0x40) { // mod==01b, rm==4
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
goto get_8bit_displ;
}
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
// (mod == 0x80), mod==10b, rm==4
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
#if BX_DYNAMIC_TRANSLATION
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
#endif
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
goto get_32bit_displ;
}
}
modrm_done:
/*
BX_DEBUG (("as_64=%d os_64=%d as_32=%d os_32=%d b1=%04x b2=%04x ofs=%4d rm=%d mod=%d nnn=%d",
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
instruction->as64L(),
instruction->os64L(),
instruction->as32L(),
instruction->os32L(),
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
b1,b2,offset,
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.rm,
mod,
nnn
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
));
*/
if (attr & BxGroupN) {
BxOpcodeInfo_t *OpcodeInfoPtr;
OpcodeInfoPtr = BxOpcodeInfo64[b1+offset].AnotherArray;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
// get additional attributes from group table
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
attr |= OpcodeInfoPtr[nnn].Attr;
Converted all the remaining available separate fields in bxInstruction_c to bitfields. bxInstruction_c is now 24 bytes, including 4 for the memory addr resolution function pointer, and 4 for the execution function pointer (16 + 4 + 4). Coded more accessors, to abstract access from most code.
2002-09-18 12:00:43 +04:00
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
#if BX_DYNAMIC_TRANSLATION
instruction->DTAttr = 0; // for now
#endif
}
else {
instruction->execute = BxOpcodeInfo64[b1+offset].ExecutePtr;
#if BX_DYNAMIC_TRANSLATION
instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
#endif
}
}
else {
// Opcode does not require a MODRM byte.
// Note that a 2-byte opcode (0F XX) will jump to before
// the if() above after fetching the 2nd byte, so this path is
// taken in all cases if a modrm byte is NOT required.
instruction->execute = BxOpcodeInfo64[b1+offset].ExecutePtr;
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
instruction->IxForm.opcodeReg = (b1 & 7) | rex_b;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
#if BX_DYNAMIC_TRANSLATION
instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
#endif
}
imm_mode = attr & BxImmediate;
if (imm_mode) {
switch (imm_mode) {
case BxImmediate_Ib:
if (ilen < remain) {
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.Ib = *iptr;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen++;
}
else {
return(0);
}
break;
case BxImmediate_Ib_SE: // Sign extend to OS size
if (ilen < remain) {
Bit8s temp8s;
temp8s = *iptr;
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (instruction->os32L())
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.Id = (Bit32s) temp8s;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
else
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.Iw = (Bit16s) temp8s;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen++;
}
else {
return(0);
}
break;
case BxImmediate_Iv: // same as BxImmediate_BrOff32
case BxImmediate_IvIw: // CALL_Ap
Moved more separate fields in the bxInstruction_c into bitfields with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
2002-09-18 09:36:48 +04:00
if (instruction->os32L()) {
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
if ((ilen+3) < remain) {
Bit32u imm32u;
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
ReadHostDWordFromLittleEndian(iptr, imm32u);
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.Id = imm32u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 4;
}
else {
return(0);
}
}
else {
if ((ilen+1) < remain) {
Bit16u imm16u;
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
ReadHostWordFromLittleEndian(iptr, imm16u);
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.Iw = imm16u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 2;
}
else {
return(0);
}
}
if (imm_mode != BxImmediate_IvIw)
break;
iptr++;
// Get Iw for BxImmediate_IvIw
if ((ilen+1) < remain) {
Bit16u imm16u;
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
ReadHostWordFromLittleEndian(iptr, imm16u);
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
instruction->IxIxForm.Iw2 = imm16u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 2;
}
else {
return(0);
}
break;
case BxImmediate_Iq: // MOV Rx,imm64
if ((ilen+7) < remain) {
Bit64u imm64u;
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
ReadHostQWordFromLittleEndian(iptr, imm64u);
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->IqForm.Iq = imm64u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 8;
}
else {
return(0);
}
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
break;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case BxImmediate_O:
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
// For instructions which embed the address in the opcode. Note
// there is only 64/32-bit addressing available in long-mode.
if (instruction->as64L()) {
if ((ilen+7) < remain) {
Bit64u imm64u;
ReadHostQWordFromLittleEndian(iptr, imm64u);
instruction->IqForm.Iq = imm64u;
ilen += 8;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
}
else {
return(0);
}
}
else {
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
if ((ilen+3) < remain) {
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
Bit32u imm32u;
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
ReadHostDWordFromLittleEndian(iptr, imm32u);
// Sign extend???
instruction->IqForm.Iq = imm32u;
ilen += 4;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
}
else {
return(0);
}
}
break;
64-bit bug#1: Instructions such as MOV_ALOq were always fetching 64-bit address opcode info, which was incorrect. Fixed. Got rid of BxImmediate_Oq. fetchdecode64.cc now uses BxImmediateO, like the fetch routine does. Addresses which are embedded in the opcode, have a size which depends on the current addressing size. For long-mode, this is either 64 (default) or 32 (AddrSize over-ride). BxImmediate_O now conditionally fetches based on AddrSize. 64-bit bug#2: In JMP_Jq(), when the current operand size is 16-bits, the upper dword of RIP was not being cleared. The semantics with this case are weird - one would think the top 48 bits would be cleared, but apparently only the top 32 bits are. Anyways, I fixed this. Replaced some of the messy immediate fetching (byte-by-byte) in fetchdecode64.cc with ReadHost{Q,D}WordFromLittleEndian() calls for cleanliness. Should do this for all the cases, plus the 32-bit stuff.
2002-09-27 01:32:26 +04:00
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
case BxImmediate_Iw:
case BxImmediate_IwIb:
if ((ilen+1) < remain) {
Bit16u imm16u;
imm16u = *iptr++;
imm16u |= (*iptr) << 8;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.Iw = imm16u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 2;
}
else {
return(0);
}
if (imm_mode == BxImmediate_Iw) break;
iptr++;
if (ilen < remain) {
Modified the way that the register field (low 3 bits of a few opcodes also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
2002-09-21 03:17:51 +04:00
instruction->IxIxForm.Ib2 = *iptr;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen++;
}
else {
return(0);
}
break;
case BxImmediate_BrOff8:
if (ilen < remain) {
Bit8s temp8s;
temp8s = *iptr;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.Id = temp8s;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen++;
}
else {
return(0);
}
break;
case BxImmediate_BrOff16:
if ((ilen+1) < remain) {
Bit16u imm16u;
imm16u = *iptr++;
imm16u |= (*iptr) << 8;
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
instruction->modRMForm.Id = (Bit16s) imm16u;
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
ilen += 2;
}
else {
return(0);
}
break;
default:
BX_INFO(("b1 was %x", b1));
BX_PANIC(("fetchdecode: imm_mode = %u", imm_mode));
}
}
Converted all the remaining available separate fields in bxInstruction_c to bitfields. bxInstruction_c is now 24 bytes, including 4 for the memory addr resolution function pointer, and 4 for the execution function pointer (16 + 4 + 4). Coded more accessors, to abstract access from most code.
2002-09-18 12:00:43 +04:00
instruction->setB1(b1);
instruction->setILen(ilen);
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
return(1);
}
#ifdef ignore
void
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
BX_CPU_C::BxError(bxInstruction_c *i)
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
{
// extern void dump_core();
Converted all the remaining available separate fields in bxInstruction_c to bitfields. bxInstruction_c is now 24 bytes, including 4 for the memory addr resolution function pointer, and 4 for the execution function pointer (16 + 4 + 4). Coded more accessors, to abstract access from most code.
2002-09-18 12:00:43 +04:00
BX_INFO(("BxError: instruction with op1=0x%x", i->b1()));
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
BX_INFO(("nnn was %u", i->modRMForm.nnn));
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
BX_INFO(("WARNING: Encountered an unknown instruction (signalling illegal instruction):"));
// dump_core();
BX_CPU_THIS_PTR UndefinedOpcode(i);
}
void
Updated accessing of modrm/sib addressing information to use accessors. This lets me work on compressing the size of fetch-decode structure (now called bxInstruction_c). I've reduced it down to about 76 bytes. We should be able to do much better soon. I needed the abstraction of the accessors, so I have a lot of freedom to re-arrange things without making massive future changes. Lost a few percent of performance in these mods, but my main focus was to get the abstraction.
2002-09-18 02:50:53 +04:00
BX_CPU_C::BxResolveError(bxInstruction_c *i)
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
{
Converted all the remaining available separate fields in bxInstruction_c to bitfields. bxInstruction_c is now 24 bytes, including 4 for the memory addr resolution function pointer, and 4 for the execution function pointer (16 + 4 + 4). Coded more accessors, to abstract access from most code.
2002-09-18 12:00:43 +04:00
BX_PANIC(("BxResolveError: instruction with op1=0x%x", i->b1()));
Moved 64-bit only files from cpu64 to cpu and modified the Makefiles accordingly. These files cause no conflicts at all, since they are not used in 32-bit compiles.
2002-09-13 19:53:22 +04:00
}
#endif
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