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Committed patches/patch-bochs-instrumentation from Stanislav.

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Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc,
and cpu.cc since the original patches, so I did some patch
integration by hand.  Check the placement of the
macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE()
in cpu.cc to make sure I go them right.  Also, I changed the
parameters to BX_INSTR_OPCODE() to update them to the new code.
I put some comments before each of these to help determine if
the placement is right.

These macros are only compiled in if you are gathering instrumentation
data from bochs, so they shouldn't effect others.
This commit is contained in:
Kevin Lawton 2002-09-28 00:54:05 +00:00
parent a2d70c9953
commit 13a1e55f20
17 changed files with 437 additions and 741 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
bochs/cpu/access.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: access.cc,v 1.29 2002-09-24 04:43:59 kevinlawton Exp $
// $Id: access.cc,v 1.30 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -289,7 +289,7 @@ BX_CPU_C::write_virtual_byte(unsigned s, bx_address offset, Bit8u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 1, BX_WRITE);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 1, BX_WRITE);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -354,7 +354,7 @@ BX_CPU_C::write_virtual_word(unsigned s, bx_address offset, Bit16u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 2, BX_WRITE);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 2, BX_WRITE);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -421,7 +421,7 @@ BX_CPU_C::write_virtual_dword(unsigned s, bx_address offset, Bit32u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 4, BX_WRITE);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 4, BX_WRITE);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -489,7 +489,7 @@ BX_CPU_C::read_virtual_byte(unsigned s, bx_address offset, Bit8u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 1, BX_READ);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 1, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -541,7 +541,7 @@ BX_CPU_C::read_virtual_word(unsigned s, bx_address offset, Bit16u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 2, BX_READ);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 2, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -595,7 +595,7 @@ BX_CPU_C::read_virtual_dword(unsigned s, bx_address offset, Bit32u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 4, BX_READ);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 4, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -654,7 +654,7 @@ BX_CPU_C::read_RMW_virtual_byte(unsigned s, bx_address offset, Bit8u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 1, BX_READ);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 1, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -723,7 +723,7 @@ BX_CPU_C::read_RMW_virtual_word(unsigned s, bx_address offset, Bit16u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 2, BX_READ);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 2, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -791,7 +791,7 @@ BX_CPU_C::read_RMW_virtual_dword(unsigned s, bx_address offset, Bit32u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 4, BX_READ);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 4, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -850,7 +850,7 @@ accessOK:
void
BX_CPU_C::write_RMW_virtual_byte(Bit8u val8)
{
BX_INSTR_MEM_DATA(BX_CPU_THIS_PTR address_xlation.paddress1, 1, BX_WRITE);
BX_INSTR_MEM_DATA(CPU_ID, BX_CPU_THIS_PTR address_xlation.paddress1, 1, BX_WRITE);
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
// Pages > 2 means it stores a host address for direct access.
@ -867,7 +867,7 @@ BX_CPU_C::write_RMW_virtual_byte(Bit8u val8)
void
BX_CPU_C::write_RMW_virtual_word(Bit16u val16)
{
BX_INSTR_MEM_DATA(BX_CPU_THIS_PTR address_xlation.paddress1, 2, BX_WRITE);
BX_INSTR_MEM_DATA(CPU_ID, BX_CPU_THIS_PTR address_xlation.paddress1, 2, BX_WRITE);
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
// Pages > 2 means it stores a host address for direct access.
@ -896,7 +896,7 @@ BX_CPU_C::write_RMW_virtual_word(Bit16u val16)
void
BX_CPU_C::write_RMW_virtual_dword(Bit32u val32)
{
BX_INSTR_MEM_DATA(BX_CPU_THIS_PTR address_xlation.paddress1, 4, BX_WRITE);
BX_INSTR_MEM_DATA(CPU_ID, BX_CPU_THIS_PTR address_xlation.paddress1, 4, BX_WRITE);
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
// Pages > 2 means it stores a host address for direct access.
@ -943,7 +943,7 @@ BX_CPU_C::write_virtual_qword(unsigned s, bx_address offset, Bit64u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 8, BX_WRITE);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 8, BX_WRITE);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -1011,7 +1011,7 @@ BX_CPU_C::read_virtual_qword(unsigned s, bx_address offset, Bit64u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 8, BX_READ);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 8, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
@ -1055,7 +1055,7 @@ accessOK:
void
BX_CPU_C::write_RMW_virtual_qword(Bit64u val64)
{
BX_INSTR_MEM_DATA(BX_CPU_THIS_PTR address_xlation.paddress1, 8, BX_WRITE);
BX_INSTR_MEM_DATA(CPU_ID, BX_CPU_THIS_PTR address_xlation.paddress1, 8, BX_WRITE);
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
// Pages > 2 means it stores a host address for direct access.
@ -1101,7 +1101,7 @@ BX_CPU_C::read_RMW_virtual_qword(unsigned s, bx_address offset, Bit64u *data)
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
BX_INSTR_MEM_DATA(laddr, 8, BX_READ);
BX_INSTR_MEM_DATA(CPU_ID, laddr, 8, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB

32
bochs/cpu/cpu.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.52 2002-09-24 18:33:37 kevinlawton Exp $
// $Id: cpu.cc,v 1.53 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -24,7 +24,6 @@
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define BX_INSTR_SPY 0
#define NEED_CPU_REG_SHORTCUTS 1
@ -173,18 +172,6 @@ async_events_processed:
}
#endif // #if BX_DEBUGGER
#if BX_INSTR_SPY
{
int n=0;
if ((n & 0xffffff) == 0) {
Bit32u cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
Bit32u rip = BX_CPU_THIS_PTR prev_eip;
fprintf (stdout, "instr %d, time %lld, pc %04x:%08x, fetch_ptr=%p\n", n, bx_pc_system.time_ticks (), cs, rip, fetch_ptr);
}
n++;
}
#endif
#if BX_EXTERNAL_DEBUGGER
if (regs.debug_state != debug_run) {
bx_external_debugger(this);
@ -281,6 +268,10 @@ async_events_processed:
resolveModRM = i->ResolveModrm; // Get function pointers as early
}
// An instruction will have been fetched using either the normal case,
// or the boundary fetch (across pages), by this point.
BX_INSTR_FETCH_DECODE_COMPLETED(CPU_ID, i);
execute = i->execute; // fetch as soon as possible for speculation.
if (resolveModRM) {
BX_CPU_CALL_METHOD(resolveModRM, (i));
@ -288,6 +279,9 @@ async_events_processed:
}
}
// An instruction was either fetched, or found in the iCache.
BX_INSTR_OPCODE(CPU_ID, fetchPtr, i->ilen(),
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b);
#if BX_DEBUGGER
@ -387,6 +381,7 @@ repeat_not_done:
REGISTER_IADDR(RIP + BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base);
#endif
BX_INSTR_REPEAT_ITERATION(CPU_ID);
BX_TICK1_IF_SINGLE_PROCESSOR();
#if BX_DEBUGGER == 0
@ -410,11 +405,15 @@ repeat_done:
REGISTER_IADDR(RIP + BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base);
#endif
BX_INSTR_REPEAT_ITERATION(CPU_ID);
BX_TICK1_IF_SINGLE_PROCESSOR();
}
debugger_check:
// inform instrumentation about new instruction
BX_INSTR_NEW_INSTRUCTION(CPU_ID);
#if (BX_SMP_PROCESSORS>1 && BX_DEBUGGER==0)
// The CHECK_MAX_INSTRUCTIONS macro allows cpu_loop to execute a few
// instructions and then return so that the other processors have a chance
@ -593,7 +592,7 @@ handle_async_event:
BX_CPU_THIS_PTR errorno = 0;
BX_CPU_THIS_PTR EXT = 1; /* external event */
interrupt(vector, 0, 0, 0);
BX_INSTR_HWINTERRUPT(vector,
BX_INSTR_HWINTERRUPT(CPU_ID, vector,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
// Set up environment, as would be when this main cpu loop gets
// invoked. At the end of normal instructions, we always commmit
@ -820,6 +819,9 @@ BX_CPU_C::boundaryFetch(bxInstruction_c *i)
// eliminate the extra prefetch() since we do it above, but have to
// think about repeated instructions, etc.
BX_CPU_THIS_PTR eipPageWindowSize = 0; // Fixme
BX_INSTR_OPCODE(CPU_ID, fetchBuffer, i->ilen(),
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b);
}

18
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.84 2002-09-27 09:56:40 sshwarts Exp $
// $Id: cpu.h,v 1.85 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -248,7 +248,7 @@ typedef Bit32u bx_address;
#endif
#define CPU_ID (BX_CPU_THIS_PTR which_cpu())
#ifndef CPL
#define CPL (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl)
@ -342,23 +342,15 @@ class BX_CPU_C;
// object->*(fnptr)(arg, ...);
// Since this is different from when SMF=1, encapsulate it in a macro.
# define BX_CPU_CALL_METHOD(func, args) \
do { \
BX_INSTR_OPCODE_BEGIN (BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base + BX_CPU_THIS_PTR prev_eip); \
(this->*((BxExecutePtr_t) (func))) args \
BX_INSTR_OPCODE_END (BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base + BX_CPU_THIS_PTR prev_eip); \
} while (0)
(this->*((BxExecutePtr_t) (func))) args
#else
// static member functions. With SMF, there is only one CPU by definition.
# define BX_CPU_THIS_PTR BX_CPU(0)->
# define BX_CPU_THIS BX_CPU(0)
# define BX_SMF static
# define BX_CPU_C_PREFIX
# define BX_CPU_CALL_METHOD(func, args) \
do { \
BX_INSTR_OPCODE_BEGIN (BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base + BX_CPU_THIS_PTR prev_eip); \
((BxExecutePtr_t) (func)) args; \
BX_INSTR_OPCODE_END (BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base + BX_CPU_THIS_PTR prev_eip); \
} while (0)
# define BX_CPU_CALL_METHOD(func, args) \
((BxExecutePtr_t) (func)) args
#endif
#if BX_SMP_PROCESSORS==1

38
bochs/cpu/ctrl_xfer16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer16.cc,v 1.15 2002-09-24 00:44:55 kevinlawton Exp $
// $Id: ctrl_xfer16.cc,v 1.16 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -61,7 +61,7 @@ BailBigRSP("RETnear16_Iw");
else
SP += imm16;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_RET, EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_RET, EIP);
}
void
@ -85,7 +85,7 @@ BailBigRSP("RETnear16");
}
EIP = return_IP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_RET, EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_RET, EIP);
}
void
@ -123,7 +123,7 @@ BailBigRSP("RETfar16_Iw");
SP += imm16;
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_RET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -152,7 +152,7 @@ BailBigRSP("RETfar16");
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_RET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -184,7 +184,7 @@ BailBigRSP("CALL_Aw");
push_16(IP);
EIP = new_EIP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL, EIP);
}
void
@ -216,7 +216,7 @@ BailBigRSP("CALL16_Ap");
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_CALL,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -252,7 +252,7 @@ BailBigRSP("CALL_Ew");
push_16(IP);
EIP = op1_16;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL, EIP);
}
void
@ -287,7 +287,7 @@ BailBigRSP("CALL_16_Ep");
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_CALL,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -313,7 +313,7 @@ BailBigRSP("JMP_Jw");
#endif
EIP = new_EIP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP, new_EIP);
}
void
@ -362,12 +362,12 @@ BailBigRSP("JCC_Jw");
}
#endif
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -391,12 +391,12 @@ BailBigRSP("JZ_Jw");
}
#endif
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -420,12 +420,12 @@ BailBigRSP("JNZ_Jw");
}
#endif
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -461,7 +461,7 @@ BailBigRSP("JMP_Ew");
EIP = new_EIP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP, new_EIP);
}
/* Far indirect jump */
@ -494,7 +494,7 @@ BailBigRSP("JMP16_Ep");
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_JMP,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -534,6 +534,6 @@ BailBigRSP("IRET16");
write_flags(flags, /* change IOPL? */ 1, /* change IF? */ 1);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_IRET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_IRET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}

40
bochs/cpu/ctrl_xfer32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer32.cc,v 1.19 2002-09-27 07:01:02 kevinlawton Exp $
// $Id: ctrl_xfer32.cc,v 1.20 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -92,7 +92,7 @@ BailBigRSP("RETnear32_Iw");
SP += imm16;
}
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_RET, EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_RET, EIP);
}
void
@ -138,7 +138,7 @@ BailBigRSP("RETnear32");
EIP = return_EIP;
}
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_RET, EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_RET, EIP);
}
void
@ -175,7 +175,7 @@ BailBigRSP("RETfar32_Iw");
SP += imm16;
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_RET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -205,7 +205,7 @@ BailBigRSP("RETfar32");
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) ecs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_RET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -239,7 +239,7 @@ BailBigRSP("CALL_Ad");
push_32(EIP);
EIP = new_EIP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL, EIP);
}
void
@ -268,7 +268,7 @@ BailBigRSP("CALL32_Ap");
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_CALL,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -309,7 +309,7 @@ BailBigRSP("CALL_Ed");
push_32(EIP);
EIP = op1_32;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL, EIP);
}
void
@ -346,7 +346,7 @@ BailBigRSP("CALL32_Ep");
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_CALL,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -371,7 +371,7 @@ BailBigRSP("JMP_Jd");
#endif
EIP = new_EIP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP, new_EIP);
}
void
@ -420,12 +420,12 @@ BailBigRSP("JCC_Jd");
}
#endif
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -448,12 +448,12 @@ BailBigRSP("JZ_Jd");
}
#endif
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -476,12 +476,12 @@ BailBigRSP("JNZ_Jd");
}
#endif
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -514,7 +514,7 @@ BailBigRSP("JMP_Ap");
EIP = disp32;
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_JMP,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -552,7 +552,7 @@ BailBigRSP("JMP_Ed");
EIP = new_EIP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_EIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP, new_EIP);
}
/* Far indirect jump */
@ -585,7 +585,7 @@ BailBigRSP("JMP32_Ep");
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_JMP,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@ -629,6 +629,6 @@ BailBigRSP("IRET32");
write_eflags(eflags, /* change IOPL? */ 1, /* change IF? */ 1, 0, 1);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_IRET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_IRET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}

67
bochs/cpu/ctrl_xfer64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer64.cc,v 1.14 2002-09-27 07:01:02 kevinlawton Exp $
// $Id: ctrl_xfer64.cc,v 1.15 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -69,7 +69,7 @@ BX_CPU_C::RETnear64_Iw(bxInstruction_c *i)
RIP = return_RIP;
RSP += 8 + imm16; /* ??? should it be 2*imm16 ? */
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_RET, BX_CPU_THIS_PTR rip);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_RET, BX_CPU_THIS_PTR rip);
}
void
@ -97,7 +97,7 @@ BX_CPU_C::RETnear64(bxInstruction_c *i)
RIP = return_RIP;
RSP += 8;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_RET, BX_CPU_THIS_PTR rip);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_RET, BX_CPU_THIS_PTR rip);
}
void
@ -129,7 +129,7 @@ BX_CPU_C::RETfar64_Iw(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) rcs_raw);
RSP += imm16;
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_RET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
@ -158,7 +158,7 @@ BX_CPU_C::RETfar64(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) rcs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_RET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
@ -184,7 +184,7 @@ BX_CPU_C::CALL_Aq(bxInstruction_c *i)
push_64(BX_CPU_THIS_PTR rip);
RIP = new_RIP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, BX_CPU_THIS_PTR rip);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL, BX_CPU_THIS_PTR rip);
}
void
@ -212,7 +212,7 @@ BX_CPU_C::CALL64_Ap(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_CALL,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
@ -240,7 +240,7 @@ BX_CPU_C::CALL_Eq(bxInstruction_c *i)
push_64(BX_CPU_THIS_PTR rip);
RIP = op1_64;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, BX_CPU_THIS_PTR rip);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL, BX_CPU_THIS_PTR rip);
}
void
@ -276,7 +276,7 @@ BX_CPU_C::CALL64_Ep(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_CALL,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
@ -284,14 +284,12 @@ done:
void
BX_CPU_C::JMP_Jq(bxInstruction_c *i)
{
Bit64u new_RIP;
invalidate_prefetch_q();
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_RIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP, RIP);
}
void
@ -329,12 +327,12 @@ BX_CPU_C::JCC_Jq(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -367,7 +365,7 @@ BX_CPU_C::JMP64_Ap(bxInstruction_c *i)
RIP = disp64;
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_JMP,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
@ -378,7 +376,6 @@ done:
void
BX_CPU_C::JMP_Eq(bxInstruction_c *i)
{
Bit64u new_RIP;
Bit64u op1_64;
invalidate_prefetch_q();
@ -392,7 +389,7 @@ BX_CPU_C::JMP_Eq(bxInstruction_c *i)
RIP = op1_64;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_RIP);
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP, RIP);
}
/* Far indirect jump */
@ -421,7 +418,7 @@ BX_CPU_C::JMP64_Ep(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_JMP,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
}
@ -446,7 +443,7 @@ BX_CPU_C::IRET64(bxInstruction_c *i)
done:
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_IRET,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_IRET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
@ -459,12 +456,12 @@ BX_CPU_C::JCXZ64_Jb(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(new_RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -473,12 +470,12 @@ BX_CPU_C::JCXZ64_Jb(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -495,12 +492,12 @@ BX_CPU_C::LOOPNE64_Jb(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -509,12 +506,12 @@ BX_CPU_C::LOOPNE64_Jb(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -529,12 +526,12 @@ BX_CPU_C::LOOPE64_Jb(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -543,12 +540,12 @@ BX_CPU_C::LOOPE64_Jb(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -563,12 +560,12 @@ BX_CPU_C::LOOP64_Jb(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -577,12 +574,12 @@ BX_CPU_C::LOOP64_Jb(bxInstruction_c *i)
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}

34
bochs/cpu/ctrl_xfer8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer8.cc,v 1.11 2002-09-24 00:44:55 kevinlawton Exp $
// $Id: ctrl_xfer8.cc,v 1.12 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -46,12 +46,12 @@ BailBigRSP("JCXZ_Jb");
if (i->as64L()) {
if ( RCX == 0 ) {
RIP += (Bit32s) i->Id();
BX_INSTR_CNEAR_BRANCH_TAKEN(new_RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -78,12 +78,12 @@ BailBigRSP("JCXZ_Jb");
}
#endif
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -100,12 +100,12 @@ BailBigRSP("loopne_jb");
if ( ((--RCX)!=0) && (get_ZF()==0) ) {
RIP += (Bit32s) i->Id();
BX_INSTR_CNEAR_BRANCH_TAKEN(RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -132,12 +132,12 @@ BailBigRSP("loopne_jb");
}
}
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
@ -157,12 +157,12 @@ BailBigRSP("loope_jb");
if ( ((--RCX)!=0) && (get_ZF()) ) {
RIP += (Bit32s) i->Id();
BX_INSTR_CNEAR_BRANCH_TAKEN(RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -189,12 +189,12 @@ BailBigRSP("loope_jb");
}
}
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
@ -214,12 +214,12 @@ BailBigRSP("loop_jb");
if ( ((--RCX)!=0) ) {
RIP += (Bit32s) i->Id();
BX_INSTR_CNEAR_BRANCH_TAKEN(RIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif
}
@ -246,12 +246,12 @@ BailBigRSP("loop_jb");
}
}
EIP = new_EIP;
BX_INSTR_CNEAR_BRANCH_TAKEN(new_EIP);
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID, );
}
#endif

6
bochs/cpu/exception.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: exception.cc,v 1.21 2002-09-27 03:33:13 ptrumpet Exp $
// $Id: exception.cc,v 1.22 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -71,7 +71,7 @@ BX_CPU_C::interrupt(Bit8u vector, Boolean is_INT, Boolean is_error_code,
//BX_DEBUG(( "::interrupt(%u)", vector ));
BX_INSTR_INTERRUPT(vector);
BX_INSTR_INTERRUPT(CPU_ID, vector);
invalidate_prefetch_q();
// Discard any traps and inhibits for new context; traps will
@ -823,7 +823,7 @@ BX_CPU_C::exception(unsigned vector, Bit16u error_code, Boolean is_INT)
#endif
BX_INSTR_EXCEPTION(vector);
BX_INSTR_EXCEPTION(CPU_ID, vector);
invalidate_prefetch_q();
UNUSED(is_INT);

20
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.22 2002-09-27 09:56:40 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.23 2002-09-28 00:54:04 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1498,6 +1498,7 @@ another_byte:
if (attr & BxPrefix) {
switch (b1) {
case 0x66: // OpSize
BX_INSTR_PREFIX_OS(CPU_ID);
os_32 = !is_32;
instruction->setOs32B(os_32);
if (ilen < remain) {
@ -1507,6 +1508,7 @@ another_byte:
return(0);
case 0x67: // AddrSize
BX_INSTR_PREFIX_AS(CPU_ID);
instruction->setAs32B(!is_32);
if (ilen < remain) {
ilen++;
@ -1515,7 +1517,16 @@ another_byte:
return(0);
case 0xf2: // REPNE/REPNZ
BX_INSTR_PREFIX_REPNE(CPU_ID);
instruction->setRepUsed(b1 & 3);
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
case 0xf3: // REP/REPE/REPZ
BX_INSTR_PREFIX_REP(CPU_ID);
instruction->setRepUsed(b1 & 3);
if (ilen < remain) {
ilen++;
@ -1524,6 +1535,7 @@ another_byte:
return(0);
case 0x2e: // CS:
BX_INSTR_PREFIX_CS(CPU_ID);
instruction->setSeg(BX_SEG_REG_CS);
if (ilen < remain) {
ilen++;
@ -1531,6 +1543,7 @@ another_byte:
}
return(0);
case 0x26: // ES:
BX_INSTR_PREFIX_ES(CPU_ID);
instruction->setSeg(BX_SEG_REG_ES);
if (ilen < remain) {
ilen++;
@ -1538,6 +1551,7 @@ another_byte:
}
return(0);
case 0x36: // SS:
BX_INSTR_PREFIX_SS(CPU_ID);
instruction->setSeg(BX_SEG_REG_SS);
if (ilen < remain) {
ilen++;
@ -1545,6 +1559,7 @@ another_byte:
}
return(0);
case 0x3e: // DS:
BX_INSTR_PREFIX_DS(CPU_ID);
instruction->setSeg(BX_SEG_REG_DS);
if (ilen < remain) {
ilen++;
@ -1552,6 +1567,7 @@ another_byte:
}
return(0);
case 0x64: // FS:
BX_INSTR_PREFIX_FS(CPU_ID);
instruction->setSeg(BX_SEG_REG_FS);
if (ilen < remain) {
ilen++;
@ -1559,6 +1575,7 @@ another_byte:
}
return(0);
case 0x65: // GS:
BX_INSTR_PREFIX_GS(CPU_ID);
instruction->setSeg(BX_SEG_REG_GS);
if (ilen < remain) {
ilen++;
@ -1567,6 +1584,7 @@ another_byte:
return(0);
case 0xf0: // LOCK:
BX_INSTR_PREFIX_LOCK(CPU_ID);
if (ilen < remain) {
ilen++;
goto fetch_b1;

21
bochs/cpu/fetchdecode64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.17 2002-09-27 09:56:40 sshwarts Exp $
// $Id: fetchdecode64.cc,v 1.18 2002-09-28 00:54:05 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2104,6 +2104,7 @@ another_byte:
if (attr & BxPrefix) {
switch (b1) {
case 0x66: // OpSize
BX_INSTR_PREFIX_OS(CPU_ID);
if (!instruction->os64L()) {
instruction->setOs32B(0);
offset = 0;
@ -2115,6 +2116,7 @@ another_byte:
return(0);
case 0x67: // AddrSize
BX_INSTR_PREFIX_AS(CPU_ID);
instruction->setAs64B(0);
if (ilen < remain) {
ilen++;
@ -2138,6 +2140,7 @@ another_byte:
case 0x4D:
case 0x4E:
case 0x4F:
BX_INSTR_PREFIX_EXTEND8B(CPU_ID);
instruction->assertExtend8bit();
//BX_DEBUG (("REX byte = %02x",b1));
@ -2166,7 +2169,16 @@ another_byte:
return(0);
case 0xf2: // REPNE/REPNZ
BX_INSTR_PREFIX_REPNE(CPU_ID);
instruction->setRepUsed(b1 & 3);
if (ilen < remain) {
ilen++;
goto fetch_b1;
}
return(0);
case 0xf3: // REP/REPE/REPZ
BX_INSTR_PREFIX_REP(CPU_ID);
instruction->setRepUsed(b1 & 3);
if (ilen < remain) {
ilen++;
@ -2175,6 +2187,7 @@ another_byte:
return(0);
case 0x2e: // CS:
BX_INSTR_PREFIX_CS(CPU_ID);
instruction->setSeg(BX_SEG_REG_CS);
if (ilen < remain) {
ilen++;
@ -2182,6 +2195,7 @@ another_byte:
}
return(0);
case 0x26: // ES:
BX_INSTR_PREFIX_ES(CPU_ID);
instruction->setSeg(BX_SEG_REG_ES);
if (ilen < remain) {
ilen++;
@ -2189,6 +2203,7 @@ another_byte:
}
return(0);
case 0x36: // SS:
BX_INSTR_PREFIX_SS(CPU_ID);
instruction->setSeg(BX_SEG_REG_SS);
if (ilen < remain) {
ilen++;
@ -2196,6 +2211,7 @@ another_byte:
}
return(0);
case 0x3e: // DS:
BX_INSTR_PREFIX_DS(CPU_ID);
instruction->setSeg(BX_SEG_REG_DS);
if (ilen < remain) {
ilen++;
@ -2203,6 +2219,7 @@ another_byte:
}
return(0);
case 0x64: // FS:
BX_INSTR_PREFIX_FS(CPU_ID);
instruction->setSeg(BX_SEG_REG_FS);
if (ilen < remain) {
ilen++;
@ -2210,6 +2227,7 @@ another_byte:
}
return(0);
case 0x65: // GS:
BX_INSTR_PREFIX_GS(CPU_ID);
instruction->setSeg(BX_SEG_REG_GS);
if (ilen < remain) {
ilen++;
@ -2217,6 +2235,7 @@ another_byte:
}
return(0);
case 0xf0: // LOCK:
BX_INSTR_PREFIX_LOCK(CPU_ID);
if (ilen < remain) {
ilen++;
goto fetch_b1;

10
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.32 2002-09-22 18:22:24 kevinlawton Exp $
// $Id: init.cc,v 1.33 2002-09-28 00:54:05 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -166,7 +166,7 @@ cpu_param_handler (bx_param_c *param, int set, Bit32s val)
void BX_CPU_C::init(BX_MEM_C *addrspace)
{
BX_DEBUG(( "Init $Id: init.cc,v 1.32 2002-09-22 18:22:24 kevinlawton Exp $"));
BX_DEBUG(( "Init $Id: init.cc,v 1.33 2002-09-28 00:54:05 kevinlawton Exp $"));
// BX_CPU_C constructor
BX_CPU_THIS_PTR set_INTR (0);
#if BX_SUPPORT_APIC
@ -325,7 +325,7 @@ void BX_CPU_C::init(BX_MEM_C *addrspace)
mem = addrspace;
sprintf (name, "CPU %p", this);
BX_INSTR_INIT();
BX_INSTR_INIT(CPU_ID);
#if BX_WITH_WX
// Register some of the CPUs variables as shadow parameters so that
@ -463,7 +463,7 @@ void BX_CPU_C::init(BX_MEM_C *addrspace)
BX_CPU_C::~BX_CPU_C(void)
{
BX_INSTR_SHUTDOWN();
BX_INSTR_SHUTDOWN(CPU_ID);
BX_DEBUG(( "Exit."));
}
@ -870,6 +870,8 @@ BX_CPU_C::reset(unsigned source)
#else
BX_CPU_THIS_PTR async_event = 0;
#endif
BX_INSTR_RESET(CPU_ID);
}

44
bochs/cpu/paging.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: paging.cc,v 1.30 2002-09-20 03:52:58 kevinlawton Exp $
// $Id: paging.cc,v 1.31 2002-09-28 00:54:05 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -546,7 +546,7 @@ BX_CPU_C::INVLPG(bxInstruction_c* i)
InstrTLB_Increment(tlbEntryInvlpg);
#endif // BX_USE_TLB
BX_INSTR_TLB_CNTRL(BX_INSTR_INVLPG, 0);
BX_INSTR_TLB_CNTRL(CPU_ID, BX_INSTR_INVLPG, 0);
#else
// not supported on < 486
@ -1090,12 +1090,12 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
BX_CPU_THIS_PTR address_xlation.pages = 1;
if (rw == BX_READ) {
BX_INSTR_LIN_READ(laddr, BX_CPU_THIS_PTR address_xlation.paddress1, length);
BX_INSTR_LIN_READ(CPU_ID, laddr, BX_CPU_THIS_PTR address_xlation.paddress1, length);
BX_CPU_THIS_PTR mem->readPhysicalPage(this,
BX_CPU_THIS_PTR address_xlation.paddress1, length, data);
}
else {
BX_INSTR_LIN_WRITE(laddr, BX_CPU_THIS_PTR address_xlation.paddress1, length);
BX_INSTR_LIN_WRITE(CPU_ID, laddr, BX_CPU_THIS_PTR address_xlation.paddress1, length);
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
BX_CPU_THIS_PTR address_xlation.paddress1, length, data);
}
@ -1115,12 +1115,12 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
#ifdef BX_LITTLE_ENDIAN
if (rw == BX_READ) {
BX_INSTR_LIN_READ(laddr,
BX_INSTR_LIN_READ(CPU_ID, laddr,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1);
BX_CPU_THIS_PTR mem->readPhysicalPage(this, BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1, data);
BX_INSTR_LIN_READ(laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_INSTR_LIN_READ(CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2);
BX_CPU_THIS_PTR mem->readPhysicalPage(this, BX_CPU_THIS_PTR address_xlation.paddress2,
@ -1128,12 +1128,12 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
}
else {
BX_INSTR_LIN_WRITE(laddr,
BX_INSTR_LIN_WRITE(CPU_ID, laddr,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1);
BX_CPU_THIS_PTR mem->writePhysicalPage(this, BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1, data);
BX_INSTR_LIN_WRITE(laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_INSTR_LIN_WRITE(CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2);
BX_CPU_THIS_PTR mem->writePhysicalPage(this, BX_CPU_THIS_PTR address_xlation.paddress2,
@ -1143,26 +1143,26 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
#else // BX_BIG_ENDIAN
if (rw == BX_READ) {
BX_INSTR_LIN_READ(laddr,
BX_INSTR_LIN_READ(CPU_ID, laddr,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1);
BX_CPU_THIS_PTR mem->readPhysicalPage(this, BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1,
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
BX_INSTR_LIN_READ(laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_INSTR_LIN_READ(CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2);
BX_CPU_THIS_PTR mem->readPhysicalPage(this, BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2, data);
}
else {
BX_INSTR_LIN_WRITE(laddr,
BX_INSTR_LIN_WRITE(CPU_ID, laddr,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1);
BX_CPU_THIS_PTR mem->writePhysicalPage(this, BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1,
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
BX_INSTR_LIN_WRITE(laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_INSTR_LIN_WRITE(CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2);
BX_CPU_THIS_PTR mem->writePhysicalPage(this, BX_CPU_THIS_PTR address_xlation.paddress2,
@ -1185,7 +1185,7 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
Bit32u lpf, tlbIndex;
#endif
BX_INSTR_LIN_READ(laddr, laddr, length);
BX_INSTR_LIN_READ(CPU_ID, laddr, laddr, length);
#if BX_SupportGuest2HostTLB
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = laddr & 0xfffff000;
@ -1227,7 +1227,7 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
Bit32u lpf, tlbIndex;
#endif
BX_INSTR_LIN_WRITE(laddr, laddr, length);
BX_INSTR_LIN_WRITE(CPU_ID, laddr, laddr, length);
#if BX_SupportGuest2HostTLB
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = laddr & 0xfffff000;
@ -1267,13 +1267,13 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
#ifdef BX_LITTLE_ENDIAN
if (rw == BX_READ) {
BX_INSTR_LIN_READ(laddr,
BX_INSTR_LIN_READ(CPU_ID, laddr,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1);
BX_CPU_THIS_PTR mem->readPhysicalPage(this,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1, data);
BX_INSTR_LIN_READ(laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_INSTR_LIN_READ(CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2);
BX_CPU_THIS_PTR mem->readPhysicalPage(this,
@ -1282,13 +1282,13 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
}
else {
BX_INSTR_LIN_WRITE(laddr,
BX_INSTR_LIN_WRITE(CPU_ID, laddr,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1);
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1, data);
BX_INSTR_LIN_WRITE(laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_INSTR_LIN_WRITE(CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2);
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
@ -1299,14 +1299,14 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
#else // BX_BIG_ENDIAN
if (rw == BX_READ) {
BX_INSTR_LIN_READ(laddr,
BX_INSTR_LIN_READ(CPU_ID, laddr,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1);
BX_CPU_THIS_PTR mem->readPhysicalPage(this,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1,
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
BX_INSTR_LIN_READ(laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_INSTR_LIN_READ(CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2);
BX_CPU_THIS_PTR mem->readPhysicalPage(this,
@ -1314,14 +1314,14 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
BX_CPU_THIS_PTR address_xlation.len2, data);
}
else {
BX_INSTR_LIN_WRITE(laddr,
BX_INSTR_LIN_WRITE(CPU_ID, laddr,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1);
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
BX_CPU_THIS_PTR address_xlation.paddress1,
BX_CPU_THIS_PTR address_xlation.len1,
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
BX_INSTR_LIN_WRITE(laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_INSTR_LIN_WRITE(CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
BX_CPU_THIS_PTR address_xlation.paddress2,
BX_CPU_THIS_PTR address_xlation.len2);
BX_CPU_THIS_PTR mem->writePhysicalPage(this,

10
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.51 2002-09-25 14:09:08 ptrumpet Exp $
// $Id: proc_ctrl.cc,v 1.52 2002-09-28 00:54:05 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -133,7 +133,7 @@ BX_CPU_C::INVD(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0, 0);
}
}
BX_INSTR_CACHE_CNTRL(BX_INSTR_INVD);
BX_INSTR_CACHE_CNTRL(CPU_ID, BX_INSTR_INVD);
#else
UndefinedOpcode(i);
#endif
@ -153,7 +153,7 @@ BX_CPU_C::WBINVD(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0, 0);
}
}
BX_INSTR_CACHE_CNTRL(BX_INSTR_WBINVD);
BX_INSTR_CACHE_CNTRL(CPU_ID, BX_INSTR_WBINVD);
#else
UndefinedOpcode(i);
#endif
@ -712,7 +712,7 @@ BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
BX_INFO(("MOV_CdRd:CR3 = %08x", (unsigned) val_32));
// Reserved bits take on value of MOV instruction
CR3_change(val_32);
BX_INSTR_TLB_CNTRL(BX_INSTR_MOV_CR3, val_32);
BX_INSTR_TLB_CNTRL(CPU_ID, BX_INSTR_MOV_CR3, val_32);
// Reload of CR3 always serializes.
// invalidate_prefetch_q(); // Already done.
break;
@ -865,7 +865,7 @@ BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
BX_INFO(("MOV_CqRq:CR3 = %08x", (unsigned) val_64));
// Reserved bits take on value of MOV instruction
CR3_change(val_64);
BX_INSTR_TLB_CNTRL(BX_INSTR_MOV_CR3, val_64);
BX_INSTR_TLB_CNTRL(CPU_ID, BX_INSTR_MOV_CR3, val_64);
break;
case 4: // CR4
#if BX_CPU_LEVEL == 3

10
bochs/cpu/soft_int.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: soft_int.cc,v 1.11 2002-09-20 03:52:58 kevinlawton Exp $
// $Id: soft_int.cc,v 1.12 2002-09-28 00:54:05 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -97,7 +97,7 @@ BX_CPU_C::INT1(bxInstruction_c *i)
#endif
interrupt(1, 1, 0, 0);
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_INT,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_INT,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
EIP);
}
@ -113,7 +113,7 @@ BX_CPU_C::INT3(bxInstruction_c *i)
//BX_PANIC(("INT3: bailing"));
interrupt(3, 1, 0, 0);
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_INT,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_INT,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
EIP);
}
@ -142,7 +142,7 @@ if ( (imm8 == 0x21) && (AH == 0x4c) ) {
#endif
interrupt(imm8, 1, 0, 0);
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_INT,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_INT,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
EIP);
}
@ -161,7 +161,7 @@ BX_CPU_C::INTO(bxInstruction_c *i)
if (get_OF()) {
interrupt(4, 1, 0, 0);
BX_INSTR_FAR_BRANCH(BX_INSTR_IS_INT,
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_INT,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
EIP);
}

4
bochs/cpu/tasking.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: tasking.cc,v 1.14 2002-09-13 16:23:02 kevinlawton Exp $
// $Id: tasking.cc,v 1.15 2002-09-28 00:54:05 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -482,7 +482,7 @@ if ( source==BX_TASK_FROM_CALL_OR_INT ) {
if ( (tss_descriptor->type >= 9) && BX_CPU_THIS_PTR cr0.pg) {
CR3_change(newCR3); // Tell paging unit about new cr3 value
BX_DEBUG (("task_switch changing CR3 to 0x%08x", newCR3));
BX_INSTR_TLB_CNTRL(BX_INSTR_TASKSWITCH, newCR3);
BX_INSTR_TLB_CNTRL(CPU_ID, BX_INSTR_TASKSWITCH, newCR3);
}
BX_CPU_THIS_PTR prev_eip = EIP = newEIP;

391
bochs/instrument/stubs/instrument.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.cc,v 1.4 2001-10-03 13:10:38 bdenney Exp $
// $Id: instrument.cc,v 1.5 2002-09-28 00:54:05 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -28,361 +28,56 @@
#include "bochs.h"
void bx_instr_init(unsigned cpu) {}
void bx_instr_shutdown(unsigned cpu) {}
void bx_instr_reset(unsigned cpu) {}
void bx_instr_new_instruction(unsigned cpu) {}
#if 0
// possible types passed to BX_INSTR_TLB_CNTRL()
#define BX_INSTR_MOV_CR3 10
#define BX_INSTR_INVLPG 11
#define BX_INSTR_TASKSWITCH 12
void bx_instr_debug_promt() {}
void bx_instr_start() {}
void bx_instr_stop() {}
void bx_instr_print() {}
// possible types passed to BX_INSTR_CACHE_CNTRL()
#define BX_INSTR_INVD 20
#define BX_INSTR_WBINVD 21
#endif
void bx_instr_cnear_branch_taken(unsigned cpu, bx_address new_eip) {}
void bx_instr_cnear_branch_not_taken(unsigned cpu) {}
void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip) {}
void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip) {}
void bx_instr_opcode(unsigned cpu, Bit8u *opcode, unsigned len, Boolean is32) {}
void bx_instr_fetch_decode_completed(unsigned cpu, bxInstruction *i) {}
// called from the CPU core
void
bx_instr_cnear_branch_taken(Bit32u new_eip)
{
UNUSED(new_eip);
}
void bx_instr_prefix_as(unsigned cpu) {}
void bx_instr_prefix_os(unsigned cpu) {}
void bx_instr_prefix_rep(unsigned cpu) {}
void bx_instr_prefix_repne(unsigned cpu) {}
void bx_instr_prefix_lock(unsigned cpu) {}
void bx_instr_prefix_cs(unsigned cpu) {}
void bx_instr_prefix_ss(unsigned cpu) {}
void bx_instr_prefix_ds(unsigned cpu) {}
void bx_instr_prefix_es(unsigned cpu) {}
void bx_instr_prefix_fs(unsigned cpu) {}
void bx_instr_prefix_gs(unsigned cpu) {}
void bx_instr_prefix_extend8b(unsigned cpu) {}
void
bx_instr_cnear_branch_not_taken(void)
{
}
void bx_instr_interrupt(unsigned cpu, unsigned vector) {}
void bx_instr_exception(unsigned cpu, unsigned vector) {}
void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip) {}
void
bx_instr_ucnear_branch(unsigned what, Bit32u new_eip)
{
UNUSED(what);
UNUSED(new_eip);
}
void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, Bit32u newval) {}
void bx_instr_cache_cntrl(unsigned cpu, unsigned what) {}
void
bx_instr_far_branch(unsigned what, Bit32u new_cs, Bit32u new_eip)
{
UNUSED(what);
UNUSED(new_eip);
UNUSED(new_cs);
}
void bx_instr_repeat_iteration(unsigned cpu) {}
void
bx_instr_opcode_byte1(Bit8u opcode)
{
UNUSED(opcode);
}
void bx_instr_inp(Bit16u addr, unsigned len) {}
void bx_instr_outp(Bit16u addr, unsigned len) {}
void bx_instr_inp2(Bit16u addr, unsigned len, unsigned val) {}
void bx_instr_outp2(Bit16u addr, unsigned len, unsigned val) {}
void
bx_instr_opcode_byte2(Bit8u opcode)
{
UNUSED(opcode);
}
void bx_instr_mem_code(unsigned cpu, bx_address linear, unsigned size) {}
void bx_instr_mem_data(unsigned cpu, bx_address linear, unsigned size, unsigned rw) {}
void
bx_instr_opcode_g1ebib(unsigned nnn)
{
UNUSED(nnn);
}
void bx_instr_lin_read(unsigned cpu, bx_address lin, bx_address phy, unsigned len) {}
void bx_instr_lin_write(unsigned cpu, bx_address lin, bx_address phy, unsigned len) {}
void
bx_instr_opcode_g1eviv(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g1evib(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g2ebib(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g2evib(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g2eb1(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g2ev1(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g2ebcl(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g2evcl(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g3eb(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g3ev(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g4(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g5(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g6(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g7(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_opcode_g8evib(unsigned nnn)
{
UNUSED(nnn);
}
void
bx_instr_mem_code(Bit32u linear, unsigned size)
{
UNUSED(linear);
UNUSED(size);
}
void
bx_instr_mem_data(Bit32u linear, unsigned size, unsigned rw)
{
UNUSED(linear);
UNUSED(size);
UNUSED(rw);
}
void
bx_instr_opcode_begin(Bit32u linear)
{
UNUSED(linear);
}
void
bx_instr_opcode_end(Bit32u linear)
{
UNUSED(linear);
}
void
bx_instr_exception(unsigned vector)
{
UNUSED(vector);
}
void
bx_instr_tlb_cntrl(unsigned what, Bit32u newval)
{
UNUSED(what);
UNUSED(newval);
}
void
bx_instr_cache_cntrl(unsigned what)
{
UNUSED(what);
}
void
bx_instr_hwinterrupt(unsigned vector, Bit32u cs, Bit32u eip)
{
UNUSED(vector);
UNUSED(cs);
UNUSED(eip);
}
void
bx_instr_init(void)
{
}
void
bx_instr_shutdown(void)
{
}
void
bx_instr_opcode_repeating(void)
{
}
// called from the debug prompt
void
bx_instr_start(void)
{
}
void
bx_instr_stop(void)
{
}
void
bx_instr_reset(void)
{
}
void
bx_instr_print(void)
{
}
void
bx_instr_prefix_as(void)
{
}
void
bx_instr_prefix_os(void)
{
}
void
bx_instr_prefix_rep(void)
{
}
void
bx_instr_prefix_repne(void)
{
}
void
bx_instr_prefix_lock(void)
{
}
void
bx_instr_prefix_cs(void)
{
}
void
bx_instr_prefix_ss(void)
{
}
void
bx_instr_prefix_ds(void)
{
}
void
bx_instr_prefix_es(void)
{
}
void
bx_instr_prefix_fs(void)
{
}
void
bx_instr_prefix_gs(void)
{
}
void
bx_instr_modrm32(unsigned modrm)
{
UNUSED(modrm);
}
void
bx_instr_sib32(unsigned sib)
{
UNUSED(sib);
}
void
bx_instr_modrm16(unsigned modrm)
{
UNUSED(modrm);
}
void
bx_instr_iret(void)
{
}
void
bx_instr_debug_prompt(void)
{
}
void
bx_instr_fetch_byte(Bit8u val8)
{
}
void
bx_instr_fetch_word(Bit16u val16)
{
}
void
bx_instr_fetch_dword(Bit32u val32)
{
}
void
bx_instr_phy_write(Bit32u addr, unsigned len)
{
}
void
bx_instr_phy_read(Bit32u addr, unsigned len)
{
}
void
bx_instr_interrupt(unsigned vector)
{
}
void
bx_instr_inp(Bit16u addr, unsigned len)
{
}
void
bx_instr_outp(Bit16u addr, unsigned len)
{
}
void
bx_instr_inp2(Bit16u addr, unsigned len, unsigned val)
{
}
void
bx_instr_outp2(Bit16u addr, unsigned len, unsigned val)
{
}
void bx_instr_lin_read(Bit32u lin, Bit32u phy, unsigned len)
{
}
void bx_instr_lin_write(Bit32u lin, Bit32u phy, unsigned len)
{
}
void bx_instr_phy_write(bx_address addr, unsigned len) {}
void bx_instr_phy_read(bx_address addr, unsigned len) {}

399
bochs/instrument/stubs/instrument.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.h,v 1.5 2001-10-03 13:10:38 bdenney Exp $
// $Id: instrument.h,v 1.6 2002-09-28 00:54:05 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,19 +25,19 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// possible types passed to BX_INSTR_TLB_CNTRL()
#define BX_INSTR_MOV_CR3 10
#define BX_INSTR_INVLPG 11
#define BX_INSTR_TASKSWITCH 12
#define BX_INSTR_MOV_CR3 10
#define BX_INSTR_INVLPG 11
#define BX_INSTR_TASKSWITCH 12
// possible types passed to BX_INSTR_CACHE_CNTRL()
#define BX_INSTR_INVD 20
#define BX_INSTR_WBINVD 21
#if BX_INSTRUMENTATION
#define BX_INSTR_INVD 20
#define BX_INSTR_WBINVD 21
#define BX_INSTR_SFENCE 22
#define BX_INSTR_PREFETCH_T0 23
#define BX_INSTR_PREFETCH_T1 24
#define BX_INSTR_PREFETCH_T2 25
#define BX_INSTR_PREFETCH_NTA 26
#define BX_INSTR_IS_CALL 10
#define BX_INSTR_IS_RET 11
@ -46,224 +46,195 @@
#define BX_INSTR_IS_INT 14
#if BX_INSTRUMENTATION
// called from the CPU core
void bx_instr_cnear_branch_taken(Bit32u new_eip);
void bx_instr_cnear_branch_not_taken(void);
void bx_instr_ucnear_branch(unsigned what, Bit32u new_eip);
void bx_instr_far_branch(unsigned what, Bit32u new_cs, Bit32u new_eip);
void bx_instr_opcode_byte1(Bit8u);
void bx_instr_opcode_byte2(Bit8u);
void bx_instr_opcode_g1ebib(unsigned nnn);
void bx_instr_opcode_g1eviv(unsigned nnn);
void bx_instr_opcode_g1evib(unsigned nnn);
void bx_instr_opcode_g2ebib(unsigned nnn);
void bx_instr_opcode_g2evib(unsigned nnn);
void bx_instr_opcode_g2eb1(unsigned nnn);
void bx_instr_opcode_g2ev1(unsigned nnn);
void bx_instr_opcode_g2ebcl(unsigned nnn);
void bx_instr_opcode_g2evcl(unsigned nnn);
void bx_instr_opcode_g3eb(unsigned nnn);
void bx_instr_opcode_g3ev(unsigned nnn);
void bx_instr_opcode_g4(unsigned nnn);
void bx_instr_opcode_g5(unsigned nnn);
void bx_instr_opcode_g6(unsigned nnn);
void bx_instr_opcode_g7(unsigned nnn);
void bx_instr_opcode_g8evib(unsigned nnn);
void bx_instr_mem_code(Bit32u linear, unsigned size);
void bx_instr_mem_data(Bit32u linear, unsigned size, unsigned rw);
void bx_instr_opcode_begin(Bit32u linear);
void bx_instr_opcode_end(Bit32u linear);
void bx_instr_fetch_byte(Bit8u val8);
void bx_instr_fetch_word(Bit16u val16);
void bx_instr_fetch_dword(Bit32u val32);
void bx_instr_phy_write(Bit32u addr, unsigned len);
void bx_instr_phy_read(Bit32u addr, unsigned len);
void bx_instr_interrupt(unsigned vector);
void bx_instr_exception(unsigned vector);
void bx_instr_init(unsigned cpu);
void bx_instr_shutdown(unsigned cpu);
void bx_instr_reset(unsigned cpu);
void bx_instr_new_instruction(unsigned cpu);
void bx_instr_debug_promt();
void bx_instr_start();
void bx_instr_stop();
void bx_instr_print();
void bx_instr_cnear_branch_taken(unsigned cpu, bx_address new_eip);
void bx_instr_cnear_branch_not_taken(unsigned cpu);
void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip);
void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip);
void bx_instr_opcode(unsigned cpu, Bit8u *opcode, unsigned len, Boolean is32);
void bx_instr_fetch_decode_completed(unsigned cpu, BxInstruction_t *i);
void bx_instr_prefix_as(unsigned cpu);
void bx_instr_prefix_os(unsigned cpu);
void bx_instr_prefix_rep(unsigned cpu);
void bx_instr_prefix_repne(unsigned cpu);
void bx_instr_prefix_lock(unsigned cpu);
void bx_instr_prefix_cs(unsigned cpu);
void bx_instr_prefix_ss(unsigned cpu);
void bx_instr_prefix_ds(unsigned cpu);
void bx_instr_prefix_es(unsigned cpu);
void bx_instr_prefix_fs(unsigned cpu);
void bx_instr_prefix_gs(unsigned cpu);
void bx_instr_prefix_extend8b(unsigned cpu);
void bx_instr_interrupt(unsigned cpu, unsigned vector);
void bx_instr_exception(unsigned cpu, unsigned vector);
void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip);
void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, Bit32u newval);
void bx_instr_cache_cntrl(unsigned cpu, unsigned what);
void bx_instr_repeat_iteration(unsigned cpu);
void bx_instr_inp(Bit16u addr, unsigned len);
void bx_instr_outp(Bit16u addr, unsigned len);
void bx_instr_inp2(Bit16u addr, unsigned len, unsigned val);
void bx_instr_outp2(Bit16u addr, unsigned len, unsigned val);
void bx_instr_tlb_cntrl(unsigned what, Bit32u newval);
void bx_instr_cache_cntrl(unsigned what);
void bx_instr_hwinterrupt(unsigned vector, Bit32u cs, Bit32u eip);
void bx_instr_init(void);
void bx_instr_shutdown(void);
void bx_instr_opcode_repeating(void);
void bx_instr_prefix_as(void);
void bx_instr_prefix_os(void);
void bx_instr_prefix_rep(void);
void bx_instr_prefix_repne(void);
void bx_instr_prefix_lock(void);
void bx_instr_prefix_cs(void);
void bx_instr_prefix_ss(void);
void bx_instr_prefix_ds(void);
void bx_instr_prefix_es(void);
void bx_instr_prefix_fs(void);
void bx_instr_prefix_gs(void);
void bx_instr_modrm32(unsigned modrm);
void bx_instr_sib32(unsigned sib);
void bx_instr_modrm16(unsigned modrm);
void bx_instr_iret(void);
void bx_instr_debug_prompt(void);
void bx_instr_lin_read(Bit32u lin, Bit32u phy, unsigned len);
void bx_instr_lin_write(Bit32u lin, Bit32u phy, unsigned len);
// called from the debug prompt
void bx_instr_start(void);
void bx_instr_stop(void);
void bx_instr_reset(void);
void bx_instr_print(void);
void bx_instr_mem_code(unsigned cpu, bx_address linear, unsigned size);
void bx_instr_mem_data(unsigned cpu, bx_address linear, unsigned size, unsigned rw);
# define BX_INSTR_INIT() bx_instr_init()
# define BX_INSTR_SHUTDOWN() bx_instr_shutdown()
# define BX_INSTR_CNEAR_BRANCH_TAKEN(new_eip) bx_instr_cnear_branch_taken(new_eip)
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN() bx_instr_cnear_branch_not_taken()
# define BX_INSTR_UCNEAR_BRANCH(what, new_eip) bx_instr_ucnear_branch(what, new_eip)
# define BX_INSTR_FAR_BRANCH(what, new_cs, new_eip) bx_instr_far_branch(what, new_cs, new_eip)
# define BX_INSTR_OPCODE_BEGIN(linear) bx_instr_opcode_begin(linear)
# define BX_INSTR_OPCODE_END(linear) bx_instr_opcode_end(linear)
# define BX_INSTR_OPCODE_BYTE1(b) bx_instr_opcode_byte1(b)
# define BX_INSTR_OPCODE_BYTE2(b) bx_instr_opcode_byte2(b)
# define BX_INSTR_OPCODE_G1EbIb(nnn) bx_instr_opcode_g1ebib(nnn)
# define BX_INSTR_OPCODE_G1EvIv(nnn) bx_instr_opcode_g1eviv(nnn)
# define BX_INSTR_OPCODE_G1EvIb(nnn) bx_instr_opcode_g1evib(nnn)
# define BX_INSTR_OPCODE_G2EbIb(nnn) bx_instr_opcode_g2ebib(nnn)
# define BX_INSTR_OPCODE_G2EvIb(nnn) bx_instr_opcode_g2evib(nnn)
# define BX_INSTR_OPCODE_G2Eb1(nnn) bx_instr_opcode_g2eb1(nnn)
# define BX_INSTR_OPCODE_G2Ev1(nnn) bx_instr_opcode_g2ev1(nnn)
# define BX_INSTR_OPCODE_G2EbCL(nnn) bx_instr_opcode_g2ebcl(nnn)
# define BX_INSTR_OPCODE_G2EvCL(nnn) bx_instr_opcode_g2evcl(nnn)
# define BX_INSTR_OPCODE_G3Eb(nnn) bx_instr_opcode_g3eb(nnn)
# define BX_INSTR_OPCODE_G3Ev(nnn) bx_instr_opcode_g3ev(nnn)
# define BX_INSTR_OPCODE_G4(nnn) bx_instr_opcode_g4(nnn)
# define BX_INSTR_OPCODE_G5(nnn) bx_instr_opcode_g5(nnn)
# define BX_INSTR_OPCODE_G6(nnn) bx_instr_opcode_g6(nnn)
# define BX_INSTR_OPCODE_G7(nnn) bx_instr_opcode_g7(nnn)
# define BX_INSTR_OPCODE_G8EvIb(nnn) bx_instr_opcode_g8evib(nnn)
# define BX_INSTR_MEM_CODE(linear, size) bx_instr_mem_code(linear, size)
# define BX_INSTR_MEM_DATA(linear, size, rw) bx_instr_mem_data(linear, size, rw)
# define BX_INSTR_EXCEPTION(vector) bx_instr_exception(vector)
# define BX_INSTR_INP(addr, len) bx_instr_inp(addr, len)
# define BX_INSTR_INP2(addr, len, val) bx_instr_inp2(addr, len, val)
# define BX_INSTR_OUTP(addr, len) bx_instr_outp(addr, len)
# define BX_INSTR_OUTP2(addr, len, val) bx_instr_outp2(addr, len, val)
# define BX_INSTR_FETCH_BYTE(val8) bx_instr_fetch_byte(val8)
# define BX_INSTR_FETCH_WORD(val16) bx_instr_fetch_word(val16)
# define BX_INSTR_FETCH_DWORD(val32) bx_instr_fetch_dword(val32)
# define BX_INSTR_PHY_WRITE(addr, len) bx_instr_phy_write(addr, len)
# define BX_INSTR_PHY_READ(addr, len) bx_instr_phy_read(addr, len)
# define BX_INSTR_INTERRUPT(vector) bx_instr_interrupt(vector)
void bx_instr_lin_read(unsigned cpu, bx_address lin, bx_address phy, unsigned len);
void bx_instr_lin_write(unsigned cpu, bx_address lin, bx_address phy, unsigned len);
# define BX_INSTR_TLB_CNTRL(what, newval) bx_instr_tlb_cntrl(what, newval)
# define BX_INSTR_CACHE_CNTRL(what) bx_instr_cache_cntrl(what)
# define BX_INSTR_HWINTERRUPT(vector, cs, eip) bx_instr_hwinterrupt(vector, cs, eip)
# define BX_INSTR_OPCODE_REPEATING() bx_instr_opcode_repeating()
void bx_instr_phy_write(bx_address addr, unsigned len);
void bx_instr_phy_read(bx_address addr, unsigned len);
# define BX_INSTR_PREFIX_AS() bx_instr_prefix_as()
# define BX_INSTR_PREFIX_OS() bx_instr_prefix_os()
# define BX_INSTR_PREFIX_REP() bx_instr_prefix_rep()
# define BX_INSTR_PREFIX_REPNE() bx_instr_prefix_repne()
# define BX_INSTR_PREFIX_LOCK() bx_instr_prefix_lock()
# define BX_INSTR_PREFIX_CS() bx_instr_prefix_cs()
# define BX_INSTR_PREFIX_SS() bx_instr_prefix_ss()
# define BX_INSTR_PREFIX_DS() bx_instr_prefix_ds()
# define BX_INSTR_PREFIX_ES() bx_instr_prefix_es()
# define BX_INSTR_PREFIX_FS() bx_instr_prefix_fs()
# define BX_INSTR_PREFIX_GS() bx_instr_prefix_gs()
/* simulation init, shutdown, reset */
# define BX_INSTR_INIT(cpu_id) bx_instr_init(cpu_id)
# define BX_INSTR_SHUTDOWN(cpu_id) bx_instr_shutdown(cpu_id)
# define BX_INSTR_RESET(cpu_id) bx_instr_reset(cpu_id)
# define BX_INSTR_NEW_INSTRUCTION(cpu_id) bx_instr_new_instruction(cpu_id)
# define BX_INSTR_MODRM32(modrm) bx_instr_modrm32(modrm)
# define BX_INSTR_SIB32(sib) bx_instr_sib32(sib)
# define BX_INSTR_MODRM16(modrm) bx_instr_modrm16(modrm)
# define BX_INSTR_SIB_mod0_base5(ss)
# define BX_INSTR_SIB_MOD0_IND4()
# define BX_INSTR_SIB_MOD1_IND4()
# define BX_INSTR_SIB_MOD2_IND4()
/* called from command line debugger */
# define BX_INSTR_DEBUG_PROMPT() bx_instr_debug_promt()
# define BX_INSTR_START() bx_instr_start()
# define BX_INSTR_STOP() bx_instr_stop()
# define BX_INSTR_PRINT() bx_instr_print()
# define BX_INSTR_IRET() bx_instr_iret()
# define BX_INSTR_DEBUG_PROMPT() bx_instr_debug_prompt()
/* branch resoultion */
# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip) bx_instr_cnear_branch_taken(cpu_id, new_eip)
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id) bx_instr_cnear_branch_not_taken(cpu_id)
# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip) bx_instr_ucnear_branch(cpu_id, what, new_eip)
# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) bx_instr_far_branch(cpu_id, what, new_cs, new_eip)
# define BX_INSTR_LIN_READ(lin, phy, len) bx_instr_lin_read(lin, phy, len)
# define BX_INSTR_LIN_WRITE(lin, phy, len) bx_instr_lin_write(lin, phy, len)
# define BX_INSTR_START() bx_instr_start ()
# define BX_INSTR_STOP() bx_instr_stop ()
# define BX_INSTR_RESET() bx_instr_reset ()
# define BX_INSTR_PRINT() bx_instr_print ()
/* decoding completed */
# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32) \
bx_instr_opcode(cpu_id, opcode, len, is32)
# define BX_INSTR_FETCH_DECODE_COMPLETED(cpu_id, i) \
bx_instr_fetch_decode_completed(cpu_id, i)
/* prefix decoded */
# define BX_INSTR_PREFIX_AS(cpu_id) bx_instr_prefix_as(cpu_id)
# define BX_INSTR_PREFIX_OS(cpu_id) bx_instr_prefix_os(cpu_id)
# define BX_INSTR_PREFIX_REP(cpu_id) bx_instr_prefix_rep(cpu_id)
# define BX_INSTR_PREFIX_REPNE(cpu_id) bx_instr_prefix_repne(cpu_id)
# define BX_INSTR_PREFIX_LOCK(cpu_id) bx_instr_prefix_lock(cpu_id)
# define BX_INSTR_PREFIX_CS(cpu_id) bx_instr_prefix_cs(cpu_id)
# define BX_INSTR_PREFIX_SS(cpu_id) bx_instr_prefix_ss(cpu_id)
# define BX_INSTR_PREFIX_DS(cpu_id) bx_instr_prefix_ds(cpu_id)
# define BX_INSTR_PREFIX_ES(cpu_id) bx_instr_prefix_es(cpu_id)
# define BX_INSTR_PREFIX_FS(cpu_id) bx_instr_prefix_fs(cpu_id)
# define BX_INSTR_PREFIX_GS(cpu_id) bx_instr_prefix_gs(cpu_id)
# define BX_INSTR_PREFIX_EXTEND8B(cpu_id) bx_instr_prefix_extend8b(cpu_id)
#else // #if BX_INSTRUMENTATION
# define BX_INSTR_INIT()
# define BX_INSTR_SHUTDOWN()
# define BX_INSTR_CNEAR_BRANCH_TAKEN(new_eip)
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN()
# define BX_INSTR_UCNEAR_BRANCH(what, new_eip)
# define BX_INSTR_FAR_BRANCH(what, new_cs, new_eip)
# define BX_INSTR_OPCODE_BEGIN(linear)
# define BX_INSTR_OPCODE_END(linear)
# define BX_INSTR_OPCODE_BYTE1(b)
# define BX_INSTR_OPCODE_BYTE2(b)
# define BX_INSTR_OPCODE_G1EbIb(nnn)
# define BX_INSTR_OPCODE_G1EvIv(nnn)
# define BX_INSTR_OPCODE_G1EvIb(nnn)
# define BX_INSTR_OPCODE_G2EbIb(nnn)
# define BX_INSTR_OPCODE_G2EvIb(nnn)
# define BX_INSTR_OPCODE_G2Eb1(nnn)
# define BX_INSTR_OPCODE_G2Ev1(nnn)
# define BX_INSTR_OPCODE_G2EbCL(nnn)
# define BX_INSTR_OPCODE_G2EvCL(nnn)
# define BX_INSTR_OPCODE_G3Eb(nnn)
# define BX_INSTR_OPCODE_G3Ev(nnn)
# define BX_INSTR_OPCODE_G4(nnn)
# define BX_INSTR_OPCODE_G5(nnn)
# define BX_INSTR_OPCODE_G6(nnn)
# define BX_INSTR_OPCODE_G7(nnn)
# define BX_INSTR_OPCODE_G8EvIb(nnn)
# define BX_INSTR_MEM_CODE(linear, size)
# define BX_INSTR_MEM_DATA(linear, size, rw)
# define BX_INSTR_EXCEPTION(vector)
/* exceptional case and interrupt */
# define BX_INSTR_EXCEPTION(cpu_id, vector) bx_instr_exception(cpu_id, vector)
# define BX_INSTR_INTERRUPT(cpu_id, vector) bx_instr_interrupt(cpu_id, vector)
# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) bx_instr_hwinterrupt(cpu_id, vector, cs, eip)
/* TLB/CACHE control instruction executed */
# define BX_INSTR_CACHE_CNTRL(cpu_id, what) bx_instr_cache_cntrl(cpu_id, what)
# define BX_INSTR_TLB_CNTRL(cpu_id, what, newval) bx_instr_tlb_cntrl(cpu_id, what, newval)
# define BX_INSTR_REPEAT_ITERATION(cpu_id) bx_instr_repeat_iteration(cpu_id, )
/* memory access */
# define BX_INSTR_LIN_READ(cpu_id, lin, phy, len) bx_instr_lin_read(cpu_id, lin, phy, len)
# define BX_INSTR_LIN_WRITE(cpu_id, lin, phy, len) bx_instr_lin_write(cpu_id, lin, phy, len)
# define BX_INSTR_MEM_CODE(cpu_id, linear, size) bx_instr_mem_code(cpu_id, linear, size)
# define BX_INSTR_MEM_DATA(cpu_id, linear, size, rw) bx_instr_mem_data(cpu_id, linear, size, rw)
/* called from memory object */
# define BX_INSTR_PHY_WRITE(addr, len) bx_instr_phy_write(addr, len)
# define BX_INSTR_PHY_READ(addr, len) bx_instr_phy_read(addr, len)
/* feedback from device units */
# define BX_INSTR_INP(addr, len) bx_instr_inp(addr, len)
# define BX_INSTR_INP2(addr, len, val) bx_instr_inp2(addr, len, val)
# define BX_INSTR_OUTP(addr, len) bx_instr_outp(addr, len)
# define BX_INSTR_OUTP2(addr, len, val) bx_instr_outp2(addr, len, val)
#else
/* simulation init, shutdown, reset */
# define BX_INSTR_INIT(cpu_id)
# define BX_INSTR_SHUTDOWN(cpu_id)
# define BX_INSTR_RESET(cpu_id)
# define BX_INSTR_NEW_INSTRUCTION(cpu_id)
/* called from command line debugger */
# define BX_INSTR_DEBUG_PROMPT()
# define BX_INSTR_START()
# define BX_INSTR_STOP()
# define BX_INSTR_PRINT()
/* branch resoultion */
# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip)
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id)
# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip)
# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
/* decoding completed */
# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32)
# define BX_INSTR_FETCH_DECODE_COMPLETED(cpu_id, i)
/* prefix decoded */
# define BX_INSTR_PREFIX_AS(cpu_id)
# define BX_INSTR_PREFIX_OS(cpu_id)
# define BX_INSTR_PREFIX_REP(cpu_id)
# define BX_INSTR_PREFIX_REPNE(cpu_id)
# define BX_INSTR_PREFIX_LOCK(cpu_id)
# define BX_INSTR_PREFIX_CS(cpu_id)
# define BX_INSTR_PREFIX_SS(cpu_id)
# define BX_INSTR_PREFIX_DS(cpu_id)
# define BX_INSTR_PREFIX_ES(cpu_id)
# define BX_INSTR_PREFIX_FS(cpu_id)
# define BX_INSTR_PREFIX_GS(cpu_id)
# define BX_INSTR_PREFIX_EXTEND8B(cpu_id)
/* exceptional case and interrupt */
# define BX_INSTR_EXCEPTION(cpu_id, vector)
# define BX_INSTR_INTERRUPT(cpu_id, vector)
# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
/* TLB/CACHE control instruction executed */
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
# define BX_INSTR_TLB_CNTRL(cpu_id, what, newval)
# define BX_INSTR_REPEAT_ITERATION(cpu_id)
/* memory access */
# define BX_INSTR_LIN_READ(cpu_id, lin, phy, len)
# define BX_INSTR_LIN_WRITE(cpu_id, lin, phy, len)
# define BX_INSTR_MEM_CODE(cpu_id, linear, size)
# define BX_INSTR_MEM_DATA(cpu_id, linear, size, rw)
/* called from memory object */
# define BX_INSTR_PHY_WRITE(addr, len)
# define BX_INSTR_PHY_READ(addr, len)
/* feedback from device units */
# define BX_INSTR_INP(addr, len)
# define BX_INSTR_INP2(addr, len, val)
# define BX_INSTR_OUTP(addr, len)
# define BX_INSTR_OUTP2(addr, len, val)
# define BX_INSTR_FETCH_BYTE(val8)
# define BX_INSTR_FETCH_WORD(val16)
# define BX_INSTR_FETCH_DWORD(val32)
# define BX_INSTR_PHY_WRITE(addr, len)
# define BX_INSTR_PHY_READ(addr, len)
# define BX_INSTR_INTERRUPT(vector)
# define BX_INSTR_TLB_CNTRL(what, newval)
# define BX_INSTR_CACHE_CNTRL(what)
# define BX_INSTR_HWINTERRUPT(vector, cs, eip)
# define BX_INSTR_OPCODE_REPEATING()
# define BX_INSTR_PREFIX_AS()
# define BX_INSTR_PREFIX_OS()
# define BX_INSTR_PREFIX_REP()
# define BX_INSTR_PREFIX_REPNE()
# define BX_INSTR_PREFIX_LOCK()
# define BX_INSTR_PREFIX_CS()
# define BX_INSTR_PREFIX_SS()
# define BX_INSTR_PREFIX_DS()
# define BX_INSTR_PREFIX_ES()
# define BX_INSTR_PREFIX_FS()
# define BX_INSTR_PREFIX_GS()
# define BX_INSTR_MODRM32(modrm)
# define BX_INSTR_SIB32(sib)
# define BX_INSTR_MODRM16(modrm)
# define BX_INSTR_SIB_mod0_base5(ss)
# define BX_INSTR_SIB_MOD0_IND4()
# define BX_INSTR_SIB_MOD1_IND4()
# define BX_INSTR_SIB_MOD2_IND4()
# define BX_INSTR_IRET()
# define BX_INSTR_DEBUG_PROMPT()
# define BX_INSTR_LIN_READ(lin, phy, len)
# define BX_INSTR_LIN_WRITE(lin, phy, len)
# define BX_INSTR_START()
# define BX_INSTR_STOP()
# define BX_INSTR_RESET()
# define BX_INSTR_PRINT()
#endif // #if BX_INSTRUMENTATION
#endif