2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2005-05-21 00:06:50 +04:00
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// $Id: debugstuff.cc,v 1.39 2005-05-20 20:06:50 sshwarts Exp $
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2001-04-10 06:20:02 +04:00
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// Copyright (C) 2001 MandrakeSoft S.A.
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2001-04-10 05:04:59 +04:00
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2001-05-24 22:46:34 +04:00
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#define NEED_CPU_REG_SHORTCUTS 1
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2001-04-10 05:04:59 +04:00
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#include "bochs.h"
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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#define LOG_THIS BX_CPU_THIS_PTR
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2001-04-10 05:04:59 +04:00
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2005-03-30 23:56:02 +04:00
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void BX_CPU_C::debug(bx_address offset)
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2001-04-10 05:04:59 +04:00
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{
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2005-03-30 23:56:02 +04:00
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static const char *cpu_mode_name[] = {
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"real mode",
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"v8086 mode",
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"protected mode",
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"compatibility mode",
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"long mode"
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};
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if (BX_CPU_THIS_PTR cpu_mode < 5)
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BX_INFO(("%s", cpu_mode_name[BX_CPU_THIS_PTR cpu_mode]));
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BX_INFO(("CS.d_b = %u bit",
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b ? 32 : 16));
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BX_INFO(("SS.d_b = %u bit",
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b ? 32 : 16));
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#if BX_SUPPORT_X86_64
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BX_INFO(("| RAX=%08x%08x RBX=%08x%08x",
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(unsigned) (RAX >> 32), (unsigned) EAX,
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(unsigned) (RBX >> 32), (unsigned) EBX));
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BX_INFO(("| RCX=%08x%08x RDX=%08x%08x",
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(unsigned) (RCX >> 32), (unsigned) ECX,
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(unsigned) (RDX >> 32), (unsigned) EDX));
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BX_INFO(("| RSP=%08x%08x RBP=%08x%08x",
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(unsigned) (RSP >> 32), (unsigned) ESP,
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(unsigned) (RBP >> 32), (unsigned) EBP));
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BX_INFO(("| RSI=%08x%08x RDI=%08x%08x",
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(unsigned) (RSI >> 32), (unsigned) ESI,
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(unsigned) (RDI >> 32), (unsigned) EDI));
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#else
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2001-05-30 22:56:02 +04:00
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BX_INFO(("| EAX=%08x EBX=%08x ECX=%08x EDX=%08x",
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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(unsigned) EAX, (unsigned) EBX, (unsigned) ECX, (unsigned) EDX));
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2001-05-30 22:56:02 +04:00
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BX_INFO(("| ESP=%08x EBP=%08x ESI=%08x EDI=%08x",
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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(unsigned) ESP, (unsigned) EBP, (unsigned) ESI, (unsigned) EDI));
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2005-03-30 23:56:02 +04:00
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#endif
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2001-05-30 22:56:02 +04:00
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BX_INFO(("| IOPL=%1u %s %s %s %s %s %s %s %s",
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2002-09-12 22:10:46 +04:00
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BX_CPU_THIS_PTR get_IOPL (),
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- the debugger was broken by recent changes in the cpu flags. To provide
a consistent way of accessing these flags that works both inside and
outside the BX_CPU class, I added inline accessor methods for each
flag: assert_FLAG(), clear_FLAG(), set_FLAG(value), and get_FLAG ()
that returns its value. I use assert to mean "set the value to one"
to avoid confusion, since there's also a set method that takes a value.
- the eflags access macros (e.g. GetEFlagsDFLogical, ClearEFlagsTF) are
now defined in terms of the inline accessors. In most cases it will
result in the same code anyway. The major advantage of the accesors
is that they can be used from inside or outside the BX_CPU object, while
the macros can only be used from inside.
- since almost all eflags were stored in val32 now, I went ahead and
removed the if_, rf, and vm fields. Now the val32 bit is the
"official" value for these flags, and they have accessors just like
everything else.
- init.cc: move the registration of registers until after they have been
initialized so that the initial value of each parameter is correct.
Modified files:
debug/dbg_main.cc cpu/cpu.h cpu/debugstuff.cc cpu/flag_ctrl.cc
cpu/flag_ctrl_pro.cc cpu/init.cc
2002-09-11 07:55:22 +04:00
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BX_CPU_THIS_PTR get_OF() ? "OV" : "NV",
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2002-09-12 22:10:46 +04:00
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BX_CPU_THIS_PTR get_DF() ? "DW" : "UP",
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BX_CPU_THIS_PTR get_IF() ? "EI" : "DI",
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- the debugger was broken by recent changes in the cpu flags. To provide
a consistent way of accessing these flags that works both inside and
outside the BX_CPU class, I added inline accessor methods for each
flag: assert_FLAG(), clear_FLAG(), set_FLAG(value), and get_FLAG ()
that returns its value. I use assert to mean "set the value to one"
to avoid confusion, since there's also a set method that takes a value.
- the eflags access macros (e.g. GetEFlagsDFLogical, ClearEFlagsTF) are
now defined in terms of the inline accessors. In most cases it will
result in the same code anyway. The major advantage of the accesors
is that they can be used from inside or outside the BX_CPU object, while
the macros can only be used from inside.
- since almost all eflags were stored in val32 now, I went ahead and
removed the if_, rf, and vm fields. Now the val32 bit is the
"official" value for these flags, and they have accessors just like
everything else.
- init.cc: move the registration of registers until after they have been
initialized so that the initial value of each parameter is correct.
Modified files:
debug/dbg_main.cc cpu/cpu.h cpu/debugstuff.cc cpu/flag_ctrl.cc
cpu/flag_ctrl_pro.cc cpu/init.cc
2002-09-11 07:55:22 +04:00
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BX_CPU_THIS_PTR get_SF() ? "NG" : "PL",
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BX_CPU_THIS_PTR get_ZF() ? "ZR" : "NZ",
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BX_CPU_THIS_PTR get_AF() ? "AC" : "NA",
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BX_CPU_THIS_PTR get_PF() ? "PE" : "PO",
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BX_CPU_THIS_PTR get_CF() ? "CY" : "NC"));
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2001-05-30 22:56:02 +04:00
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BX_INFO(("| SEG selector base limit G D"));
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BX_INFO(("| SEG sltr(index|ti|rpl) base limit G D"));
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2005-03-30 23:56:02 +04:00
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BX_INFO(("| CS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b));
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2001-05-30 22:56:02 +04:00
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BX_INFO(("| DS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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2001-04-10 05:04:59 +04:00
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.g,
|
merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.d_b));
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2005-03-30 23:56:02 +04:00
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BX_INFO(("| SS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b));
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2001-05-30 22:56:02 +04:00
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BX_INFO(("| ES:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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2001-04-10 05:04:59 +04:00
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.g,
|
merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.d_b));
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2001-05-30 22:56:02 +04:00
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BX_INFO(("| FS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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2001-04-10 05:04:59 +04:00
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.g,
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.d_b));
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2001-05-30 22:56:02 +04:00
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BX_INFO(("| GS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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2001-04-10 05:04:59 +04:00
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.g,
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
|
|
|
(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.d_b));
|
2005-03-30 23:56:02 +04:00
|
|
|
|
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
|
BX_INFO(("| RIP=%08x%08x (%08x%08x)",
|
|
|
|
|
(unsigned) BX_CPU_THIS_PTR dword.rip_upper, (unsigned) EIP,
|
|
|
|
|
(unsigned) (BX_CPU_THIS_PTR prev_eip >> 32),
|
|
|
|
|
(unsigned) (BX_CPU_THIS_PTR prev_eip & 0xffffffff)));
|
|
|
|
|
BX_INFO(("| CR0=0x%08x CR1=0x%x CR2=0x%08x%08x",
|
|
|
|
|
(unsigned) (BX_CPU_THIS_PTR cr0.val32), 0,
|
|
|
|
|
(unsigned) (BX_CPU_THIS_PTR cr2 >> 32),
|
|
|
|
|
(unsigned) (BX_CPU_THIS_PTR cr2 & 0xffffffff)));
|
|
|
|
|
BX_INFO(("| CR3=0x%08x%08x CR4=0x%08x",
|
|
|
|
|
(unsigned) (BX_CPU_THIS_PTR cr3 >> 32),
|
|
|
|
|
(unsigned) (BX_CPU_THIS_PTR cr3 & 0xffffffff),
|
|
|
|
|
BX_CPU_THIS_PTR cr4.getRegister()));
|
|
|
|
|
#else
|
2002-09-13 04:15:23 +04:00
|
|
|
BX_INFO(("| EIP=%08x (%08x)", (unsigned) EIP,
|
merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
|
|
|
(unsigned) BX_CPU_THIS_PTR prev_eip));
|
2005-03-30 23:56:02 +04:00
|
|
|
|
2002-09-24 02:10:00 +04:00
|
|
|
#if BX_CPU_LEVEL >= 2 && BX_CPU_LEVEL < 4
|
2005-03-30 23:56:02 +04:00
|
|
|
BX_INFO(("| CR0=0x%08x CR1=%x CR2=0x%08x CR3=0x%08x",
|
|
|
|
|
BX_CPU_THIS_PTR cr0.val32, 0,
|
2002-09-24 02:10:00 +04:00
|
|
|
BX_CPU_THIS_PTR cr2,
|
|
|
|
|
BX_CPU_THIS_PTR cr3));
|
|
|
|
|
#elif BX_CPU_LEVEL >= 4
|
2005-03-30 23:56:02 +04:00
|
|
|
BX_INFO(("| CR0=0x%08x CR1=%x CR2=0x%08x",
|
|
|
|
|
BX_CPU_THIS_PTR cr0.val32, 0,
|
2002-09-24 02:10:00 +04:00
|
|
|
BX_CPU_THIS_PTR cr2));
|
|
|
|
|
BX_INFO(("| CR3=0x%08x CR4=0x%08x",
|
|
|
|
|
BX_CPU_THIS_PTR cr3,
|
|
|
|
|
BX_CPU_THIS_PTR cr4.getRegister()));
|
|
|
|
|
#endif
|
2002-10-04 21:04:33 +04:00
|
|
|
|
2005-03-30 23:56:02 +04:00
|
|
|
#endif // BX_SUPPORT_X86_64
|
|
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
/* (mch) Hack to display the area round EIP and prev_EIP */
|
|
|
|
|
char buf[100];
|
2002-10-17 02:10:07 +04:00
|
|
|
sprintf(buf, "%04x:%08x ", BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
|
2001-04-10 05:04:59 +04:00
|
|
|
for (int i = 0; i < 8; i++) {
|
|
|
|
|
Bit8u data;
|
2002-10-17 02:10:07 +04:00
|
|
|
BX_CPU_THIS_PTR read_virtual_byte(BX_SEG_REG_CS, EIP + i, &data);
|
2001-04-10 05:04:59 +04:00
|
|
|
sprintf(buf+strlen(buf), "%02x ", data);
|
2005-03-30 23:56:02 +04:00
|
|
|
}
|
merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
|
|
|
BX_INFO((buf));
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2002-10-17 02:10:07 +04:00
|
|
|
sprintf(buf, "%04x:%08x ", BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR prev_eip);
|
2001-04-10 05:04:59 +04:00
|
|
|
for (int i = 0; i < 8; i++) {
|
|
|
|
|
Bit8u data;
|
2002-10-17 02:10:07 +04:00
|
|
|
BX_CPU_THIS_PTR read_virtual_byte(BX_SEG_REG_CS, BX_CPU_THIS_PTR prev_eip + i, &data);
|
2001-04-10 05:04:59 +04:00
|
|
|
sprintf(buf+strlen(buf), "%02x ", data);
|
2005-03-30 23:56:02 +04:00
|
|
|
}
|
merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
|
|
|
BX_INFO((buf));
|
2001-04-10 05:04:59 +04:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#if BX_DISASM
|
2002-10-25 15:44:41 +04:00
|
|
|
bx_bool valid;
|
2003-08-04 20:03:09 +04:00
|
|
|
Bit32u phy_addr, Base;
|
2001-04-10 05:04:59 +04:00
|
|
|
Bit8u instr_buf[32];
|
|
|
|
|
char char_buf[256];
|
|
|
|
|
unsigned isize;
|
|
|
|
|
|
2003-12-24 23:32:59 +03:00
|
|
|
static disassembler bx_disassemble;
|
|
|
|
|
|
2005-03-15 22:00:04 +03:00
|
|
|
if (BX_CPU_THIS_PTR protected_mode()) { // 16bit & 32bit protected mode
|
|
|
|
|
Base=BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS);
|
2003-08-04 20:03:09 +04:00
|
|
|
}
|
|
|
|
|
else {
|
2005-03-15 22:00:04 +03:00
|
|
|
Base=BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value<<4;
|
2003-08-04 20:03:09 +04:00
|
|
|
}
|
|
|
|
|
|
2005-02-28 21:56:05 +03:00
|
|
|
dbg_xlate_linear2phy(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + offset,
|
2001-04-10 05:04:59 +04:00
|
|
|
&phy_addr, &valid);
|
2002-10-25 15:54:42 +04:00
|
|
|
if (valid && BX_CPU_THIS_PTR mem!=NULL) {
|
2001-05-23 12:16:07 +04:00
|
|
|
BX_CPU_THIS_PTR mem->dbg_fetch_mem(phy_addr, 16, instr_buf);
|
2002-10-04 21:04:33 +04:00
|
|
|
isize = bx_disassemble.disasm(
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b,
|
2003-08-04 20:03:09 +04:00
|
|
|
Base,
|
2002-10-04 21:04:33 +04:00
|
|
|
EIP, instr_buf, char_buf);
|
2005-03-30 23:56:02 +04:00
|
|
|
#if BX_SUPPORT_X86_64
|
2005-03-31 02:31:03 +04:00
|
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) isize = 16;
|
2005-03-30 23:56:02 +04:00
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
for (unsigned j=0; j<isize; j++)
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_INFO((">> %02x", (unsigned) instr_buf[j]));
|
|
|
|
|
BX_INFO((">> : %s", char_buf));
|
2005-03-15 22:00:04 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_INFO(("(instruction unavailable) page not present"));
|
2005-03-15 22:00:04 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
#else
|
|
|
|
|
UNUSED(offset);
|
|
|
|
|
#endif // #if BX_DISASM
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#if BX_DEBUGGER
|
2005-03-28 22:19:02 +04:00
|
|
|
Bit32u BX_CPU_C::dbg_get_reg(unsigned reg)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
|
Bit32u return_val32;
|
|
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
|
case BX_DBG_REG_EAX: return(EAX);
|
|
|
|
|
case BX_DBG_REG_ECX: return(ECX);
|
|
|
|
|
case BX_DBG_REG_EDX: return(EDX);
|
|
|
|
|
case BX_DBG_REG_EBX: return(EBX);
|
|
|
|
|
case BX_DBG_REG_ESP: return(ESP);
|
|
|
|
|
case BX_DBG_REG_EBP: return(EBP);
|
|
|
|
|
case BX_DBG_REG_ESI: return(ESI);
|
|
|
|
|
case BX_DBG_REG_EDI: return(EDI);
|
|
|
|
|
case BX_DBG_REG_EIP: return(EIP);
|
|
|
|
|
case BX_DBG_REG_EFLAGS:
|
|
|
|
|
return_val32 = dbg_get_eflags();
|
|
|
|
|
return(return_val32);
|
|
|
|
|
case BX_DBG_REG_CS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
|
|
|
|
case BX_DBG_REG_SS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
|
|
|
|
|
case BX_DBG_REG_DS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
|
|
|
case BX_DBG_REG_ES: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
|
|
|
case BX_DBG_REG_FS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
|
|
|
case BX_DBG_REG_GS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
|
|
|
default:
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_PANIC(("get_reg: request for unknown register"));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
bx_bool BX_CPU_C::dbg_set_reg(unsigned reg, Bit32u val)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
|
// returns 1=OK, 0=can't change
|
|
|
|
|
bx_segment_reg_t *seg;
|
|
|
|
|
Bit32u current_sys_bits;
|
|
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
|
case BX_DBG_REG_EAX: EAX = val; return(1);
|
|
|
|
|
case BX_DBG_REG_ECX: ECX = val; return(1);
|
|
|
|
|
case BX_DBG_REG_EDX: EDX = val; return(1);
|
|
|
|
|
case BX_DBG_REG_EBX: EBX = val; return(1);
|
|
|
|
|
case BX_DBG_REG_ESP: ESP = val; return(1);
|
|
|
|
|
case BX_DBG_REG_EBP: EBP = val; return(1);
|
|
|
|
|
case BX_DBG_REG_ESI: ESI = val; return(1);
|
|
|
|
|
case BX_DBG_REG_EDI: EDI = val; return(1);
|
|
|
|
|
case BX_DBG_REG_EIP: EIP = val; return(1);
|
|
|
|
|
case BX_DBG_REG_EFLAGS:
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_INFO(("dbg_set_reg: can not handle eflags yet."));
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( val & 0xffff0000 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_INFO(("dbg_set_reg: can not set upper 16 bits of eflags."));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
// make sure none of the system bits are being changed
|
2002-09-24 22:33:38 +04:00
|
|
|
current_sys_bits = ((BX_CPU_THIS_PTR getB_NT()) << 14) |
|
2002-09-12 22:10:46 +04:00
|
|
|
(BX_CPU_THIS_PTR get_IOPL () << 12) |
|
2002-09-24 22:33:38 +04:00
|
|
|
((BX_CPU_THIS_PTR getB_TF()) << 8);
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( current_sys_bits != (val & 0x0000f100) ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_INFO(("dbg_set_reg: can not modify NT, IOPL, or TF."));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR set_CF(val & 0x01); val >>= 2;
|
|
|
|
|
BX_CPU_THIS_PTR set_PF(val & 0x01); val >>= 2;
|
|
|
|
|
BX_CPU_THIS_PTR set_AF(val & 0x01); val >>= 2;
|
|
|
|
|
BX_CPU_THIS_PTR set_ZF(val & 0x01); val >>= 1;
|
|
|
|
|
BX_CPU_THIS_PTR set_SF(val & 0x01); val >>= 2;
|
2002-09-12 22:10:46 +04:00
|
|
|
BX_CPU_THIS_PTR set_IF (val & 0x01); val >>= 1;
|
|
|
|
|
BX_CPU_THIS_PTR set_DF (val & 0x01); val >>= 1;
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR set_OF(val & 0x01);
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_IF ())
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
|
|
|
return(1);
|
|
|
|
|
case BX_DBG_REG_CS:
|
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS];
|
|
|
|
|
break;
|
|
|
|
|
case BX_DBG_REG_SS:
|
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS];
|
|
|
|
|
break;
|
|
|
|
|
case BX_DBG_REG_DS:
|
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS];
|
|
|
|
|
break;
|
|
|
|
|
case BX_DBG_REG_ES:
|
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
|
|
|
|
|
break;
|
|
|
|
|
case BX_DBG_REG_FS:
|
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS];
|
|
|
|
|
break;
|
|
|
|
|
case BX_DBG_REG_GS:
|
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS];
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_PANIC(("dbg_set_reg: unrecognized register ID (%u)", reg));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (BX_CPU_THIS_PTR real_mode()) {
|
|
|
|
|
seg->selector.value = val;
|
|
|
|
|
seg->cache.valid = 1;
|
|
|
|
|
seg->cache.p = 1;
|
|
|
|
|
seg->cache.dpl = 0;
|
|
|
|
|
seg->cache.segment = 1; // regular segment
|
|
|
|
|
if (reg == BX_DBG_REG_CS) {
|
|
|
|
|
seg->cache.u.segment.executable = 1; // code segment
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
|
|
|
|
seg->cache.u.segment.executable = 0; // data segment
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
seg->cache.u.segment.c_ed = 0; // expand up/non-conforming
|
|
|
|
|
seg->cache.u.segment.r_w = 1; // writeable
|
|
|
|
|
seg->cache.u.segment.a = 1; // accessed
|
|
|
|
|
seg->cache.u.segment.base = val << 4;
|
|
|
|
|
seg->cache.u.segment.limit = 0xffff;
|
|
|
|
|
seg->cache.u.segment.limit_scaled = 0xffff;
|
|
|
|
|
seg->cache.u.segment.g = 0; // byte granular
|
|
|
|
|
seg->cache.u.segment.d_b = 0; // default 16bit size
|
|
|
|
|
seg->cache.u.segment.avl = 0;
|
|
|
|
|
return(1); // ok
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
return(0); // can't change when not in real mode
|
|
|
|
|
}
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
unsigned BX_CPU_C::dbg_query_pending(void)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
|
unsigned ret = 0;
|
|
|
|
|
|
|
|
|
|
if ( BX_HRQ ) { // DMA Hold Request
|
|
|
|
|
ret |= BX_DBG_PENDING_DMA;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2002-09-12 22:10:46 +04:00
|
|
|
if ( BX_CPU_THIS_PTR INTR && BX_CPU_THIS_PTR get_IF () ) {
|
2001-04-10 05:04:59 +04:00
|
|
|
ret |= BX_DBG_PENDING_IRQ;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
return(ret);
|
|
|
|
|
}
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
Bit32u BX_CPU_C::dbg_get_eflags(void)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2004-09-30 20:50:03 +04:00
|
|
|
return (BX_CPU_THIS_PTR read_eflags());
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
Bit32u BX_CPU_C::dbg_get_descriptor_l(bx_descriptor_t *d)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
|
Bit32u val;
|
|
|
|
|
|
|
|
|
|
if (d->valid == 0) {
|
|
|
|
|
return(0);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (d->segment) {
|
|
|
|
|
val = ((d->u.segment.base & 0xffff) << 16) |
|
|
|
|
|
(d->u.segment.limit & 0xffff);
|
|
|
|
|
return(val);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
|
|
|
|
switch (d->type) {
|
|
|
|
|
case 0: // Reserved (not yet defined)
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "#get_descriptor_l(): type %d not finished", d->type ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0);
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
case BX_SYS_SEGMENT_AVAIL_286_TSS:
|
2001-04-10 05:04:59 +04:00
|
|
|
val = ((d->u.tss286.base & 0xffff) << 16) |
|
|
|
|
|
(d->u.tss286.limit & 0xffff);
|
|
|
|
|
return(val);
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
case BX_SYS_SEGMENT_LDT:
|
2001-04-10 05:04:59 +04:00
|
|
|
val = ((d->u.ldt.base & 0xffff) << 16) |
|
|
|
|
|
d->u.ldt.limit;
|
|
|
|
|
return(val);
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
case BX_SYS_SEGMENT_AVAIL_386_TSS:
|
2001-04-10 05:04:59 +04:00
|
|
|
val = ((d->u.tss386.base & 0xffff) << 16) |
|
|
|
|
|
(d->u.tss386.limit & 0xffff);
|
|
|
|
|
return(val);
|
|
|
|
|
|
|
|
|
|
default:
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "#get_descriptor_l(): type %d not finished", d->type ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0);
|
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
Bit32u BX_CPU_C::dbg_get_descriptor_h(bx_descriptor_t *d)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
|
Bit32u val;
|
|
|
|
|
|
|
|
|
|
if (d->valid == 0) {
|
|
|
|
|
return(0);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (d->segment) {
|
|
|
|
|
val = (d->u.segment.base & 0xff000000) |
|
|
|
|
|
((d->u.segment.base >> 16) & 0x000000ff) |
|
|
|
|
|
(d->u.segment.executable << 11) |
|
|
|
|
|
(d->u.segment.c_ed << 10) |
|
|
|
|
|
(d->u.segment.r_w << 9) |
|
|
|
|
|
(d->u.segment.a << 8) |
|
|
|
|
|
(d->segment << 12) |
|
|
|
|
|
(d->dpl << 13) |
|
|
|
|
|
(d->p << 15) |
|
|
|
|
|
(d->u.segment.limit & 0xf0000) |
|
|
|
|
|
(d->u.segment.avl << 20) |
|
|
|
|
|
(d->u.segment.d_b << 22) |
|
|
|
|
|
(d->u.segment.g << 23);
|
|
|
|
|
return(val);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
|
|
|
|
switch (d->type) {
|
|
|
|
|
case 0: // Reserved (not yet defined)
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "#get_descriptor_h(): type %d not finished", d->type ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0);
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
case BX_SYS_SEGMENT_AVAIL_286_TSS:
|
2001-04-10 05:04:59 +04:00
|
|
|
val = ((d->u.tss286.base >> 16) & 0xff) |
|
|
|
|
|
(d->type << 8) |
|
|
|
|
|
(d->dpl << 13) |
|
|
|
|
|
(d->p << 15);
|
|
|
|
|
return(val);
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
case BX_SYS_SEGMENT_LDT:
|
2001-04-10 05:04:59 +04:00
|
|
|
val = ((d->u.ldt.base >> 16) & 0xff) |
|
|
|
|
|
(d->type << 8) |
|
|
|
|
|
(d->dpl << 13) |
|
|
|
|
|
(d->p << 15) |
|
|
|
|
|
(d->u.ldt.base & 0xff000000);
|
|
|
|
|
return(val);
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
case BX_SYS_SEGMENT_AVAIL_386_TSS:
|
2001-04-10 05:04:59 +04:00
|
|
|
val = ((d->u.tss386.base >> 16) & 0xff) |
|
|
|
|
|
(d->type << 8) |
|
|
|
|
|
(d->dpl << 13) |
|
|
|
|
|
(d->p << 15) |
|
|
|
|
|
(d->u.tss386.limit & 0xf0000) |
|
|
|
|
|
(d->u.tss386.avl << 20) |
|
|
|
|
|
(d->u.tss386.g << 23) |
|
|
|
|
|
(d->u.tss386.base & 0xff000000);
|
|
|
|
|
return(val);
|
|
|
|
|
|
|
|
|
|
default:
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "#get_descriptor_h(): type %d not finished", d->type ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0);
|
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
bx_bool BX_CPU_C::dbg_get_sreg(bx_dbg_sreg_t *sreg, unsigned sreg_no)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
|
if (sreg_no > 5)
|
|
|
|
|
return(0);
|
|
|
|
|
sreg->sel = BX_CPU_THIS_PTR sregs[sreg_no].selector.value;
|
|
|
|
|
sreg->des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR sregs[sreg_no].cache);
|
|
|
|
|
sreg->des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR sregs[sreg_no].cache);
|
|
|
|
|
sreg->valid = BX_CPU_THIS_PTR sregs[sreg_no].cache.valid;
|
|
|
|
|
return(1);
|
|
|
|
|
}
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
bx_bool BX_CPU_C::dbg_get_cpu(bx_dbg_cpu_t *cpu)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
|
cpu->eax = EAX;
|
|
|
|
|
cpu->ebx = EBX;
|
|
|
|
|
cpu->ecx = ECX;
|
|
|
|
|
cpu->edx = EDX;
|
|
|
|
|
|
|
|
|
|
cpu->ebp = EBP;
|
|
|
|
|
cpu->esi = ESI;
|
|
|
|
|
cpu->edi = EDI;
|
|
|
|
|
cpu->esp = ESP;
|
|
|
|
|
|
|
|
|
|
cpu->eflags = dbg_get_eflags();
|
2002-09-13 04:15:23 +04:00
|
|
|
cpu->eip = EIP;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
cpu->cs.sel = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
|
|
|
|
cpu->cs.des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache);
|
|
|
|
|
cpu->cs.des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache);
|
|
|
|
|
cpu->cs.valid = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid;
|
|
|
|
|
|
|
|
|
|
cpu->ss.sel = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
|
|
|
|
|
cpu->ss.des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache);
|
|
|
|
|
cpu->ss.des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache);
|
|
|
|
|
cpu->ss.valid = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid;
|
|
|
|
|
|
|
|
|
|
cpu->ds.sel = BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value;
|
|
|
|
|
cpu->ds.des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache);
|
|
|
|
|
cpu->ds.des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache);
|
|
|
|
|
cpu->ds.valid = BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid;
|
|
|
|
|
|
|
|
|
|
cpu->es.sel = BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value;
|
|
|
|
|
cpu->es.des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache);
|
|
|
|
|
cpu->es.des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache);
|
|
|
|
|
cpu->es.valid = BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid;
|
|
|
|
|
|
|
|
|
|
cpu->fs.sel = BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value;
|
|
|
|
|
cpu->fs.des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache);
|
|
|
|
|
cpu->fs.des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache);
|
|
|
|
|
cpu->fs.valid = BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid;
|
|
|
|
|
|
|
|
|
|
cpu->gs.sel = BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value;
|
|
|
|
|
cpu->gs.des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache);
|
|
|
|
|
cpu->gs.des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache);
|
|
|
|
|
cpu->gs.valid = BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid;
|
|
|
|
|
|
|
|
|
|
cpu->ldtr.sel = BX_CPU_THIS_PTR ldtr.selector.value;
|
|
|
|
|
cpu->ldtr.des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR ldtr.cache);
|
|
|
|
|
cpu->ldtr.des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR ldtr.cache);
|
|
|
|
|
cpu->ldtr.valid = BX_CPU_THIS_PTR ldtr.cache.valid;
|
|
|
|
|
|
|
|
|
|
cpu->tr.sel = BX_CPU_THIS_PTR tr.selector.value;
|
|
|
|
|
cpu->tr.des_l = dbg_get_descriptor_l(&BX_CPU_THIS_PTR tr.cache);
|
|
|
|
|
cpu->tr.des_h = dbg_get_descriptor_h(&BX_CPU_THIS_PTR tr.cache);
|
|
|
|
|
cpu->tr.valid = BX_CPU_THIS_PTR tr.cache.valid;
|
|
|
|
|
|
|
|
|
|
cpu->gdtr.base = BX_CPU_THIS_PTR gdtr.base;
|
|
|
|
|
cpu->gdtr.limit = BX_CPU_THIS_PTR gdtr.limit;
|
|
|
|
|
|
|
|
|
|
cpu->idtr.base = BX_CPU_THIS_PTR idtr.base;
|
|
|
|
|
cpu->idtr.limit = BX_CPU_THIS_PTR idtr.limit;
|
|
|
|
|
|
|
|
|
|
cpu->dr0 = BX_CPU_THIS_PTR dr0;
|
|
|
|
|
cpu->dr1 = BX_CPU_THIS_PTR dr1;
|
|
|
|
|
cpu->dr2 = BX_CPU_THIS_PTR dr2;
|
|
|
|
|
cpu->dr3 = BX_CPU_THIS_PTR dr3;
|
|
|
|
|
cpu->dr6 = BX_CPU_THIS_PTR dr6;
|
|
|
|
|
cpu->dr7 = BX_CPU_THIS_PTR dr7;
|
|
|
|
|
|
|
|
|
|
cpu->tr3 = 0;
|
|
|
|
|
cpu->tr4 = 0;
|
|
|
|
|
cpu->tr5 = 0;
|
|
|
|
|
cpu->tr6 = 0;
|
|
|
|
|
cpu->tr7 = 0;
|
|
|
|
|
|
2002-10-27 18:15:12 +03:00
|
|
|
#if BX_CPU_LEVEL >= 2
|
2001-04-10 05:04:59 +04:00
|
|
|
// cr0:32=pg,cd,nw,am,wp,ne,ts,em,mp,pe
|
|
|
|
|
cpu->cr0 = BX_CPU_THIS_PTR cr0.val32;
|
|
|
|
|
cpu->cr1 = 0;
|
|
|
|
|
cpu->cr2 = BX_CPU_THIS_PTR cr2;
|
|
|
|
|
cpu->cr3 = BX_CPU_THIS_PTR cr3;
|
2002-10-27 18:15:12 +03:00
|
|
|
#endif
|
|
|
|
|
#if BX_CPU_LEVEL >= 4
|
2002-09-14 23:21:41 +04:00
|
|
|
cpu->cr4 = BX_CPU_THIS_PTR cr4.getRegister();
|
2002-10-27 18:15:12 +03:00
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
cpu->inhibit_mask = BX_CPU_THIS_PTR inhibit_mask;
|
|
|
|
|
|
|
|
|
|
return(1);
|
|
|
|
|
}
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
|
// returns 1=OK, 0=Error
|
|
|
|
|
Bit32u val;
|
|
|
|
|
Bit32u type;
|
|
|
|
|
|
|
|
|
|
// =================================================
|
|
|
|
|
// Do checks first, before setting any CPU registers
|
|
|
|
|
// =================================================
|
|
|
|
|
|
|
|
|
|
// CS, SS, DS, ES, FS, GS descriptor checks
|
|
|
|
|
if (!cpu->cs.valid) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: CS not valid" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( (cpu->cs.des_h & 0x1000) == 0 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: CS not application type" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( (cpu->cs.des_h & 0x0800) == 0 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: CS not executable" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (!cpu->ss.valid) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: SS not valid" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( (cpu->ss.des_h & 0x1000) == 0 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: SS not application type" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (cpu->ds.valid) {
|
|
|
|
|
if ( (cpu->ds.des_h & 0x1000) == 0 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: DS not application type" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (cpu->es.valid) {
|
|
|
|
|
if ( (cpu->es.des_h & 0x1000) == 0 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: ES not application type" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (cpu->fs.valid) {
|
|
|
|
|
if ( (cpu->fs.des_h & 0x1000) == 0 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: FS not application type" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (cpu->gs.valid) {
|
|
|
|
|
if ( (cpu->gs.des_h & 0x1000) == 0 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: GS not application type" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (cpu->ldtr.valid) {
|
|
|
|
|
if ( cpu->ldtr.des_h & 0x1000 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: LDTR not system type" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( ((cpu->ldtr.des_h >> 8) & 0x0f) != 2 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: LDTR descriptor type not LDT" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
if (cpu->tr.valid) {
|
|
|
|
|
if ( cpu->tr.des_h & 0x1000 ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: TR not system type"));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
type = (cpu->tr.des_h >> 8) & 0x0f;
|
|
|
|
|
|
|
|
|
|
if ( (type != 1) && (type != 9) ) {
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_ERROR(( "Error: TR descriptor type not TSS" ));
|
2001-04-10 05:04:59 +04:00
|
|
|
return(0); // error
|
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
// =============
|
|
|
|
|
// end of checks
|
|
|
|
|
// =============
|
|
|
|
|
|
|
|
|
|
EAX = cpu->eax;
|
|
|
|
|
EBX = cpu->ebx;
|
|
|
|
|
ECX = cpu->ecx;
|
|
|
|
|
EDX = cpu->edx;
|
|
|
|
|
EBP = cpu->ebp;
|
|
|
|
|
ESI = cpu->esi;
|
|
|
|
|
EDI = cpu->edi;
|
|
|
|
|
ESP = cpu->esp;
|
|
|
|
|
|
|
|
|
|
// eflags
|
|
|
|
|
val = cpu->eflags;
|
|
|
|
|
BX_CPU_THIS_PTR set_CF(val & 0x01); val >>= 2;
|
|
|
|
|
BX_CPU_THIS_PTR set_PF(val & 0x01); val >>= 2;
|
|
|
|
|
BX_CPU_THIS_PTR set_AF(val & 0x01); val >>= 2;
|
|
|
|
|
BX_CPU_THIS_PTR set_ZF(val & 0x01); val >>= 1;
|
|
|
|
|
BX_CPU_THIS_PTR set_SF(val & 0x01); val >>= 1;
|
2002-09-12 22:10:46 +04:00
|
|
|
BX_CPU_THIS_PTR set_TF (val & 0x01); val >>= 1;
|
|
|
|
|
BX_CPU_THIS_PTR set_IF (val & 0x01); val >>= 1;
|
|
|
|
|
BX_CPU_THIS_PTR set_DF (val & 0x01); val >>= 1;
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR set_OF(val & 0x01); val >>= 1;
|
2002-09-12 22:10:46 +04:00
|
|
|
BX_CPU_THIS_PTR set_IOPL (val & 0x03); val >>= 2;
|
|
|
|
|
BX_CPU_THIS_PTR set_NT (val & 0x01); val >>= 2;
|
|
|
|
|
BX_CPU_THIS_PTR set_RF (val & 0x01); val >>= 1;
|
|
|
|
|
BX_CPU_THIS_PTR set_VM (val & 0x01); val >>= 1;
|
2001-04-10 05:04:59 +04:00
|
|
|
#if BX_CPU_LEVEL >= 4
|
2002-09-12 22:10:46 +04:00
|
|
|
BX_CPU_THIS_PTR set_AC (val & 0x01); val >>= 1;
|
- the debugger was broken by recent changes in the cpu flags. To provide
a consistent way of accessing these flags that works both inside and
outside the BX_CPU class, I added inline accessor methods for each
flag: assert_FLAG(), clear_FLAG(), set_FLAG(value), and get_FLAG ()
that returns its value. I use assert to mean "set the value to one"
to avoid confusion, since there's also a set method that takes a value.
- the eflags access macros (e.g. GetEFlagsDFLogical, ClearEFlagsTF) are
now defined in terms of the inline accessors. In most cases it will
result in the same code anyway. The major advantage of the accesors
is that they can be used from inside or outside the BX_CPU object, while
the macros can only be used from inside.
- since almost all eflags were stored in val32 now, I went ahead and
removed the if_, rf, and vm fields. Now the val32 bit is the
"official" value for these flags, and they have accessors just like
everything else.
- init.cc: move the registration of registers until after they have been
initialized so that the initial value of each parameter is correct.
Modified files:
debug/dbg_main.cc cpu/cpu.h cpu/debugstuff.cc cpu/flag_ctrl.cc
cpu/flag_ctrl_pro.cc cpu/init.cc
2002-09-11 07:55:22 +04:00
|
|
|
//BX_CPU_THIS_PTR eflags.set_VIF (val & 0x01);
|
2001-04-10 05:04:59 +04:00
|
|
|
val >>= 1;
|
- the debugger was broken by recent changes in the cpu flags. To provide
a consistent way of accessing these flags that works both inside and
outside the BX_CPU class, I added inline accessor methods for each
flag: assert_FLAG(), clear_FLAG(), set_FLAG(value), and get_FLAG ()
that returns its value. I use assert to mean "set the value to one"
to avoid confusion, since there's also a set method that takes a value.
- the eflags access macros (e.g. GetEFlagsDFLogical, ClearEFlagsTF) are
now defined in terms of the inline accessors. In most cases it will
result in the same code anyway. The major advantage of the accesors
is that they can be used from inside or outside the BX_CPU object, while
the macros can only be used from inside.
- since almost all eflags were stored in val32 now, I went ahead and
removed the if_, rf, and vm fields. Now the val32 bit is the
"official" value for these flags, and they have accessors just like
everything else.
- init.cc: move the registration of registers until after they have been
initialized so that the initial value of each parameter is correct.
Modified files:
debug/dbg_main.cc cpu/cpu.h cpu/debugstuff.cc cpu/flag_ctrl.cc
cpu/flag_ctrl_pro.cc cpu/init.cc
2002-09-11 07:55:22 +04:00
|
|
|
//BX_CPU_THIS_PTR eflags.set_VIP (val & 0x01);
|
2001-04-10 05:04:59 +04:00
|
|
|
val >>= 1;
|
2002-09-12 22:10:46 +04:00
|
|
|
BX_CPU_THIS_PTR set_ID (val & 0x01);
|
2001-04-10 05:04:59 +04:00
|
|
|
#endif
|
|
|
|
|
|
2002-09-13 04:15:23 +04:00
|
|
|
EIP = cpu->eip;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
// CS:
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value = cpu->cs.sel;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index = cpu->cs.sel >> 3;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti = (cpu->cs.sel >> 2) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl = cpu->cs.sel & 0x03;
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = cpu->cs.valid;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = (cpu->cs.des_h >> 15) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = (cpu->cs.des_h >> 13) & 0x03;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = (cpu->cs.des_h >> 12) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = (cpu->cs.des_h >> 8) & 0x0f;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = (cpu->cs.des_h >> 11) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = (cpu->cs.des_h >> 10) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = (cpu->cs.des_h >> 9) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = (cpu->cs.des_h >> 8) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = (cpu->cs.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base |= (cpu->cs.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base |= (cpu->cs.des_h & 0xff000000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = (cpu->cs.des_l & 0xffff);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit |= (cpu->cs.des_h & 0x000f0000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = (cpu->cs.des_h >> 23) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = (cpu->cs.des_h >> 22) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = (cpu->cs.des_h >> 20) & 0x01;
|
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g)
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled =
|
|
|
|
|
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit << 12) | 0x0fff;
|
|
|
|
|
else
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled =
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit;
|
2001-10-03 00:01:29 +04:00
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
// SS:
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = cpu->ss.sel;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index = cpu->ss.sel >> 3;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti = (cpu->ss.sel >> 2) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = cpu->ss.sel & 0x03;
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = cpu->ss.valid;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = (cpu->ss.des_h >> 15) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = (cpu->ss.des_h >> 13) & 0x03;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = (cpu->ss.des_h >> 12) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = (cpu->ss.des_h >> 8) & 0x0f;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = (cpu->ss.des_h >> 11) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = (cpu->ss.des_h >> 10) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = (cpu->ss.des_h >> 9) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = (cpu->ss.des_h >> 8) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = (cpu->ss.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base |= (cpu->ss.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base |= (cpu->ss.des_h & 0xff000000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = (cpu->ss.des_l & 0xffff);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit |= (cpu->ss.des_h & 0x000f0000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = (cpu->ss.des_h >> 23) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = (cpu->ss.des_h >> 22) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = (cpu->ss.des_h >> 20) & 0x01;
|
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g)
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled =
|
|
|
|
|
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit << 12) | 0x0fff;
|
|
|
|
|
else
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled =
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit;
|
2001-10-03 00:01:29 +04:00
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
// DS:
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = cpu->ds.sel;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.index = cpu->ds.sel >> 3;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.ti = (cpu->ds.sel >> 2) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.rpl = cpu->ds.sel & 0x03;
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = cpu->ds.valid;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.p = (cpu->ds.des_h >> 15) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.dpl = (cpu->ds.des_h >> 13) & 0x03;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment = (cpu->ds.des_h >> 12) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.type = (cpu->ds.des_h >> 8) & 0x0f;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.executable = (cpu->ds.des_h >> 11) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.c_ed = (cpu->ds.des_h >> 10) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.r_w = (cpu->ds.des_h >> 9) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.a = (cpu->ds.des_h >> 8) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base = (cpu->ds.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base |= (cpu->ds.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base |= (cpu->ds.des_h & 0xff000000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit = (cpu->ds.des_l & 0xffff);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit |= (cpu->ds.des_h & 0x000f0000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.g = (cpu->ds.des_h >> 23) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.d_b = (cpu->ds.des_h >> 22) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.avl = (cpu->ds.des_h >> 20) & 0x01;
|
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.g)
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled =
|
|
|
|
|
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit << 12) | 0x0fff;
|
|
|
|
|
else
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled =
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit;
|
2001-10-03 00:01:29 +04:00
|
|
|
|
|
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
// ES:
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = cpu->es.sel;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.index = cpu->es.sel >> 3;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.ti = (cpu->es.sel >> 2) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.rpl = cpu->es.sel & 0x03;
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = cpu->es.valid;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.p = (cpu->es.des_h >> 15) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.dpl = (cpu->es.des_h >> 13) & 0x03;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.segment = (cpu->es.des_h >> 12) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.type = (cpu->es.des_h >> 8) & 0x0f;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.executable = (cpu->es.des_h >> 11) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.c_ed = (cpu->es.des_h >> 10) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.r_w = (cpu->es.des_h >> 9) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.a = (cpu->es.des_h >> 8) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base = (cpu->es.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base |= (cpu->es.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base |= (cpu->es.des_h & 0xff000000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit = (cpu->es.des_l & 0xffff);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit |= (cpu->es.des_h & 0x000f0000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.g = (cpu->es.des_h >> 23) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.d_b = (cpu->es.des_h >> 22) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.avl = (cpu->es.des_h >> 20) & 0x01;
|
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.g)
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit_scaled =
|
|
|
|
|
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit << 12) | 0x0fff;
|
|
|
|
|
else
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit_scaled =
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit;
|
2001-10-03 00:01:29 +04:00
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
// FS:
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = cpu->fs.sel;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.index = cpu->fs.sel >> 3;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.ti = (cpu->fs.sel >> 2) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.rpl = cpu->fs.sel & 0x03;
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = cpu->fs.valid;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.p = (cpu->fs.des_h >> 15) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.dpl = (cpu->fs.des_h >> 13) & 0x03;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.segment = (cpu->fs.des_h >> 12) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.type = (cpu->fs.des_h >> 8) & 0x0f;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.executable = (cpu->fs.des_h >> 11) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.c_ed = (cpu->fs.des_h >> 10) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.r_w = (cpu->fs.des_h >> 9) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.a = (cpu->fs.des_h >> 8) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base = (cpu->fs.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base |= (cpu->fs.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base |= (cpu->fs.des_h & 0xff000000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit = (cpu->fs.des_l & 0xffff);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit |= (cpu->fs.des_h & 0x000f0000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.g = (cpu->fs.des_h >> 23) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.d_b = (cpu->fs.des_h >> 22) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.avl = (cpu->fs.des_h >> 20) & 0x01;
|
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.g)
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit_scaled =
|
|
|
|
|
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit << 12) | 0x0fff;
|
|
|
|
|
else
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit_scaled =
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit;
|
2001-10-03 00:01:29 +04:00
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
// GS:
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = cpu->gs.sel;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.index = cpu->gs.sel >> 3;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.ti = (cpu->gs.sel >> 2) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.rpl = cpu->gs.sel & 0x03;
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = cpu->gs.valid;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.p = (cpu->gs.des_h >> 15) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.dpl = (cpu->gs.des_h >> 13) & 0x03;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.segment = (cpu->gs.des_h >> 12) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.type = (cpu->gs.des_h >> 8) & 0x0f;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.executable = (cpu->gs.des_h >> 11) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.c_ed = (cpu->gs.des_h >> 10) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.r_w = (cpu->gs.des_h >> 9) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.a = (cpu->gs.des_h >> 8) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base = (cpu->gs.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base |= (cpu->gs.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base |= (cpu->gs.des_h & 0xff000000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit = (cpu->gs.des_l & 0xffff);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit |= (cpu->gs.des_h & 0x000f0000);
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.g = (cpu->gs.des_h >> 23) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.d_b = (cpu->gs.des_h >> 22) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.avl = (cpu->gs.des_h >> 20) & 0x01;
|
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.g)
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit_scaled =
|
|
|
|
|
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit << 12) | 0x0fff;
|
|
|
|
|
else
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit_scaled =
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit;
|
|
|
|
|
|
|
|
|
|
// LDTR:
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.selector.value = cpu->ldtr.sel;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.selector.index = cpu->ldtr.sel >> 3;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.selector.ti = (cpu->ldtr.sel >> 2) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.selector.rpl = cpu->ldtr.sel & 0x03;
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.valid = cpu->ldtr.valid;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.p = (cpu->ldtr.des_h >> 15) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.dpl = (cpu->ldtr.des_h >> 13) & 0x03;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.segment = (cpu->ldtr.des_h >> 12) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.type = (cpu->ldtr.des_h >> 8) & 0x0f;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base = (cpu->ldtr.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base |= (cpu->ldtr.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base |= (cpu->ldtr.des_h & 0xff000000);
|
|
|
|
|
BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit = (cpu->ldtr.des_l & 0xffff);
|
|
|
|
|
|
|
|
|
|
// TR
|
|
|
|
|
type = (cpu->tr.des_h >> 8) & 0x0f;
|
2001-10-10 01:15:14 +04:00
|
|
|
type &= ~2; // never allow busy bit in tr.cache.type
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR tr.selector.value = cpu->tr.sel;
|
|
|
|
|
BX_CPU_THIS_PTR tr.selector.index = cpu->tr.sel >> 3;
|
|
|
|
|
BX_CPU_THIS_PTR tr.selector.ti = (cpu->tr.sel >> 2) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR tr.selector.rpl = cpu->tr.sel & 0x03;
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.valid = cpu->tr.valid;
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.p = (cpu->tr.des_h >> 15) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.dpl = (cpu->tr.des_h >> 13) & 0x03;
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.segment = (cpu->tr.des_h >> 12) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.type = type;
|
|
|
|
|
if (type == 1) { // 286 TSS
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss286.base = (cpu->tr.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss286.base |= (cpu->tr.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss286.limit = (cpu->tr.des_l & 0xffff);
|
|
|
|
|
}
|
|
|
|
|
else { // type == 9, 386 TSS
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss386.base = (cpu->tr.des_l >> 16);
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss386.base |= (cpu->tr.des_h & 0xff) << 16;
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss386.base |= (cpu->tr.des_h & 0xff000000);
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss386.limit = (cpu->tr.des_l & 0xffff);
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss386.limit |= (cpu->tr.des_h & 0x000f0000);
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss386.g = (cpu->tr.des_h >> 23) & 0x01;
|
|
|
|
|
BX_CPU_THIS_PTR tr.cache.u.tss386.avl = (cpu->tr.des_h >> 20) & 0x01;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// gdtr
|
|
|
|
|
BX_CPU_THIS_PTR gdtr.base = cpu->gdtr.base;
|
|
|
|
|
BX_CPU_THIS_PTR gdtr.limit = cpu->gdtr.limit;
|
|
|
|
|
|
|
|
|
|
// idtr
|
|
|
|
|
BX_CPU_THIS_PTR idtr.base = cpu->idtr.base;
|
|
|
|
|
BX_CPU_THIS_PTR idtr.limit = cpu->idtr.limit;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR dr0 = cpu->dr0;
|
|
|
|
|
BX_CPU_THIS_PTR dr1 = cpu->dr1;
|
|
|
|
|
BX_CPU_THIS_PTR dr2 = cpu->dr2;
|
|
|
|
|
BX_CPU_THIS_PTR dr3 = cpu->dr3;
|
|
|
|
|
BX_CPU_THIS_PTR dr6 = cpu->dr6;
|
|
|
|
|
BX_CPU_THIS_PTR dr7 = cpu->dr7;
|
|
|
|
|
|
|
|
|
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// BX_CPU_THIS_PTR tr3 = cpu->tr3;
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// BX_CPU_THIS_PTR tr4 = cpu->tr4;
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// BX_CPU_THIS_PTR tr5 = cpu->tr5;
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// BX_CPU_THIS_PTR tr6 = cpu->tr6;
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// BX_CPU_THIS_PTR tr7 = cpu->tr7;
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2002-10-27 18:15:12 +03:00
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#if BX_CPU_LEVEL >= 2
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2001-04-10 05:04:59 +04:00
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// cr0, cr1, cr2, cr3, cr4
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SetCR0(cpu->cr0);
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BX_CPU_THIS_PTR cr1 = cpu->cr1;
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BX_CPU_THIS_PTR cr2 = cpu->cr2;
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BX_CPU_THIS_PTR cr3 = cpu->cr3;
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2002-10-27 18:15:12 +03:00
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#endif
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#if BX_CPU_LEVEL >= 4
|
2002-09-14 23:21:41 +04:00
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BX_CPU_THIS_PTR cr4.setRegister(cpu->cr4);
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2001-04-10 05:04:59 +04:00
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#endif
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BX_CPU_THIS_PTR inhibit_mask = cpu->inhibit_mask;
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//
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// flush cached items, prefetch, paging, etc
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//
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BX_CPU_THIS_PTR CR3_change(cpu->cr3);
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BX_CPU_THIS_PTR invalidate_prefetch_q();
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BX_CPU_THIS_PTR async_event = 1;
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return(1);
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}
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|
#if BX_SIM_ID == 0
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# define BX_DBG_NULL_CALLBACK bx_dbg_null_callback0
|
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#else
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# define BX_DBG_NULL_CALLBACK bx_dbg_null_callback1
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|
#endif
|
2005-03-28 22:19:02 +04:00
|
|
|
void BX_DBG_NULL_CALLBACK(unsigned val)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
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|
|
|
// bochs uses the pc_system variables, so this function is
|
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|
|
// a stub for notification by the debugger, that a change
|
|
|
|
|
// occurred.
|
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|
UNUSED(val);
|
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}
|
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|
|
void
|
|
|
|
|
#if BX_SIM_ID == 0
|
|
|
|
|
bx_dbg_init_cpu_mem_env0(bx_dbg_callback_t *callback, int argc, char *argv[])
|
|
|
|
|
#else
|
|
|
|
|
bx_dbg_init_cpu_mem_env1(bx_dbg_callback_t *callback, int argc, char *argv[])
|
|
|
|
|
#endif
|
|
|
|
|
{
|
|
|
|
|
UNUSED(argc);
|
|
|
|
|
UNUSED(argv);
|
|
|
|
|
|
2001-05-23 12:16:07 +04:00
|
|
|
#if 0
|
2002-10-25 16:36:44 +04:00
|
|
|
#ifdef __GNUC__
|
2001-05-23 12:16:07 +04:00
|
|
|
#warning hardcoding BX_CPU_THIS_PTR mem[0] and cpu[0]
|
2002-10-25 16:36:44 +04:00
|
|
|
#endif
|
2001-05-23 12:16:07 +04:00
|
|
|
callback->setphymem = BX_MEM(0)->dbg_set_mem;
|
|
|
|
|
callback->getphymem = BX_MEM(0)->dbg_fetch_mem;
|
|
|
|
|
callback->xlate_linear2phy = BX_CPU(0)->dbg_xlate_linear2phy;
|
|
|
|
|
callback->set_reg = BX_CPU(0)->dbg_set_reg;
|
|
|
|
|
callback->get_reg = BX_CPU(0)->dbg_get_reg;
|
|
|
|
|
callback->get_sreg = BX_CPU(0)->dbg_get_sreg;
|
|
|
|
|
callback->get_cpu = BX_CPU(0)->dbg_get_cpu;
|
|
|
|
|
callback->set_cpu = BX_CPU(0)->dbg_set_cpu;
|
|
|
|
|
callback->dirty_page_tbl_size = sizeof(BX_MEM(0)->dbg_dirty_pages);
|
|
|
|
|
callback->dirty_page_tbl = BX_MEM(0)->dbg_dirty_pages;
|
|
|
|
|
callback->atexit = BX_CPU(0)->atexit;
|
|
|
|
|
callback->query_pending = BX_CPU(0)->dbg_query_pending;
|
|
|
|
|
callback->execute = BX_CPU(0)->cpu_loop;
|
|
|
|
|
callback->take_irq = BX_CPU(0)->dbg_take_irq;
|
|
|
|
|
callback->take_dma = BX_CPU(0)->dbg_take_dma;
|
|
|
|
|
callback->reset_cpu = BX_CPU(0)->reset;
|
|
|
|
|
callback->init_mem = BX_MEM(0)->init_memory;
|
|
|
|
|
callback->load_ROM = BX_MEM(0)->load_ROM;
|
2001-04-10 05:04:59 +04:00
|
|
|
callback->set_A20 = NULL;
|
|
|
|
|
callback->set_NMI = BX_DBG_NULL_CALLBACK;
|
|
|
|
|
callback->set_RESET = BX_DBG_NULL_CALLBACK;
|
2001-05-23 12:16:07 +04:00
|
|
|
callback->set_INTR = BX_CPU(0)->set_INTR;
|
|
|
|
|
callback->force_interrupt = BX_CPU(0)->dbg_force_interrupt;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
|
#if BX_INSTRUMENTATION
|
|
|
|
|
callback->instr_start = bx_instr_start;
|
|
|
|
|
callback->instr_stop = bx_instr_stop;
|
|
|
|
|
callback->instr_reset = bx_instr_reset;
|
|
|
|
|
callback->instr_print = bx_instr_print;
|
|
|
|
|
#endif
|
|
|
|
|
#if BX_USE_LOADER
|
|
|
|
|
callback->loader = bx_dbg_loader;
|
|
|
|
|
#endif
|
2001-05-23 12:16:07 +04:00
|
|
|
callback->crc32 = BX_MEM(0)->dbg_crc32;
|
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif // #if BX_DEBUGGER
|
|
|
|
|
|
2005-03-28 22:19:02 +04:00
|
|
|
void BX_CPU_C::atexit(void)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2001-05-23 12:16:07 +04:00
|
|
|
debug(BX_CPU_THIS_PTR prev_eip);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|