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Removed duplicated definition of BX_SEG_REGS

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This commit is contained in:
Stanislav Shwartsman 2002-10-16 22:10:07 +00:00
parent ee0ec5908e
commit c5f0ef8c76
8 changed files with 89 additions and 96 deletions
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8
bochs/cpu/cpu.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.65 2002-10-07 22:51:56 kevinlawton Exp $
// $Id: cpu.cc,v 1.66 2002-10-16 22:10:02 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -306,7 +306,7 @@ BX_CPU_C::cpu_loop(Bit32s max_instr_count)
BX_CPU_THIS_PTR prev_eip = RIP; // commit new EIP
BX_CPU_THIS_PTR prev_esp = RSP; // commit new ESP
#ifdef REGISTER_IADDR
REGISTER_IADDR(RIP + BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base);
REGISTER_IADDR(RIP + BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base);
#endif
BX_TICK1_IF_SINGLE_PROCESSOR();
@ -381,7 +381,7 @@ repeat_loop:
// shouldn't get here from above
repeat_not_done:
#ifdef REGISTER_IADDR
REGISTER_IADDR(RIP + BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base);
REGISTER_IADDR(RIP + BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base);
#endif
BX_INSTR_REPEAT_ITERATION(CPU_ID);
@ -405,7 +405,7 @@ repeat_done:
BX_CPU_THIS_PTR prev_eip = RIP; // commit new EIP
BX_CPU_THIS_PTR prev_esp = RSP; // commit new ESP
#ifdef REGISTER_IADDR
REGISTER_IADDR(RIP + BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base);
REGISTER_IADDR(RIP + BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base);
#endif
BX_INSTR_REPEAT_ITERATION(CPU_ID);

9
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.104 2002-10-16 17:37:33 sshwarts Exp $
// $Id: cpu.h,v 1.105 2002-10-16 22:10:03 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -32,13 +32,6 @@
#include "cpu/lazy_flags.h"
#define BX_SREG_ES 0
#define BX_SREG_CS 1
#define BX_SREG_SS 2
#define BX_SREG_DS 3
#define BX_SREG_FS 4
#define BX_SREG_GS 5
// segment register encoding
#define BX_SEG_REG_ES 0
#define BX_SEG_REG_CS 1

14
bochs/cpu/debugstuff.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: debugstuff.cc,v 1.22 2002-10-04 17:04:32 kevinlawton Exp $
// $Id: debugstuff.cc,v 1.23 2002-10-16 22:10:05 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -127,18 +127,18 @@ BX_CPU_C::debug(Bit32u offset)
#if 0
/* (mch) Hack to display the area round EIP and prev_EIP */
char buf[100];
sprintf(buf, "%04x:%08x ", BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.value, EIP);
sprintf(buf, "%04x:%08x ", BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
for (int i = 0; i < 8; i++) {
Bit8u data;
BX_CPU_THIS_PTR read_virtual_byte(BX_SREG_CS, EIP + i, &data);
BX_CPU_THIS_PTR read_virtual_byte(BX_SEG_REG_CS, EIP + i, &data);
sprintf(buf+strlen(buf), "%02x ", data);
}
BX_INFO((buf));
sprintf(buf, "%04x:%08x ", BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.value, BX_CPU_THIS_PTR prev_eip);
sprintf(buf, "%04x:%08x ", BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR prev_eip);
for (int i = 0; i < 8; i++) {
Bit8u data;
BX_CPU_THIS_PTR read_virtual_byte(BX_SREG_CS, BX_CPU_THIS_PTR prev_eip + i, &data);
BX_CPU_THIS_PTR read_virtual_byte(BX_SEG_REG_CS, BX_CPU_THIS_PTR prev_eip + i, &data);
sprintf(buf+strlen(buf), "%02x ", data);
}
BX_INFO((buf));
@ -1000,9 +1000,9 @@ BX_CPU_C::atexit(void)
else if (v8086_mode()) BX_INFO(("v8086 mode"));
else BX_INFO(("real mode"));
BX_INFO(("CS.d_b = %u bit",
BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.d_b ? 32 : 16));
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b ? 32 : 16));
BX_INFO(("SS.d_b = %u bit",
BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.d_b ? 32 : 16));
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b ? 32 : 16));
debug(BX_CPU_THIS_PTR prev_eip);
}

4
bochs/cpu/io.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: io.cc,v 1.19 2002-09-24 04:43:59 kevinlawton Exp $
// $Id: io.cc,v 1.20 2002-10-16 22:10:06 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -182,7 +182,7 @@ BX_CPU_C::INSW_YvDX(bxInstruction_c *i)
bx_segment_reg_t *dstSegPtr;
int pointerDelta;
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SREG_ES];
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
// Do segment checks for the 1st word. We do not want to
// trip an exception beyond this, because the address would

16
bochs/cpu/segment_ctrl_pro.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: segment_ctrl_pro.cc,v 1.20 2002-10-04 17:04:33 kevinlawton Exp $
// $Id: segment_ctrl_pro.cc,v 1.21 2002-10-16 22:10:06 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -49,7 +49,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
seg->cache.p = 1;
seg->cache.dpl = 3;
seg->cache.segment = 1; /* regular segment */
if (seg == &BX_CPU_THIS_PTR sregs[BX_SREG_CS]) {
if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
seg->cache.u.segment.executable = 1; /* code segment */
#if BX_SupportICache
BX_CPU_THIS_PTR iCache.fetchModeMask =
@ -77,7 +77,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
#if BX_CPU_LEVEL >= 2
if (protected_mode()) {
if (seg == &BX_CPU_THIS_PTR sregs[BX_SREG_SS]) {
if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS]) {
Bit16u index;
Bit8u ti;
Bit8u rpl;
@ -181,11 +181,11 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
return;
}
else if ( (seg==&BX_CPU_THIS_PTR sregs[BX_SREG_DS]) ||
(seg==&BX_CPU_THIS_PTR sregs[BX_SREG_ES])
else if ( (seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS]) ||
(seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES])
#if BX_CPU_LEVEL >= 3
|| (seg==&BX_CPU_THIS_PTR sregs[BX_SREG_FS]) ||
(seg==&BX_CPU_THIS_PTR sregs[BX_SREG_GS])
|| (seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS]) ||
(seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS])
#endif
) {
Bit16u index;
@ -311,7 +311,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
/* something about honoring previous values */
/* ??? */
if (seg == &BX_CPU_THIS_PTR sregs[BX_SREG_CS]) {
if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value = new_value;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;

10
bochs/cpu/string.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: string.cc,v 1.19 2002-10-07 22:51:58 kevinlawton Exp $
// $Id: string.cc,v 1.20 2002-10-16 22:10:06 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -156,7 +156,7 @@ BX_CPU_C::MOVSB_XbYb(bxInstruction_c *i)
Bit32u paddrDst, paddrSrc;
srcSegPtr = &BX_CPU_THIS_PTR sregs[seg];
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SREG_ES];
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
// Do segment checks for the 1st word. We do not want to
// trip an exception beyond this, because the address would
@ -468,7 +468,7 @@ BX_CPU_C::MOVSW_XvYv(bxInstruction_c *i)
Bit32u paddrDst, paddrSrc;
srcSegPtr = &BX_CPU_THIS_PTR sregs[seg];
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SREG_ES];
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
// Do segment checks for the 1st word. We do not want to
// trip an exception beyond this, because the address would
@ -726,7 +726,7 @@ doIncr32:
Bit32u paddrDst, paddrSrc;
srcSegPtr = &BX_CPU_THIS_PTR sregs[seg];
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SREG_ES];
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
// Do segment checks for the 1st word. We do not want to
// trip an exception beyond this, because the address would
@ -1664,7 +1664,7 @@ BX_CPU_C::STOSB_YbAL(bxInstruction_c *i)
bx_address laddrDst;
Bit32u paddrDst;
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SREG_ES];
dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
// Do segment checks for the 1st word. We do not want to
// trip an exception beyond this, because the address would

12
bochs/debug/dbg_main.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: dbg_main.cc,v 1.76 2002-10-16 21:32:56 bdenney Exp $
// $Id: dbg_main.cc,v 1.77 2002-10-16 22:10:07 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1029,7 +1029,7 @@ bx_dbg_where_command()
dbg_printf ( "'where' only supported in protected mode\n");
return;
}
if (BX_CPU(dbg_cpu)->sregs[BX_SREG_SS].cache.u.segment.base != 0) {
if (BX_CPU(dbg_cpu)->sregs[BX_SEG_REG_SS].cache.u.segment.base != 0) {
dbg_printf ( "non-zero stack base\n");
return;
}
@ -1278,10 +1278,10 @@ void
bx_dbg_print_stack_command(int nwords)
{
// Get linear address for stack top
Bit32u sp = (BX_CPU(dbg_cpu)->sregs[BX_SREG_SS].cache.u.segment.d_b)?
Bit32u sp = (BX_CPU(dbg_cpu)->sregs[BX_SEG_REG_SS].cache.u.segment.d_b)?
BX_CPU(dbg_cpu)->get_ESP ()
: BX_CPU(dbg_cpu)->get_SP ();
Bit32u linear_sp = sp + BX_CPU(dbg_cpu)->sregs[BX_SREG_SS].cache.u.segment.base;
Bit32u linear_sp = sp + BX_CPU(dbg_cpu)->sregs[BX_SEG_REG_SS].cache.u.segment.base;
Bit8u buf[8];
for (int i = 0; i < nwords; i++) {
@ -2180,13 +2180,13 @@ void bx_dbg_disassemble_current (int which_cpu, int print_time)
dbg_printf ( "%04x:%08x (%s): ",
(unsigned) BX_CPU(which_cpu)->guard_found.cs,
(unsigned) BX_CPU(which_cpu)->guard_found.eip,
bx_dbg_symbolic_address((BX_CPU(which_cpu)->cr3) >> 12, BX_CPU(which_cpu)->guard_found.eip, BX_CPU(which_cpu)->sregs[BX_SREG_CS].cache.u.segment.base));
bx_dbg_symbolic_address((BX_CPU(which_cpu)->cr3) >> 12, BX_CPU(which_cpu)->guard_found.eip, BX_CPU(which_cpu)->sregs[BX_SEG_REG_CS].cache.u.segment.base));
}
else {
dbg_printf ( "%04x:%04x (%s): ",
(unsigned) BX_CPU(which_cpu)->guard_found.cs,
(unsigned) BX_CPU(which_cpu)->guard_found.eip,
bx_dbg_symbolic_address_16bit(BX_CPU(which_cpu)->guard_found.eip, BX_CPU(which_cpu)->sregs[BX_SREG_CS].selector.value));
bx_dbg_symbolic_address_16bit(BX_CPU(which_cpu)->guard_found.eip, BX_CPU(which_cpu)->sregs[BX_SEG_REG_CS].selector.value));
}
for (unsigned j=0; j<ilen; j++)
dbg_printf ( "%02x", (unsigned) bx_disasm_ibuf[j]);

112
bochs/patches/patch.sysenterexit-mrieker
View File

@ -231,35 +231,35 @@ diff -u -r1.22 proc_ctrl.cc
+ BX_CPU_THIS_PTR eflags.if_ = 0;
+ BX_CPU_THIS_PTR eflags.rf = 0;
+
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.value = BX_CPU_THIS_PTR sysenter_cs_msr;
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.index = BX_CPU_THIS_PTR sysenter_cs_msr >> 3;
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.rpl = 0;
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.executable = 1; // code segment
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.c_ed = 0; // non-conforming
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.r_w = 1; // readable
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.a = 1; // accessed
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base = 0; // base address
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.g = 1; // 4k granularity
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.d_b = 1; // 32-bit mode
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.avl = 0; // available for use by system
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value = BX_CPU_THIS_PTR sysenter_cs_msr;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index = BX_CPU_THIS_PTR sysenter_cs_msr >> 3;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl = 0;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; // code segment
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; // non-conforming
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; // readable
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; // accessed
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; // 32-bit mode
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
+
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].selector.value = BX_CPU_THIS_PTR sysenter_cs_msr + 8;
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 8) >> 3;
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].selector.rpl = 0;
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.executable = 0; // data segment
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.c_ed = 0; // expand-up
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.r_w = 1; // writeable
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.a = 1; // accessed
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.base = 0; // base address
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.g = 1; // 4k granularity
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.d_b = 1; // 32-bit mode
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.avl = 0; // available for use by system
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = BX_CPU_THIS_PTR sysenter_cs_msr + 8;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 8) >> 3;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = 0;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; // data segment
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; // expand-up
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; // writeable
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; // accessed
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; // 4k granularity
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; // 32-bit mode
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; // available for use by system
+
+ // BX_INFO (("sysenter: old eip %X, esp %x, new eip %x, esp %X, edx %X", BX_CPU_THIS_PTR prev_eip, ESP, BX_CPU_THIS_PTR sysenter_eip_msr, BX_CPU_THIS_PTR sysenter_esp_msr, EDX));
+
@ -292,35 +292,35 @@ diff -u -r1.22 proc_ctrl.cc
+
+ invalidate_prefetch_q ();
+
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.value = (BX_CPU_THIS_PTR sysenter_cs_msr + 16) | 3;
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 16) >> 3;
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].selector.rpl = 3;
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.executable = 1; // code segment
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.c_ed = 0; // non-conforming
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.r_w = 1; // readable
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.a = 1; // accessed
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.base = 0; // base address
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.g = 1; // 4k granularity
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.d_b = 1; // 32-bit mode
+ BX_CPU_THIS_PTR sregs[BX_SREG_CS].cache.u.segment.avl = 0; // available for use by system
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value = (BX_CPU_THIS_PTR sysenter_cs_msr + 16) | 3;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 16) >> 3;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl = 3;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; // code segment
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; // non-conforming
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; // readable
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; // accessed
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; // 32-bit mode
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
+
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].selector.value = (BX_CPU_THIS_PTR sysenter_cs_msr + 24) | 3;
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 24) >> 3;
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].selector.rpl = 3;
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.executable = 0; // data segment
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.c_ed = 0; // expand-up
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.r_w = 1; // writeable
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.a = 1; // accessed
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.base = 0; // base address
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.g = 1; // 4k granularity
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.d_b = 1; // 32-bit mode
+ BX_CPU_THIS_PTR sregs[BX_SREG_SS].cache.u.segment.avl = 0; // available for use by system
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = (BX_CPU_THIS_PTR sysenter_cs_msr + 24) | 3;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 24) >> 3;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = 3;
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; // data segment
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; // expand-up
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; // writeable
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; // accessed
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; // 4k granularity
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; // 32-bit mode
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; // available for use by system
+
+ // BX_INFO (("sysexit: old eip %X, esp %x, new eip %x, esp %X, eax %X", BX_CPU_THIS_PTR prev_eip, ESP, EDX, ECX, EAX));
+