2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2008-08-28 01:57:40 +04:00
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// $Id: stack32.cc,v 1.56 2008-08-27 21:57:40 sshwarts Exp $
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2001-04-10 06:20:02 +04:00
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// Copyright (C) 2001 MandrakeSoft S.A.
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2001-04-10 05:04:59 +04:00
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2007-12-20 21:29:42 +03:00
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/////////////////////////////////////////////////////////////////////////
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2001-04-10 05:04:59 +04:00
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2001-05-24 22:46:34 +04:00
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#define NEED_CPU_REG_SHORTCUTS 1
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2001-04-10 05:04:59 +04:00
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#include "bochs.h"
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2006-03-07 01:03:16 +03:00
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#include "cpu.h"
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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#define LOG_THIS BX_CPU_THIS_PTR
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2001-04-10 05:04:59 +04:00
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2007-11-24 17:22:34 +03:00
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// Make code more tidy with a few macros.
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#if BX_SUPPORT_X86_64==0
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#define RSP ESP
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#endif
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_EdM(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 1;
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BX_CPU_THIS_PTR prev_rsp = RSP;
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2007-12-20 21:29:42 +03:00
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Bit32u val32 = pop_32();
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2001-04-10 05:04:59 +04:00
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2008-02-03 00:46:54 +03:00
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// Note: there is one little weirdism here. It is possible to use
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// ESP in the modrm addressing. If used, the value of ESP after the
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2007-11-20 20:15:33 +03:00
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// pop is used to calculate the address.
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2008-08-08 13:22:49 +04:00
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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2008-04-03 21:56:59 +04:00
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2008-08-08 13:22:49 +04:00
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write_virtual_dword(i->seg(), eaddr, val32);
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 0;
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2007-11-18 21:49:19 +03:00
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}
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_ERX(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-14 00:07:08 +03:00
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push_32(BX_READ_32BIT_REG(i->opcodeReg()));
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2001-04-10 05:04:59 +04:00
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}
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_ERX(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-12-20 21:29:42 +03:00
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BX_WRITE_32BIT_REGZ(i->opcodeReg(), pop_32());
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2001-04-10 05:04:59 +04:00
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}
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH32_CS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-30 11:49:12 +03:00
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH32_DS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-30 11:49:12 +03:00
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH32_ES(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-30 11:49:12 +03:00
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH32_FS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-30 11:49:12 +03:00
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH32_GS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-30 11:49:12 +03:00
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH32_SS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-30 11:49:12 +03:00
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
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2001-04-10 05:04:59 +04:00
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}
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP32_DS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 1;
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BX_CPU_THIS_PTR prev_rsp = RSP;
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2007-12-20 21:29:42 +03:00
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Bit32u ds = pop_32();
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2005-07-31 21:57:27 +04:00
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], (Bit16u) ds);
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 0;
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP32_ES(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 1;
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BX_CPU_THIS_PTR prev_rsp = RSP;
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2007-12-20 21:29:42 +03:00
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Bit32u es = pop_32();
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2005-07-31 21:57:27 +04:00
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], (Bit16u) es);
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 0;
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP32_FS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 1;
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BX_CPU_THIS_PTR prev_rsp = RSP;
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2007-12-20 21:29:42 +03:00
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Bit32u fs = pop_32();
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2005-07-31 21:57:27 +04:00
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], (Bit16u) fs);
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 0;
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP32_GS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 1;
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BX_CPU_THIS_PTR prev_rsp = RSP;
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2007-12-20 21:29:42 +03:00
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Bit32u gs = pop_32();
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2005-07-31 21:57:27 +04:00
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], (Bit16u) gs);
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 0;
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2001-04-10 05:04:59 +04:00
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}
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2004-11-02 19:10:02 +03:00
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP32_SS(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 1;
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BX_CPU_THIS_PTR prev_rsp = RSP;
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2007-12-20 21:29:42 +03:00
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Bit32u ss = pop_32();
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2005-07-31 21:57:27 +04:00
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], (Bit16u) ss);
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2001-04-10 05:04:59 +04:00
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2007-11-24 17:22:34 +03:00
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BX_CPU_THIS_PTR speculative_rsp = 0;
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2001-04-10 05:04:59 +04:00
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// POP SS inhibits interrupts, debug exceptions and single-step
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// trap exceptions until the execution boundary following the
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// next instruction is reached.
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// Same code as MOV_SwEw()
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BX_CPU_THIS_PTR inhibit_mask |=
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BX_INHIBIT_INTERRUPTS | BX_INHIBIT_DEBUG;
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BX_CPU_THIS_PTR async_event = 1;
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}
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_Id(bxInstruction_c *i)
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2007-11-18 21:52:44 +03:00
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{
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push_32(i->Id());
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}
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_EdM(bxInstruction_c *i)
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2007-11-18 21:52:44 +03:00
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{
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2008-08-08 13:22:49 +04:00
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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2008-01-10 22:37:56 +03:00
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2008-08-08 13:22:49 +04:00
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Bit32u op1_32 = read_virtual_dword(i->seg(), eaddr);
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2007-11-18 21:52:44 +03:00
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push_32(op1_32);
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}
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSHAD32(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-03-03 00:03:25 +03:00
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Bit32u temp_ESP = ESP;
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Bit16u temp_SP = SP;
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2001-04-10 05:04:59 +04:00
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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2007-03-03 00:03:25 +03:00
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{
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2008-06-12 23:14:40 +04:00
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP - 4), EAX);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP - 8), ECX);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP - 12), EDX);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP - 16), EBX);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP - 20), temp_ESP);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP - 24), EBP);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP - 28), ESI);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP - 32), EDI);
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2007-03-03 00:03:25 +03:00
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ESP -= 32;
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2005-01-28 23:50:48 +03:00
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}
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2007-03-03 00:03:25 +03:00
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else
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{
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2008-06-12 23:14:40 +04:00
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP - 4), EAX);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP - 8), ECX);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP - 12), EDX);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP - 16), EBX);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP - 20), temp_ESP);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP - 24), EBP);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP - 28), ESI);
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write_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP - 32), EDI);
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2007-03-03 00:03:25 +03:00
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SP -= 32;
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2005-01-28 23:50:48 +03:00
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}
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2001-04-10 05:04:59 +04:00
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}
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2008-03-23 00:29:41 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPAD32(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2008-05-01 00:41:40 +04:00
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Bit32u edi, esi, ebp, ebx, edx, ecx, eax, dummy;
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2001-04-10 05:04:59 +04:00
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2007-03-03 00:03:25 +03:00
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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{
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Bit32u temp_ESP = ESP;
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2008-06-12 23:14:40 +04:00
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edi = read_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP + 0));
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esi = read_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP + 4));
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ebp = read_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP + 8));
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dummy = read_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP + 12));
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ebx = read_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP + 16));
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edx = read_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP + 20));
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ecx = read_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP + 24));
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eax = read_virtual_dword_32(BX_SEG_REG_SS, (Bit32u) (temp_ESP + 28));
|
2007-03-03 00:03:25 +03:00
|
|
|
ESP += 32;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
Bit16u temp_SP = SP;
|
2008-06-12 23:14:40 +04:00
|
|
|
edi = read_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP + 0));
|
|
|
|
esi = read_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP + 4));
|
|
|
|
ebp = read_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP + 8));
|
|
|
|
dummy = read_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP + 12));
|
|
|
|
ebx = read_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP + 16));
|
|
|
|
edx = read_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP + 20));
|
|
|
|
ecx = read_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP + 24));
|
|
|
|
eax = read_virtual_dword_32(BX_SEG_REG_SS, (Bit16u) (temp_SP + 28));
|
2007-03-03 00:03:25 +03:00
|
|
|
SP += 32;
|
2005-01-28 23:50:48 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
EDI = edi;
|
|
|
|
ESI = esi;
|
|
|
|
EBP = ebp;
|
|
|
|
EBX = ebx;
|
|
|
|
EDX = edx;
|
|
|
|
ECX = ecx;
|
|
|
|
EAX = eax;
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
2007-11-17 15:44:10 +03:00
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::ENTER32_IwIb(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2005-02-17 00:27:21 +03:00
|
|
|
Bit16u imm16 = i->Iw();
|
2004-11-27 23:36:53 +03:00
|
|
|
Bit8u level = i->Ib2();
|
|
|
|
level &= 0x1F;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2007-11-24 17:22:34 +03:00
|
|
|
BX_CPU_THIS_PTR speculative_rsp = 1;
|
|
|
|
BX_CPU_THIS_PTR prev_rsp = RSP;
|
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
push_32(EBP);
|
2004-11-27 23:36:53 +03:00
|
|
|
Bit32u frame_ptr32 = ESP;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
|
|
|
|
Bit32u ebp = EBP; // Use temp copy for case of exception.
|
2005-02-17 00:27:21 +03:00
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
if (level > 0) {
|
|
|
|
/* do level-1 times */
|
|
|
|
while (--level) {
|
|
|
|
ebp -= 4;
|
2008-06-12 23:14:40 +04:00
|
|
|
Bit32u temp32 = read_virtual_dword_32(BX_SEG_REG_SS, ebp);
|
2008-05-08 22:02:21 +04:00
|
|
|
push_32(temp32);
|
2005-08-10 22:40:38 +04:00
|
|
|
}
|
2007-11-22 20:33:06 +03:00
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
/* push(frame pointer) */
|
|
|
|
push_32(frame_ptr32);
|
|
|
|
}
|
2007-11-24 17:22:34 +03:00
|
|
|
|
2007-11-22 20:33:06 +03:00
|
|
|
ESP -= imm16;
|
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
// ENTER finishes with memory write check on the final stack pointer
|
|
|
|
// the memory is touched but no write actually occurs
|
|
|
|
// emulate it by doing RMW read access from SS:ESP
|
|
|
|
read_RMW_virtual_dword(BX_SEG_REG_SS, ESP);
|
2007-11-22 20:33:06 +03:00
|
|
|
}
|
|
|
|
else {
|
2008-05-08 22:02:21 +04:00
|
|
|
Bit16u bp = BP;
|
|
|
|
|
|
|
|
if (level > 0) {
|
|
|
|
/* do level-1 times */
|
|
|
|
while (--level) {
|
|
|
|
bp -= 4;
|
2008-06-12 23:14:40 +04:00
|
|
|
Bit32u temp32 = read_virtual_dword_32(BX_SEG_REG_SS, bp);
|
2008-05-08 22:02:21 +04:00
|
|
|
push_32(temp32);
|
2007-11-22 20:33:06 +03:00
|
|
|
}
|
2008-05-08 22:02:21 +04:00
|
|
|
|
|
|
|
/* push(frame pointer) */
|
|
|
|
push_32(frame_ptr32);
|
2004-11-27 23:36:53 +03:00
|
|
|
}
|
2007-11-22 20:33:06 +03:00
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
SP -= imm16;
|
|
|
|
|
|
|
|
// ENTER finishes with memory write check on the final stack pointer
|
|
|
|
// the memory is touched but no write actually occurs
|
|
|
|
// emulate it by doing RMW read access from SS:SP
|
2008-06-12 23:14:40 +04:00
|
|
|
read_RMW_virtual_dword_32(BX_SEG_REG_SS, SP);
|
2007-11-22 20:33:06 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
EBP = frame_ptr32;
|
2007-11-24 17:22:34 +03:00
|
|
|
|
2008-05-08 22:02:21 +04:00
|
|
|
BX_CPU_THIS_PTR speculative_rsp = 0;
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2008-08-28 01:57:40 +04:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LEAVE32(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2008-08-28 01:57:40 +04:00
|
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
2007-11-24 17:22:34 +03:00
|
|
|
|
2008-08-28 01:57:40 +04:00
|
|
|
Bit32u value32;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2008-08-28 01:57:40 +04:00
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
|
|
|
|
value32 = read_virtual_dword_32(BX_SEG_REG_SS, EBP);
|
|
|
|
ESP = EBP + 4;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
value32 = read_virtual_dword_32(BX_SEG_REG_SS, BP);
|
|
|
|
SP = BP + 4;
|
|
|
|
}
|
2007-11-24 17:22:34 +03:00
|
|
|
|
2008-08-28 01:57:40 +04:00
|
|
|
EBP = value32;
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|