2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2006-06-05 20:38:43 +04:00
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// $Id: exception.cc,v 1.78 2006-06-05 16:38:43 sshwarts Exp $
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2001-04-10 06:20:02 +04:00
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// Copyright (C) 2001 MandrakeSoft S.A.
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2001-04-10 05:04:59 +04:00
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2001-05-24 22:46:34 +04:00
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#define NEED_CPU_REG_SHORTCUTS 1
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2001-04-10 05:04:59 +04:00
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#include "bochs.h"
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2006-03-07 01:03:16 +03:00
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#include "cpu.h"
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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#define LOG_THIS BX_CPU_THIS_PTR
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2001-04-10 05:04:59 +04:00
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2006-03-07 01:03:16 +03:00
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#include "iodev/iodev.h"
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2005-12-12 22:54:48 +03:00
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#if BX_SUPPORT_X86_64==0
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// Make life easier merging cpu64 & cpu code.
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#define RIP EIP
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#define RSP ESP
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#endif
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2001-04-10 05:04:59 +04:00
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/* Exception classes. These are used as indexes into the 'is_exception_OK'
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* array below, and are stored in the 'exception' array also
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*/
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#define BX_ET_BENIGN 0
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#define BX_ET_CONTRIBUTORY 1
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#define BX_ET_PAGE_FAULT 2
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#define BX_ET_DOUBLE_FAULT 10
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2004-09-15 00:19:54 +04:00
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static const bx_bool is_exception_OK[3][3] = {
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2001-04-10 05:04:59 +04:00
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{ 1, 1, 1 }, /* 1st exception is BENIGN */
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{ 1, 0, 1 }, /* 1st exception is CONTRIBUTORY */
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{ 1, 0, 0 } /* 1st exception is PAGE_FAULT */
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2004-09-15 00:19:54 +04:00
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};
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2001-04-10 05:04:59 +04:00
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2006-02-11 12:08:02 +03:00
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#define BX_EXCEPTION_CLASS_TRAP 0
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#define BX_EXCEPTION_CLASS_FAULT 1
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#define BX_EXCEPTION_CLASS_ABORT 2
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2005-04-12 22:08:10 +04:00
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::long_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
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2001-04-10 05:04:59 +04:00
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{
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2005-04-12 22:08:10 +04:00
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// long mode interrupt
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Bit64u idtindex;
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Bit32u dword1, dword2, dword3;
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bx_descriptor_t gate_descriptor, cs_descriptor;
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bx_selector_t cs_selector;
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Bit16u gate_dest_selector;
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Bit64u gate_dest_offset;
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// interrupt vector must be within IDT table limits,
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// else #GP(vector number*16 + 2 + EXT)
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idtindex = vector*16;
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if ( (idtindex + 15) > BX_CPU_THIS_PTR idtr.limit) {
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2005-07-07 22:40:35 +04:00
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BX_ERROR(("interrupt(long mode): vector > idtr.limit"));
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2005-04-12 22:08:10 +04:00
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BX_ERROR(("IDT.limit = %04x", (unsigned) BX_CPU_THIS_PTR idtr.limit));
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BX_ERROR(("IDT.base = %06x", (unsigned) BX_CPU_THIS_PTR idtr.base));
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BX_ERROR(("interrupt vector must be within IDT table limits"));
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exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
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}
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// descriptor AR byte must indicate interrupt gate, trap gate,
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// or task gate, else #GP(vector*8 + 2 + EXT)
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idtindex += BX_CPU_THIS_PTR idtr.base;
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access_linear(idtindex, 4, 0, BX_READ, &dword1);
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access_linear(idtindex + 4, 4, 0, BX_READ, &dword2);
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access_linear(idtindex + 8, 4, 0, BX_READ, &dword3);
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parse_descriptor(dword1, dword2, &gate_descriptor);
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if ((gate_descriptor.valid==0) || gate_descriptor.segment)
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{
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BX_ERROR(("interrupt(long mode): gate descriptor is not valid sys seg"));
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2005-08-03 00:20:22 +04:00
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exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
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2005-04-12 22:08:10 +04:00
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}
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2005-08-03 00:20:22 +04:00
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if (gate_descriptor.type != BX_386_INTERRUPT_GATE &&
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gate_descriptor.type != BX_386_TRAP_GATE)
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{
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2005-08-04 01:10:42 +04:00
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BX_ERROR(("interrupt(long mode): unsupported gate type %u",
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2005-04-12 22:08:10 +04:00
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(unsigned) gate_descriptor.type));
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2005-08-04 01:10:42 +04:00
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exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
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2005-04-12 22:08:10 +04:00
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}
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// if software interrupt, then gate descripor DPL must be >= CPL,
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// else #GP(vector * 8 + 2 + EXT)
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if (is_INT && (gate_descriptor.dpl < CPL))
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{
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BX_ERROR(("interrupt(long mode): is_INT && (dpl < CPL)"));
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2005-08-03 00:20:22 +04:00
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exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
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2002-03-12 21:59:31 +03:00
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}
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2005-04-12 22:08:10 +04:00
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// Gate must be present, else #NP(vector * 8 + 2 + EXT)
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2005-07-11 00:32:32 +04:00
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if (! IS_PRESENT(gate_descriptor)) {
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2005-04-12 22:08:10 +04:00
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BX_ERROR(("interrupt(long mode): p == 0"));
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2005-08-03 00:20:22 +04:00
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exception(BX_NP_EXCEPTION, vector*16 + 2, 0);
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2001-05-23 12:16:07 +04:00
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}
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2001-04-10 05:04:59 +04:00
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2005-04-12 22:08:10 +04:00
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gate_dest_selector = gate_descriptor.u.gate386.dest_selector;
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gate_dest_offset = ((Bit64u)dword3 << 32) +
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gate_descriptor.u.gate386.dest_offset;
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2001-04-10 05:04:59 +04:00
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2005-04-12 22:08:10 +04:00
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unsigned ist = gate_descriptor.u.gate386.dword_count & 0x7;
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2001-04-10 05:04:59 +04:00
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2005-04-12 22:08:10 +04:00
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// examine CS selector and descriptor given in gate descriptor
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// selector must be non-null else #GP(EXT)
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if ( (gate_dest_selector & 0xfffc) == 0 ) {
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2005-08-03 00:20:22 +04:00
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BX_ERROR(("int_trap_gate(long mode): selector null"));
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2005-04-12 22:08:10 +04:00
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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2001-04-10 05:04:59 +04:00
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2005-04-12 22:08:10 +04:00
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parse_selector(gate_dest_selector, &cs_selector);
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2001-04-10 05:04:59 +04:00
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2005-04-12 22:08:10 +04:00
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// selector must be within its descriptor table limits
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// else #GP(selector+EXT)
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2005-08-04 01:10:42 +04:00
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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2005-04-12 22:08:10 +04:00
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parse_descriptor(dword1, dword2, &cs_descriptor);
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// descriptor AR byte must indicate code seg
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// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
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if ( cs_descriptor.valid==0 ||
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cs_descriptor.segment==0 ||
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cs_descriptor.u.segment.executable==0 ||
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cs_descriptor.dpl>CPL)
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{
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BX_ERROR(("interrupt(long mode): not code segment"));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
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}
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2001-04-10 05:04:59 +04:00
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2005-04-12 22:08:10 +04:00
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// check that it's a 64 bit segment
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2005-08-04 01:10:42 +04:00
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if (! IS_LONG64_SEGMENT(cs_descriptor) || cs_descriptor.u.segment.d_b)
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2005-02-02 00:17:57 +03:00
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{
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2005-04-12 22:08:10 +04:00
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BX_ERROR(("interrupt(long mode): must be 64 bit segment"));
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exception(BX_GP_EXCEPTION, vector, 0);
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}
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// segment must be present, else #NP(selector + EXT)
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2005-07-11 00:32:32 +04:00
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if (! IS_PRESENT(cs_descriptor)) {
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2005-04-12 22:08:10 +04:00
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BX_ERROR(("interrupt(long mode): segment not present"));
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exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc, 0);
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}
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// if code segment is non-conforming and DPL < CPL then
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// INTERRUPT TO INNER PRIVILEGE:
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if ((cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl<CPL) || (ist > 0))
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{
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Bit64u RSP_for_cpl_x;
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BX_DEBUG(("interrupt(long mode): INTERRUPT TO INNER PRIVILEGE"));
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// check selector and descriptor for new stack in current TSS
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if (ist > 0) {
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BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d\n",ist));
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get_RSP_from_TSS(ist+3, &RSP_for_cpl_x);
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}
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else {
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get_RSP_from_TSS(cs_descriptor.dpl, &RSP_for_cpl_x);
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2005-02-02 00:17:57 +03:00
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}
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2005-08-04 23:31:59 +04:00
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RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0);
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if (! IsCanonical(RSP_for_cpl_x)) {
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2005-08-04 01:10:42 +04:00
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BX_ERROR(("interrupt(long mode): canonical address failure %08x%08x",
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2005-08-04 23:31:59 +04:00
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(Bit32u)(RSP_for_cpl_x >> 32), (Bit32u)(RSP_for_cpl_x & 0xffffffff)));
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2005-08-04 01:10:42 +04:00
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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Bit16u old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
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Bit64u old_RIP = RIP;
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2005-04-12 22:08:10 +04:00
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Bit16u old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
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Bit64u old_RSP = RSP;
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2002-09-14 21:29:47 +04:00
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2005-08-04 01:10:42 +04:00
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bx_selector_t ss_selector;
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bx_descriptor_t ss_descriptor;
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2002-09-14 21:29:47 +04:00
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2005-08-04 01:10:42 +04:00
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// set up a null descriptor
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parse_selector(0, &ss_selector);
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parse_descriptor(0, 0, &ss_descriptor);
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2005-04-12 22:08:10 +04:00
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2005-08-04 01:10:42 +04:00
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// load CS:RIP (guaranteed to be in 64 bit mode)
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branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, cs_descriptor.dpl);
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2005-04-12 22:08:10 +04:00
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2005-08-04 01:10:42 +04:00
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// set up null SS descriptor
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load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
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2005-04-12 22:08:10 +04:00
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2005-08-04 01:10:42 +04:00
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RSP = RSP_for_cpl_x;
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2005-04-12 22:08:10 +04:00
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2005-08-04 01:10:42 +04:00
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/* the size of the gate controls the size of the stack pushes */
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2005-04-12 22:08:10 +04:00
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2005-08-04 01:10:42 +04:00
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// push old stack long pointer onto new stack
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2005-04-12 22:08:10 +04:00
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push_64(old_SS);
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push_64(old_RSP);
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push_64(read_eflags());
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// push long pointer to return address onto new stack
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2005-08-04 01:10:42 +04:00
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push_64(old_CS);
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push_64(old_RIP);
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2005-04-12 22:08:10 +04:00
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if ( is_error_code )
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push_64(error_code);
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// if INTERRUPT GATE set IF to 0
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if ( !(gate_descriptor.type & 1) ) // even is int-gate
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BX_CPU_THIS_PTR clear_IF ();
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BX_CPU_THIS_PTR clear_TF ();
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BX_CPU_THIS_PTR clear_VM ();
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BX_CPU_THIS_PTR clear_RF ();
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BX_CPU_THIS_PTR clear_NT ();
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return;
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}
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// if code segment is conforming OR code segment DPL = CPL then
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// INTERRUPT TO SAME PRIVILEGE LEVEL:
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2005-08-04 23:31:59 +04:00
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if (cs_descriptor.u.segment.c_ed || cs_descriptor.dpl==CPL)
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2005-04-12 22:08:10 +04:00
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{
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BX_DEBUG(("interrupt(long mode): INTERRUPT TO SAME PRIVILEGE"));
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Bit64u old_RSP = RSP;
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// check selector and descriptor for new stack in current TSS
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if (ist > 0) {
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BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d\n",ist));
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get_RSP_from_TSS(ist+3, &RSP);
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2005-02-02 00:17:57 +03:00
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}
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2005-04-12 22:08:10 +04:00
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// align stack
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2005-08-04 23:31:59 +04:00
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RSP &= BX_CONST64(0xfffffffffffffff0);
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2005-04-12 22:08:10 +04:00
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// push flags onto stack
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// push current CS selector onto stack
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// push return offset onto stack
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
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push_64(old_RSP);
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push_64(read_eflags());
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_64(RIP);
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if ( is_error_code )
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push_64(error_code);
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// set the RPL field of CS to CPL
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2005-08-04 01:10:42 +04:00
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branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, CPL);
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2005-04-12 22:08:10 +04:00
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// if interrupt gate then set IF to 0
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if ( !(gate_descriptor.type & 1) ) // even is int-gate
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BX_CPU_THIS_PTR clear_IF ();
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BX_CPU_THIS_PTR clear_TF ();
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BX_CPU_THIS_PTR clear_VM ();
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|
BX_CPU_THIS_PTR clear_RF ();
|
|
|
|
BX_CPU_THIS_PTR clear_NT ();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// else #GP(CS selector + ext)
|
|
|
|
BX_ERROR(("interrupt(long mode): bad descriptor"));
|
|
|
|
BX_ERROR(("c_ed=%u, descriptor.dpl=%u, CPL=%u",
|
|
|
|
(unsigned) cs_descriptor.u.segment.c_ed,
|
|
|
|
(unsigned) cs_descriptor.dpl,
|
|
|
|
(unsigned) CPL));
|
|
|
|
BX_ERROR(("cs.segment = %u", (unsigned) cs_descriptor.segment));
|
|
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
|
|
|
|
{
|
|
|
|
// protected mode interrupt
|
|
|
|
Bit32u dword1, dword2;
|
|
|
|
bx_descriptor_t gate_descriptor, cs_descriptor;
|
|
|
|
bx_selector_t cs_selector;
|
|
|
|
|
|
|
|
Bit16u raw_tss_selector;
|
|
|
|
bx_selector_t tss_selector;
|
|
|
|
bx_descriptor_t tss_descriptor;
|
|
|
|
|
|
|
|
Bit16u gate_dest_selector;
|
|
|
|
Bit32u gate_dest_offset;
|
|
|
|
|
|
|
|
// interrupt vector must be within IDT table limits,
|
|
|
|
// else #GP(vector number*8 + 2 + EXT)
|
|
|
|
if ( (vector*8 + 7) > BX_CPU_THIS_PTR idtr.limit) {
|
|
|
|
BX_DEBUG(("IDT.limit = %04x", (unsigned) BX_CPU_THIS_PTR idtr.limit));
|
|
|
|
BX_DEBUG(("IDT.base = %06x", (unsigned) BX_CPU_THIS_PTR idtr.base));
|
|
|
|
BX_DEBUG(("interrupt vector must be within IDT table limits"));
|
|
|
|
BX_DEBUG(("interrupt(): vector > idtr.limit"));
|
|
|
|
exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
// descriptor AR byte must indicate interrupt gate, trap gate,
|
|
|
|
// or task gate, else #GP(vector*8 + 2 + EXT)
|
|
|
|
access_linear(BX_CPU_THIS_PTR idtr.base + vector*8, 4, 0,
|
|
|
|
BX_READ, &dword1);
|
|
|
|
access_linear(BX_CPU_THIS_PTR idtr.base + vector*8 + 4, 4, 0,
|
|
|
|
BX_READ, &dword2);
|
|
|
|
|
|
|
|
parse_descriptor(dword1, dword2, &gate_descriptor);
|
|
|
|
|
|
|
|
if ((gate_descriptor.valid==0) || gate_descriptor.segment) {
|
|
|
|
BX_DEBUG(("interrupt(): gate descriptor is not valid sys seg"));
|
|
|
|
exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (gate_descriptor.type) {
|
|
|
|
case BX_TASK_GATE:
|
|
|
|
case BX_286_INTERRUPT_GATE:
|
|
|
|
case BX_286_TRAP_GATE:
|
|
|
|
case BX_386_INTERRUPT_GATE:
|
|
|
|
case BX_386_TRAP_GATE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BX_DEBUG(("interrupt(): gate.type(%u) != {5,6,7,14,15}",
|
|
|
|
(unsigned) gate_descriptor.type));
|
|
|
|
exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
// if software interrupt, then gate descripor DPL must be >= CPL,
|
|
|
|
// else #GP(vector * 8 + 2 + EXT)
|
|
|
|
if (is_INT && (gate_descriptor.dpl < CPL)) {
|
|
|
|
BX_DEBUG(("interrupt(): is_INT && (dpl < CPL)"));
|
|
|
|
exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Gate must be present, else #NP(vector * 8 + 2 + EXT)
|
2005-07-11 00:32:32 +04:00
|
|
|
if (! IS_PRESENT(gate_descriptor)) {
|
2005-04-12 22:08:10 +04:00
|
|
|
BX_DEBUG(("interrupt(): gate not present"));
|
|
|
|
exception(BX_NP_EXCEPTION, vector*8 + 2, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (gate_descriptor.type) {
|
|
|
|
case BX_TASK_GATE:
|
|
|
|
// examine selector to TSS, given in task gate descriptor
|
|
|
|
raw_tss_selector = gate_descriptor.u.taskgate.tss_selector;
|
|
|
|
parse_selector(raw_tss_selector, &tss_selector);
|
|
|
|
|
|
|
|
// must specify global in the local/global bit,
|
2005-12-12 22:44:06 +03:00
|
|
|
// else #GP(TSS selector)
|
2005-04-12 22:08:10 +04:00
|
|
|
if (tss_selector.ti) {
|
|
|
|
BX_PANIC(("interrupt: tss_selector.ti=1"));
|
2005-12-12 22:44:06 +03:00
|
|
|
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// index must be within GDT limits, else #TS(TSS selector)
|
2005-12-13 01:01:22 +03:00
|
|
|
fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
|
2005-04-12 22:08:10 +04:00
|
|
|
|
|
|
|
parse_descriptor(dword1, dword2, &tss_descriptor);
|
|
|
|
|
2005-12-12 22:44:06 +03:00
|
|
|
// AR byte must specify available TSS,
|
|
|
|
// else #GP(TSS selector)
|
2005-04-12 22:08:10 +04:00
|
|
|
if (tss_descriptor.valid==0 || tss_descriptor.segment) {
|
|
|
|
BX_PANIC(("exception: TSS selector points to bad TSS"));
|
2005-12-12 22:44:06 +03:00
|
|
|
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
|
2005-04-12 22:08:10 +04:00
|
|
|
}
|
|
|
|
if (tss_descriptor.type!=9 && tss_descriptor.type!=1) {
|
|
|
|
BX_INFO(("exception: TSS selector points to bad TSS"));
|
2005-12-12 22:44:06 +03:00
|
|
|
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// TSS must be present, else #NP(TSS selector)
|
2005-08-02 22:44:20 +04:00
|
|
|
if (! IS_PRESENT(tss_descriptor)) {
|
|
|
|
BX_ERROR(("exception: TSS descriptor.p == 0"));
|
|
|
|
exception(BX_NP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
|
|
|
|
}
|
2005-04-12 22:08:10 +04:00
|
|
|
|
|
|
|
// switch tasks with nesting to TSS
|
|
|
|
task_switch(&tss_selector, &tss_descriptor,
|
|
|
|
BX_TASK_FROM_CALL_OR_INT, dword1, dword2);
|
|
|
|
|
|
|
|
// if interrupt was caused by fault with error code
|
|
|
|
// stack limits must allow push of 2 more bytes, else #SS(0)
|
|
|
|
// push error code onto stack
|
|
|
|
|
|
|
|
if ( is_error_code ) {
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b)
|
|
|
|
push_32(error_code);
|
|
|
|
else
|
|
|
|
push_16(error_code);
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// instruction pointer must be in CS limit, else #GP(0)
|
|
|
|
if (EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
|
|
|
|
BX_ERROR(("exception(): EIP > CS.limit"));
|
|
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
return;
|
|
|
|
|
|
|
|
case BX_286_INTERRUPT_GATE:
|
|
|
|
case BX_286_TRAP_GATE:
|
|
|
|
case BX_386_INTERRUPT_GATE:
|
|
|
|
case BX_386_TRAP_GATE:
|
|
|
|
if ( gate_descriptor.type >= 14 ) { // 386 gate
|
|
|
|
gate_dest_selector = gate_descriptor.u.gate386.dest_selector;
|
|
|
|
gate_dest_offset = gate_descriptor.u.gate386.dest_offset;
|
|
|
|
}
|
|
|
|
else { // 286 gate
|
|
|
|
gate_dest_selector = gate_descriptor.u.gate286.dest_selector;
|
|
|
|
gate_dest_offset = gate_descriptor.u.gate286.dest_offset;
|
|
|
|
}
|
2003-02-26 05:48:12 +03:00
|
|
|
|
2002-09-14 21:29:47 +04:00
|
|
|
// examine CS selector and descriptor given in gate descriptor
|
|
|
|
// selector must be non-null else #GP(EXT)
|
|
|
|
if ( (gate_dest_selector & 0xfffc) == 0 ) {
|
2005-07-07 22:40:35 +04:00
|
|
|
BX_ERROR(("int_trap_gate(): selector null"));
|
2002-09-14 21:29:47 +04:00
|
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
|
|
|
parse_selector(gate_dest_selector, &cs_selector);
|
|
|
|
|
|
|
|
// selector must be within its descriptor table limits
|
|
|
|
// else #GP(selector+EXT)
|
2005-04-12 22:08:10 +04:00
|
|
|
fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
|
2002-09-14 21:29:47 +04:00
|
|
|
parse_descriptor(dword1, dword2, &cs_descriptor);
|
|
|
|
|
|
|
|
// descriptor AR byte must indicate code seg
|
|
|
|
// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
|
|
|
|
if ( cs_descriptor.valid==0 ||
|
|
|
|
cs_descriptor.segment==0 ||
|
|
|
|
cs_descriptor.u.segment.executable==0 ||
|
2005-04-12 22:08:10 +04:00
|
|
|
cs_descriptor.dpl>CPL )
|
2004-07-12 23:20:55 +04:00
|
|
|
{
|
2005-04-12 22:08:10 +04:00
|
|
|
BX_DEBUG(("interrupt(): not code segment"));
|
2002-09-14 21:29:47 +04:00
|
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
2004-07-12 23:20:55 +04:00
|
|
|
}
|
2005-02-02 00:17:57 +03:00
|
|
|
|
2002-09-14 21:29:47 +04:00
|
|
|
// segment must be present, else #NP(selector + EXT)
|
2005-07-11 00:32:32 +04:00
|
|
|
if (! IS_PRESENT(cs_descriptor)) {
|
2005-04-12 22:08:10 +04:00
|
|
|
BX_DEBUG(("interrupt(): segment not present"));
|
2002-09-14 21:29:47 +04:00
|
|
|
exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
2004-07-12 23:20:55 +04:00
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
|
|
|
// if code segment is non-conforming and DPL < CPL then
|
|
|
|
// INTERRUPT TO INNER PRIVILEGE:
|
2005-04-12 22:08:10 +04:00
|
|
|
if ( cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl<CPL )
|
2004-07-12 23:20:55 +04:00
|
|
|
{
|
2005-04-12 22:08:10 +04:00
|
|
|
Bit16u old_SS, old_CS, SS_for_cpl_x;
|
|
|
|
Bit32u ESP_for_cpl_x, old_EIP, old_ESP;
|
|
|
|
bx_descriptor_t ss_descriptor;
|
|
|
|
bx_selector_t ss_selector;
|
|
|
|
int bytes;
|
|
|
|
int is_v8086_mode = v8086_mode();
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE"));
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
if (is_v8086_mode && cs_descriptor.dpl != 0) {
|
|
|
|
// if code segment DPL != 0 then #GP(new code segment selector)
|
|
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
2003-02-26 05:48:12 +03:00
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// check selector and descriptor for new stack in current TSS
|
|
|
|
get_SS_ESP_from_TSS(cs_descriptor.dpl,
|
|
|
|
&SS_for_cpl_x, &ESP_for_cpl_x);
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// Selector must be non-null else #TS(EXT)
|
|
|
|
if ( (SS_for_cpl_x & 0xfffc) == 0 ) {
|
|
|
|
BX_PANIC(("interrupt(): SS selector null"));
|
|
|
|
exception(BX_TS_EXCEPTION, 0, 0); /* TS(ext) */
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// selector index must be within its descriptor table limits
|
|
|
|
// else #TS(SS selector + EXT)
|
|
|
|
parse_selector(SS_for_cpl_x, &ss_selector);
|
|
|
|
// fetch 2 dwords of descriptor; call handles out of limits checks
|
|
|
|
fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
|
|
|
|
parse_descriptor(dword1, dword2, &ss_descriptor);
|
|
|
|
|
|
|
|
// selector rpl must = dpl of code segment,
|
|
|
|
// else #TS(SS selector + ext)
|
|
|
|
if (ss_selector.rpl != cs_descriptor.dpl) {
|
|
|
|
BX_PANIC(("interrupt(): SS.rpl != CS.dpl"));
|
|
|
|
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
|
|
}
|
2002-10-08 18:43:18 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// stack seg DPL must = DPL of code segment,
|
|
|
|
// else #TS(SS selector + ext)
|
|
|
|
if (ss_descriptor.dpl != cs_descriptor.dpl) {
|
|
|
|
BX_PANIC(("interrupt(): SS.dpl != CS.dpl"));
|
|
|
|
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
|
|
}
|
2002-10-08 18:43:18 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// descriptor must indicate writable data segment,
|
|
|
|
// else #TS(SS selector + EXT)
|
|
|
|
if (ss_descriptor.valid==0 ||
|
|
|
|
ss_descriptor.segment==0 ||
|
|
|
|
ss_descriptor.u.segment.executable==1 ||
|
|
|
|
ss_descriptor.u.segment.r_w==0)
|
|
|
|
{
|
|
|
|
BX_PANIC(("interrupt(): SS not writable data segment"));
|
|
|
|
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// seg must be present, else #SS(SS selector + ext)
|
2005-07-11 00:32:32 +04:00
|
|
|
if (! IS_PRESENT(ss_descriptor)) {
|
|
|
|
BX_ERROR(("interrupt(): SS not present"));
|
2005-04-12 22:08:10 +04:00
|
|
|
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
if (gate_descriptor.type>=14) {
|
|
|
|
// 386 int/trap gate
|
|
|
|
// new stack must have room for 20|24 bytes, else #SS(0)
|
|
|
|
if ( is_error_code )
|
|
|
|
bytes = 24;
|
|
|
|
else
|
|
|
|
bytes = 20;
|
|
|
|
if (is_v8086_mode)
|
|
|
|
bytes += 16;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
// new stack must have room for 10|12 bytes, else #SS(0)
|
|
|
|
if ( is_error_code )
|
|
|
|
bytes = 12;
|
|
|
|
else
|
|
|
|
bytes = 10;
|
|
|
|
if (is_v8086_mode) {
|
|
|
|
bytes += 8;
|
|
|
|
BX_PANIC(("interrupt: int/trap gate VM"));
|
|
|
|
}
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// new stack must have enough room, else #SS(seg selector)
|
|
|
|
if ( !can_push(&ss_descriptor, ESP_for_cpl_x, bytes) )
|
|
|
|
{
|
|
|
|
BX_DEBUG(("interrupt(): new stack doesn't have room for %u bytes", (unsigned) bytes));
|
|
|
|
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// IP must be within CS segment boundaries, else #GP(0)
|
|
|
|
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
|
|
|
|
BX_DEBUG(("interrupt(): gate EIP > CS.limit"));
|
|
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
old_ESP = ESP;
|
|
|
|
old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
|
|
|
|
old_EIP = EIP;
|
|
|
|
old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// load new SS:SP values from TSS
|
|
|
|
load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
|
2003-02-26 05:48:12 +03:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
if (ss_descriptor.u.segment.d_b)
|
|
|
|
ESP = ESP_for_cpl_x;
|
|
|
|
else
|
|
|
|
SP = ESP_for_cpl_x; // leave upper 16bits
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// load new CS:IP values from gate
|
|
|
|
// set CPL to new code segment DPL
|
|
|
|
// set RPL of CS to CPL
|
|
|
|
load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
|
|
|
|
EIP = gate_dest_offset;
|
|
|
|
|
|
|
|
Bit32u eflags = read_eflags();
|
|
|
|
|
2002-09-14 21:29:47 +04:00
|
|
|
// if INTERRUPT GATE set IF to 0
|
|
|
|
if ( !(gate_descriptor.type & 1) ) // even is int-gate
|
|
|
|
BX_CPU_THIS_PTR clear_IF ();
|
|
|
|
BX_CPU_THIS_PTR clear_TF ();
|
|
|
|
BX_CPU_THIS_PTR clear_VM ();
|
|
|
|
BX_CPU_THIS_PTR clear_RF ();
|
|
|
|
BX_CPU_THIS_PTR clear_NT ();
|
2005-04-12 22:08:10 +04:00
|
|
|
|
|
|
|
if (is_v8086_mode)
|
|
|
|
{
|
|
|
|
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
|
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
|
|
}
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 0;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = 0;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 0;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = 0;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
|
|
|
// push long pointer to old stack onto new stack
|
|
|
|
push_32(old_SS);
|
|
|
|
push_32(old_ESP);
|
|
|
|
|
|
|
|
// push EFLAGS
|
|
|
|
push_32(eflags);
|
|
|
|
|
|
|
|
// push long pointer to return address onto new stack
|
|
|
|
push_32(old_CS);
|
|
|
|
push_32(old_EIP);
|
|
|
|
|
2005-12-13 01:01:22 +03:00
|
|
|
if (is_error_code)
|
2005-04-12 22:08:10 +04:00
|
|
|
push_32(error_code);
|
|
|
|
}
|
|
|
|
else { // 286 int/trap gate
|
|
|
|
// push long pointer to old stack onto new stack
|
|
|
|
push_16(old_SS);
|
|
|
|
push_16(old_ESP); // ignores upper 16bits
|
|
|
|
|
|
|
|
// push FLAGS
|
|
|
|
push_16(eflags); // ignores upper 16bits
|
|
|
|
|
|
|
|
// push return address onto new stack
|
|
|
|
push_16(old_CS);
|
|
|
|
push_16(old_EIP); // ignores upper 16bits
|
|
|
|
|
2005-12-13 01:01:22 +03:00
|
|
|
if (is_error_code)
|
2005-04-12 22:08:10 +04:00
|
|
|
push_16(error_code);
|
|
|
|
}
|
|
|
|
|
2002-09-14 21:29:47 +04:00
|
|
|
return;
|
2004-07-12 23:20:55 +04:00
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
if (v8086_mode()) {
|
|
|
|
// if code segment DPL != 0 then #GP(new code segment selector)
|
|
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
|
|
|
}
|
|
|
|
|
2002-09-14 21:29:47 +04:00
|
|
|
// if code segment is conforming OR code segment DPL = CPL then
|
|
|
|
// INTERRUPT TO SAME PRIVILEGE LEVEL:
|
2005-04-12 22:08:10 +04:00
|
|
|
if ( cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL )
|
2004-07-12 23:20:55 +04:00
|
|
|
{
|
2005-04-12 22:08:10 +04:00
|
|
|
int bytes;
|
|
|
|
Bit32u temp_ESP;
|
|
|
|
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
|
|
|
|
temp_ESP = ESP;
|
|
|
|
else
|
|
|
|
temp_ESP = SP;
|
|
|
|
|
|
|
|
BX_DEBUG(("int_trap_gate286(): INTERRUPT TO SAME PRIVILEGE"));
|
|
|
|
|
|
|
|
// Current stack limits must allow pushing 6|8 bytes, else #SS(0)
|
|
|
|
if (gate_descriptor.type >= 14) { // 386 gate
|
|
|
|
if ( is_error_code )
|
|
|
|
bytes = 16;
|
|
|
|
else
|
|
|
|
bytes = 12;
|
|
|
|
}
|
|
|
|
else { // 286 gate
|
|
|
|
if ( is_error_code )
|
|
|
|
bytes = 8;
|
|
|
|
else
|
|
|
|
bytes = 6;
|
|
|
|
}
|
2005-03-31 01:43:08 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
if (! can_push(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, temp_ESP, bytes))
|
|
|
|
{
|
|
|
|
BX_DEBUG(("interrupt(): stack doesn't have room"));
|
|
|
|
exception(BX_SS_EXCEPTION, 0, 0);
|
2005-03-31 01:43:08 +04:00
|
|
|
}
|
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// EIP must be in CS limit else #GP(0)
|
|
|
|
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
|
|
|
|
BX_ERROR(("interrupt(): IP > cs descriptor limit"));
|
|
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
|
|
|
// push flags onto stack
|
|
|
|
// push current CS selector onto stack
|
|
|
|
// push return offset onto stack
|
2005-04-12 22:08:10 +04:00
|
|
|
if (gate_descriptor.type >= 14) { // 386 gate
|
|
|
|
push_32(read_eflags());
|
|
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
|
|
|
push_32(EIP);
|
|
|
|
if ( is_error_code )
|
|
|
|
push_32(error_code);
|
|
|
|
}
|
|
|
|
else { // 286 gate
|
|
|
|
push_16(read_flags());
|
|
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
|
|
|
push_16(IP);
|
|
|
|
if ( is_error_code )
|
|
|
|
push_16(error_code);
|
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
|
|
|
// load CS:IP from gate
|
|
|
|
// load CS descriptor
|
|
|
|
// set the RPL field of CS to CPL
|
|
|
|
load_cs(&cs_selector, &cs_descriptor, CPL);
|
2005-04-12 22:08:10 +04:00
|
|
|
EIP = gate_dest_offset;
|
2002-09-14 21:29:47 +04:00
|
|
|
|
|
|
|
// if interrupt gate then set IF to 0
|
|
|
|
if ( !(gate_descriptor.type & 1) ) // even is int-gate
|
|
|
|
BX_CPU_THIS_PTR clear_IF ();
|
|
|
|
BX_CPU_THIS_PTR clear_TF ();
|
2005-04-12 22:08:10 +04:00
|
|
|
BX_CPU_THIS_PTR clear_NT ();
|
2002-09-14 21:29:47 +04:00
|
|
|
BX_CPU_THIS_PTR clear_VM ();
|
|
|
|
BX_CPU_THIS_PTR clear_RF ();
|
|
|
|
return;
|
2004-07-12 23:20:55 +04:00
|
|
|
}
|
2002-09-14 21:29:47 +04:00
|
|
|
|
|
|
|
// else #GP(CS selector + ext)
|
2005-04-12 22:08:10 +04:00
|
|
|
BX_DEBUG(("interrupt: bad descriptor"));
|
|
|
|
BX_DEBUG(("c_ed=%u, descriptor.dpl=%u, CPL=%u",
|
|
|
|
(unsigned) cs_descriptor.u.segment.c_ed,
|
|
|
|
(unsigned) cs_descriptor.dpl,
|
|
|
|
(unsigned) CPL));
|
|
|
|
BX_DEBUG(("cs.segment = %u", (unsigned) cs_descriptor.segment));
|
2002-09-14 21:29:47 +04:00
|
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
2005-04-12 22:08:10 +04:00
|
|
|
break;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
default:
|
|
|
|
BX_PANIC(("bad descriptor type in interrupt()!"));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
void BX_CPU_C::real_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
|
|
|
|
{
|
|
|
|
// real mode interrupt
|
|
|
|
Bit16u cs_selector, ip;
|
2005-03-01 23:55:25 +03:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
if ( (vector*4+3) > BX_CPU_THIS_PTR idtr.limit )
|
|
|
|
{
|
|
|
|
BX_ERROR(("interrupt(real mode) vector > idtr.limit"));
|
|
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
push_16(read_flags());
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
cs_selector = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
|
|
|
push_16(cs_selector);
|
|
|
|
ip = EIP;
|
|
|
|
push_16(ip);
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
access_linear(BX_CPU_THIS_PTR idtr.base + 4 * vector, 2, 0, BX_READ, &ip);
|
|
|
|
EIP = (Bit32u) ip;
|
|
|
|
access_linear(BX_CPU_THIS_PTR idtr.base + 4 * vector + 2, 2, 0, BX_READ, &cs_selector);
|
|
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_selector);
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
/* INT affects the following flags: I,T */
|
|
|
|
BX_CPU_THIS_PTR clear_IF ();
|
|
|
|
BX_CPU_THIS_PTR clear_TF ();
|
|
|
|
#if BX_CPU_LEVEL >= 4
|
|
|
|
BX_CPU_THIS_PTR clear_AC ();
|
|
|
|
#endif
|
|
|
|
BX_CPU_THIS_PTR clear_RF ();
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
void BX_CPU_C::interrupt(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
|
|
|
|
{
|
|
|
|
#if BX_DEBUGGER
|
|
|
|
if (bx_guard.special_unwind_stack) {
|
|
|
|
BX_INFO (("interrupt() returning early because special_unwind_stack is set"));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
BX_CPU_THIS_PTR show_flag |= Flag_intsig;
|
|
|
|
#if BX_DEBUG_LINUX
|
|
|
|
if (bx_dbg.linux_syscall) {
|
2006-01-26 01:20:00 +03:00
|
|
|
if (vector == 0x80) bx_dbg_linux_syscall(BX_CPU_ID);
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
#endif
|
2005-04-12 22:08:10 +04:00
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
BX_DEBUG(("interrupt(): vector = %u, INT = %u, EXT = %u",
|
|
|
|
(unsigned) vector, (unsigned) is_INT, (unsigned) BX_CPU_THIS_PTR EXT));
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
BX_INSTR_INTERRUPT(BX_CPU_ID, vector);
|
|
|
|
invalidate_prefetch_q();
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
// Discard any traps and inhibits for new context; traps will
|
|
|
|
// resume upon return.
|
|
|
|
BX_CPU_THIS_PTR debug_trap = 0;
|
|
|
|
BX_CPU_THIS_PTR inhibit_mask = 0;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-10-17 17:06:09 +04:00
|
|
|
BX_CPU_THIS_PTR save_cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS];
|
|
|
|
BX_CPU_THIS_PTR save_ss = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS];
|
|
|
|
BX_CPU_THIS_PTR save_eip = RIP;
|
|
|
|
BX_CPU_THIS_PTR save_esp = RSP;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
if (BX_CPU_THIS_PTR msr.lma) {
|
|
|
|
long_mode_int(vector, is_INT, is_error_code, error_code);
|
2005-08-09 01:03:32 +04:00
|
|
|
return;
|
2005-04-12 22:08:10 +04:00
|
|
|
}
|
|
|
|
#endif // #if BX_SUPPORT_X86_64
|
2005-08-09 01:03:32 +04:00
|
|
|
|
2005-04-12 22:08:10 +04:00
|
|
|
if(real_mode()) {
|
|
|
|
real_mode_int(vector, is_INT, is_error_code, error_code);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
protected_mode_int(vector, is_INT, is_error_code, error_code);
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-02-02 00:17:57 +03:00
|
|
|
// vector: 0..255: vector in IDT
|
|
|
|
// error_code: if exception generates and error, push this error code
|
|
|
|
void BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2006-02-11 12:08:02 +03:00
|
|
|
unsigned exception_type = 0, exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
bx_bool push_error = 0;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2002-10-07 02:08:18 +04:00
|
|
|
invalidate_prefetch_q();
|
|
|
|
UNUSED(is_INT);
|
|
|
|
|
2002-03-12 21:59:31 +03:00
|
|
|
#if BX_DEBUGGER
|
2002-03-12 12:16:41 +03:00
|
|
|
if (bx_guard.special_unwind_stack) {
|
|
|
|
BX_INFO (("exception() returning early because special_unwind_stack is set"));
|
2002-10-07 02:08:18 +04:00
|
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2002-03-12 21:59:31 +03:00
|
|
|
#endif
|
2002-03-12 12:16:41 +03:00
|
|
|
|
2005-10-13 20:22:21 +04:00
|
|
|
//#if BX_EXTERNAL_DEBUGGER
|
2002-09-25 10:36:42 +04:00
|
|
|
//trap_debugger(1);
|
2005-10-13 20:22:21 +04:00
|
|
|
//#endif
|
2002-09-14 21:29:47 +04:00
|
|
|
|
2003-02-13 18:04:11 +03:00
|
|
|
BX_INSTR_EXCEPTION(BX_CPU_ID, vector);
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2006-06-05 20:38:43 +04:00
|
|
|
BX_DEBUG(("exception(0x%02X)", (unsigned) vector));
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
// if not initial error, restore previous register values from
|
|
|
|
// previous attempt to handle exception
|
|
|
|
if (BX_CPU_THIS_PTR errorno) {
|
2005-10-17 17:06:09 +04:00
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS] = BX_CPU_THIS_PTR save_cs;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS] = BX_CPU_THIS_PTR save_ss;
|
|
|
|
RIP = BX_CPU_THIS_PTR save_eip;
|
|
|
|
RSP = BX_CPU_THIS_PTR save_esp;
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
BX_CPU_THIS_PTR errorno++;
|
|
|
|
|
2006-02-01 21:12:08 +03:00
|
|
|
if (BX_CPU_THIS_PTR errorno >= 3 ||
|
|
|
|
// if 1st was a double fault (software INT?), then shutdown
|
|
|
|
(BX_CPU_THIS_PTR errorno == 2 && BX_CPU_THIS_PTR curr_exception[0]==BX_ET_DOUBLE_FAULT))
|
|
|
|
{
|
2006-02-18 19:53:18 +03:00
|
|
|
if (SIM->get_param_bool(BXPN_RESET_ON_TRIPLE_FAULT)->get()) {
|
2006-02-01 21:12:08 +03:00
|
|
|
BX_ERROR(("exception(): 3rd (%d) exception with no resolution, shutdown status is %02xh, resetting", vector, DEV_cmos_get_reg(0x0f)));
|
|
|
|
debug(BX_CPU_THIS_PTR prev_eip);
|
|
|
|
bx_pc_system.Reset(BX_RESET_SOFTWARE);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
BX_PANIC(("exception(): 3rd (%d) exception with no resolution", vector));
|
|
|
|
BX_ERROR(("WARNING: Any simulation after this point is completely bogus !"));
|
2006-04-05 21:31:35 +04:00
|
|
|
shutdown();
|
2006-02-01 21:12:08 +03:00
|
|
|
}
|
2002-03-12 22:00:44 +03:00
|
|
|
#if BX_DEBUGGER
|
2002-03-12 12:16:41 +03:00
|
|
|
bx_guard.special_unwind_stack = true;
|
2002-03-12 22:00:44 +03:00
|
|
|
#endif
|
2002-10-07 02:08:18 +04:00
|
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
2005-08-03 00:20:22 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
// note: fault-class exceptions _except_ #DB set RF in
|
|
|
|
// eflags image.
|
|
|
|
|
|
|
|
switch (vector) {
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_DE_EXCEPTION: // DIV by 0
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_DB_EXCEPTION: // debug exceptions
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
// Instruction fetch breakpoint - FAULT
|
|
|
|
// Data read or write breakpoint - TRAP
|
|
|
|
// I/O read or write breakpoint - TRAP
|
|
|
|
// General detect condition - FAULT
|
|
|
|
// Single-step - TRAP
|
|
|
|
// Task-switch - TRAP
|
|
|
|
exception_class = BX_EXCEPTION_CLASS_TRAP; // FIXME !
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case 2: // NMI
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_BP_EXCEPTION: // breakpoint
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_TRAP;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_OF_EXCEPTION: // overflow
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_TRAP;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_BR_EXCEPTION: // bounds check
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_UD_EXCEPTION: // invalid opcode
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_NM_EXCEPTION: // device not available
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_DF_EXCEPTION: // double fault
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 1;
|
2006-02-11 12:08:02 +03:00
|
|
|
error_code = 0;
|
|
|
|
exception_class = BX_EXCEPTION_CLASS_ABORT;
|
|
|
|
exception_type = BX_ET_DOUBLE_FAULT;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case 9: // coprocessor segment overrun (286,386 only)
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_ABORT;
|
|
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_PANIC(("exception(9): unfinished"));
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_TS_EXCEPTION: // invalid TSS
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 1;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_NP_EXCEPTION: // segment not present
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 1;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_SS_EXCEPTION: // stack fault
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 1;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_GP_EXCEPTION: // general protection
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 1;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_PF_EXCEPTION: // page fault
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 1;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_PAGE_FAULT;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case 15: // reserved
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_PANIC(("exception(15): reserved"));
|
2006-01-31 20:41:08 +03:00
|
|
|
push_error = 0;
|
|
|
|
exception_type = 0;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_MF_EXCEPTION: // floating-point error
|
2001-04-10 05:04:59 +04:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
#if BX_CPU_LEVEL >= 4
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_AC_EXCEPTION: // alignment check
|
2006-02-11 12:08:02 +03:00
|
|
|
BX_PANIC(("exception(): alignment-check, vector 17 not implemented"));
|
|
|
|
push_error = 1;
|
|
|
|
error_code = 0;
|
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if BX_CPU_LEVEL >= 5
|
2006-01-31 20:41:08 +03:00
|
|
|
case BX_MC_EXCEPTION: // machine check
|
2006-02-11 12:08:02 +03:00
|
|
|
BX_PANIC(("exception(): machine-check, vector 18 not implemented"));
|
2006-01-31 20:41:08 +03:00
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_ABORT;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2006-01-31 20:41:08 +03:00
|
|
|
#if BX_SUPPORT_SSE
|
|
|
|
case BX_XM_EXCEPTION: // SIMD Floating-Point exception
|
|
|
|
push_error = 0;
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_class = BX_EXCEPTION_CLASS_FAULT;
|
|
|
|
exception_type = BX_ET_BENIGN;
|
2006-01-31 20:41:08 +03:00
|
|
|
break;
|
|
|
|
#endif
|
2001-04-10 05:04:59 +04:00
|
|
|
#endif
|
|
|
|
default:
|
2001-05-30 22:56:02 +04:00
|
|
|
BX_PANIC(("exception(%u): bad vector", (unsigned) vector));
|
2006-02-11 12:08:02 +03:00
|
|
|
exception_type = BX_ET_BENIGN;
|
|
|
|
push_error = 0; // keep compiler happy for now
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2006-02-11 12:08:02 +03:00
|
|
|
if (exception_class == BX_EXCEPTION_CLASS_FAULT)
|
|
|
|
{
|
|
|
|
// restore RIP/RSP to value before error occurred
|
|
|
|
RIP = BX_CPU_THIS_PTR prev_eip;
|
|
|
|
RSP = BX_CPU_THIS_PTR prev_esp;
|
|
|
|
|
2006-02-28 23:29:03 +03:00
|
|
|
if (BX_CPU_THIS_PTR except_chk) // FIXME: Help with OS/2
|
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR except_chk = 0;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS] = BX_CPU_THIS_PTR except_cs;
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS] = BX_CPU_THIS_PTR except_ss;
|
|
|
|
}
|
|
|
|
|
2006-02-11 12:08:02 +03:00
|
|
|
if (vector != BX_DB_EXCEPTION) BX_CPU_THIS_PTR assert_RF();
|
|
|
|
}
|
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
if (exception_type != BX_ET_PAGE_FAULT) {
|
|
|
|
// Page faults have different format
|
|
|
|
error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2006-01-31 20:41:08 +03:00
|
|
|
else {
|
|
|
|
// FIXME: special format error returned for page faults ?
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR EXT = 1;
|
|
|
|
|
|
|
|
/* if we've already had 1st exception, see if 2nd causes a
|
|
|
|
* Double Fault instead. Otherwise, just record 1st exception
|
|
|
|
*/
|
|
|
|
if (BX_CPU_THIS_PTR errorno >= 2) {
|
|
|
|
if (is_exception_OK[BX_CPU_THIS_PTR curr_exception[0]][exception_type])
|
|
|
|
BX_CPU_THIS_PTR curr_exception[1] = exception_type;
|
2001-05-15 19:29:33 +04:00
|
|
|
else {
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR curr_exception[1] = BX_ET_DOUBLE_FAULT;
|
2006-01-31 20:41:08 +03:00
|
|
|
vector = BX_DF_EXCEPTION;
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
2001-05-15 19:29:33 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
|
|
|
BX_CPU_THIS_PTR curr_exception[0] = exception_type;
|
2001-05-15 19:29:33 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2006-02-01 21:12:08 +03:00
|
|
|
if (real_mode()) {
|
|
|
|
// not INT, no error code pushed
|
|
|
|
BX_CPU_THIS_PTR interrupt(vector, 0, 0, 0);
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR errorno = 0; // error resolved
|
|
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
2005-02-02 00:17:57 +03:00
|
|
|
}
|
2006-02-01 21:12:08 +03:00
|
|
|
else {
|
|
|
|
BX_CPU_THIS_PTR interrupt(vector, 0, push_error, error_code);
|
2001-04-10 05:04:59 +04:00
|
|
|
BX_CPU_THIS_PTR errorno = 0; // error resolved
|
|
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
2004-07-12 23:20:55 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|