Fixed bug in interrupt function in real mode
Style change Update CHANGES Remove patch.v8086-exception.lightcone because it already in CVS
This commit is contained in:
Stanislav Shwartsman
parent
a16fbc293a
commit
3fdbf48a69
@ -190,6 +190,9 @@ Changes to next release:
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[1093796] Fix for bug #1093786 (Nigel Horne)
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[1082584] The start of Bus mice and USB mice by Ben Lunt
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[1104695] msvc6 compatibility update (Royce Mitchell III)
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[1059199] VGA text font bug fix
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[1108001] Null pointer on bx_atexit() (Ben Lunt)
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[1112093] Fixed mouse cursor remain area drawing
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- SF patches partially applied
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[896733] Lazy flags, for more instructions, only 1 src op
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@ -201,6 +204,10 @@ Changes to next release:
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- patch.apic-zwane (APIC fixes) (Zwane Mwaikambo)
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- these S.F. bugs were closed
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#549793 flaw in interrupt gate handling(exception.cc)
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#692055 SMP Error
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#805479 Booting from disk causes illegal instruction warnings
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#909677 pc-speaker doesn't work
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#831751 behaviour unrealistic
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#661213 CR4.TSD is broken
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#685508 PANIC: prefetch: RIP > CS.limit
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dbg_main.cc,v 1.13 2005-01-05 19:50:54 vruppert Exp $
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// $Id: dbg_main.cc,v 1.14 2005-02-01 21:17:38 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -5908,5 +5908,5 @@ bx_dbg_info_flags(void)
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dbg_printf ("CF");
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dbg_printf ("\n");
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}
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#endif /* if BX_DEBUGGER */
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#endif /* if BX_DEBUGGER */
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.cc,v 1.37 2005-01-13 19:03:36 sshwarts Exp $
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// $Id: apic.cc,v 1.38 2005-02-01 21:17:51 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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@ -224,8 +224,7 @@ bx_bool bx_generic_apic_c::deliver (Bit8u dest, Bit8u dest_mode, Bit8u delivery_
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case APIC_DM_INIT:
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// normal INIT IPI sent to processors
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for (i = 0; i < BX_LOCAL_APIC_NUM; i++) {
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if (deliver_bitmask & (1<<i))
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local_apic_index[i]->init();
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if (deliver_bitmask & (1<<i)) local_apic_index[i]->init();
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}
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// HACK! We need to do some IOAPIC init after the CPUs
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// are fired up
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@ -234,8 +233,8 @@ bx_bool bx_generic_apic_c::deliver (Bit8u dest, Bit8u dest_mode, Bit8u delivery_
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case APIC_DM_EXTINT:
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for (int i = 0; i < BX_LOCAL_APIC_NUM; i++)
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if (deliver_bitmask & (1<<i))
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local_apic_index[i]->bypass_irr_isr = true;
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if (deliver_bitmask & (1<<i))
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local_apic_index[i]->bypass_irr_isr = true;
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break;
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case APIC_DM_SMI:
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case APIC_DM_NMI:
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: exception.cc,v 1.44 2004-11-04 22:41:23 sshwarts Exp $
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// $Id: exception.cc,v 1.45 2005-02-01 21:17:53 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -48,8 +48,7 @@ static const bx_bool is_exception_OK[3][3] = {
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};
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void
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BX_CPU_C::interrupt(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
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void BX_CPU_C::interrupt(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
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{
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#if BX_DEBUGGER
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if (bx_guard.special_unwind_stack) {
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@ -80,15 +79,16 @@ BX_CPU_C::interrupt(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u
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BX_DEBUG(("interrupt(): vector = %u, INT = %u, EXT = %u",
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(unsigned) vector, (unsigned) is_INT, (unsigned) BX_CPU_THIS_PTR EXT));
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BX_CPU_THIS_PTR save_cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS];
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BX_CPU_THIS_PTR save_ss = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS];
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BX_CPU_THIS_PTR save_eip = EIP;
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BX_CPU_THIS_PTR save_esp = ESP;
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BX_CPU_THIS_PTR save_cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS];
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BX_CPU_THIS_PTR save_ss = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS];
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BX_CPU_THIS_PTR save_eip = EIP;
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BX_CPU_THIS_PTR save_esp = ESP;
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// prev_errno = BX_CPU_THIS_PTR errorno;
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR msr.lma) {
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if (BX_CPU_THIS_PTR msr.lma)
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{
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// long mode interrupt
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Bit64u idtindex;
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@ -112,10 +112,10 @@ BX_CPU_THIS_PTR save_esp = ESP;
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BX_DEBUG(("interrupt(): vector > idtr.limit"));
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exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
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}
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}
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// descriptor AR byte must indicate interrupt gate, trap gate,
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// or task gate, else #GP(vector*8 + 2 + EXT)
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idtindex += BX_CPU_THIS_PTR idtr.base;
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access_linear(idtindex, 4, 0, BX_READ, &dword1);
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@ -124,10 +124,12 @@ BX_CPU_THIS_PTR save_esp = ESP;
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parse_descriptor(dword1, dword2, &gate_descriptor);
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if ( (gate_descriptor.valid==0) || gate_descriptor.segment) {
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if ((gate_descriptor.valid==0) || gate_descriptor.segment)
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{
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BX_DEBUG(("interrupt(): gate descriptor is not valid sys seg"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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}
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}
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switch (gate_descriptor.type) {
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//case 5: // task gate
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//case 6: // 286 interrupt gate
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@ -140,22 +142,23 @@ BX_CPU_THIS_PTR save_esp = ESP;
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(unsigned) gate_descriptor.type));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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return;
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}
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}
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// if software interrupt, then gate descripor DPL must be >= CPL,
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// else #GP(vector * 8 + 2 + EXT)
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if (is_INT && (gate_descriptor.dpl < CPL)) {
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/* ??? */
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if (is_INT && (gate_descriptor.dpl < CPL))
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{
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BX_DEBUG(("interrupt(): is_INT && (dpl < CPL)"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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return;
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}
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}
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// Gate must be present, else #NP(vector * 8 + 2 + EXT)
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if (gate_descriptor.p == 0) {
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BX_DEBUG(("interrupt(): p == 0"));
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exception(BX_NP_EXCEPTION, vector*8 + 2, 0);
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}
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}
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gate_dest_selector = gate_descriptor.u.gate386.dest_selector;
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gate_dest_offset = ((Bit64u)dword3 << 32) +
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gate_descriptor.u.gate386.dest_offset;
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@ -167,7 +170,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
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if ( (gate_dest_selector & 0xfffc) == 0 ) {
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BX_PANIC(("int_trap_gate(): selector null"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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parse_selector(gate_dest_selector, &cs_selector);
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@ -187,6 +190,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
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BX_DEBUG(("interrupt(): not code segment"));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
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}
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// check that it's a 64 bit segment
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if ( cs_descriptor.u.segment.l == 0 ||
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cs_descriptor.u.segment.d_b == 1)
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@ -217,7 +221,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
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if (ist > 0) {
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BX_DEBUG(("trap to IST, vector = %d\n",ist));
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get_RSP_from_TSS(ist+3,&RSP_for_cpl_x);
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}
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}
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else {
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get_RSP_from_TSS(cs_descriptor.dpl,&RSP_for_cpl_x);
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}
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@ -276,7 +280,6 @@ BX_CPU_THIS_PTR save_esp = ESP;
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RIP = gate_dest_offset;
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// if INTERRUPT GATE set IF to 0
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if ( !(gate_descriptor.type & 1) ) // even is int-gate
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BX_CPU_THIS_PTR clear_IF ();
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@ -289,7 +292,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
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// if code segment is conforming OR code segment DPL = CPL then
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// INTERRUPT TO SAME PRIVILEGE LEVEL:
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if (cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL )
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if (cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL)
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{
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BX_DEBUG(("int_trap_gate286(): INTERRUPT TO SAME PRIVILEGE"));
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@ -367,15 +370,15 @@ BX_CPU_THIS_PTR save_esp = ESP;
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parse_descriptor(dword1, dword2, &gate_descriptor);
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if ( (gate_descriptor.valid==0) || gate_descriptor.segment) {
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if ((gate_descriptor.valid==0) || gate_descriptor.segment) {
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BX_DEBUG(("interrupt(): gate descriptor is not valid sys seg"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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}
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}
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switch (gate_descriptor.type) {
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case 5: // task gate
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case 6: // 286 interrupt gate
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case 7: // 286 trap gate
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case 5: // task gate
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case 6: // 286 interrupt gate
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case 7: // 286 trap gate
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case 14: // 386 interrupt gate
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case 15: // 386 trap gate
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break;
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@ -388,18 +391,16 @@ BX_CPU_THIS_PTR save_esp = ESP;
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// if software interrupt, then gate descripor DPL must be >= CPL,
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// else #GP(vector * 8 + 2 + EXT)
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if (is_INT && (gate_descriptor.dpl < CPL)) {
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/* ??? */
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if (is_INT && (gate_descriptor.dpl < CPL)) {
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BX_DEBUG(("interrupt(): is_INT && (dpl < CPL)"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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return;
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}
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}
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// Gate must be present, else #NP(vector * 8 + 2 + EXT)
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if (gate_descriptor.p == 0) {
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BX_DEBUG(("interrupt(): p == 0"));
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BX_DEBUG(("interrupt(): gate not present"));
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exception(BX_NP_EXCEPTION, vector*8 + 2, 0);
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}
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}
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switch (gate_descriptor.type) {
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case 5: // 286/386 task gate
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@ -409,14 +410,14 @@ BX_CPU_THIS_PTR save_esp = ESP;
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// must specify global in the local/global bit,
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// else #TS(TSS selector)
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// +++
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// 486/Pent books say #TSS(selector)
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// PPro+ says #GP(selector)
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// +++
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// 486/Pent books say #TSS(selector)
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// PPro+ says #GP(selector)
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if (tss_selector.ti) {
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BX_PANIC(("interrupt: tss_selector.ti=1"));
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exception(BX_TS_EXCEPTION, raw_tss_selector & 0xfffc, 0);
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return;
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}
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}
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// index must be within GDT limits, else #TS(TSS selector)
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fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
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@ -424,16 +425,17 @@ BX_CPU_THIS_PTR save_esp = ESP;
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// AR byte must specify available TSS,
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// else #TS(TSS selector)
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parse_descriptor(dword1, dword2, &tss_descriptor);
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if (tss_descriptor.valid==0 || tss_descriptor.segment) {
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BX_PANIC(("exception: TSS selector points to bad TSS"));
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exception(BX_TS_EXCEPTION, raw_tss_selector & 0xfffc, 0);
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return;
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}
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}
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if (tss_descriptor.type!=9 && tss_descriptor.type!=1) {
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BX_PANIC(("exception: TSS selector points to bad TSS"));
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exception(BX_TS_EXCEPTION, raw_tss_selector & 0xfffc, 0);
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return;
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}
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}
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// TSS must be present, else #NP(TSS selector)
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// done in task_switch()
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@ -453,7 +455,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
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push_32(error_code);
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else
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push_16(error_code);
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}
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}
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// instruction pointer must be in CS limit, else #GP(0)
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if (EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
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@ -463,32 +465,31 @@ BX_CPU_THIS_PTR save_esp = ESP;
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return;
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case 6: // 286 interrupt gate
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case 7: // 286 trap gate
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case 6: // 286 interrupt gate
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case 7: // 286 trap gate
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case 14: // 386 interrupt gate
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case 15: // 386 trap gate
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if ( gate_descriptor.type >= 14 ) { // 386 gate
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gate_dest_selector = gate_descriptor.u.gate386.dest_selector;
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gate_dest_offset = gate_descriptor.u.gate386.dest_offset;
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}
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}
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else { // 286 gate
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gate_dest_selector = gate_descriptor.u.gate286.dest_selector;
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gate_dest_offset = gate_descriptor.u.gate286.dest_offset;
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}
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}
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// examine CS selector and descriptor given in gate descriptor
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// selector must be non-null else #GP(EXT)
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if ( (gate_dest_selector & 0xfffc) == 0 ) {
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BX_PANIC(("int_trap_gate(): selector null"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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parse_selector(gate_dest_selector, &cs_selector);
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// selector must be within its descriptor table limits
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// else #GP(selector+EXT)
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2,
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BX_GP_EXCEPTION);
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &cs_descriptor);
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// descriptor AR byte must indicate code seg
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@ -496,20 +497,22 @@ BX_CPU_THIS_PTR save_esp = ESP;
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if ( cs_descriptor.valid==0 ||
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cs_descriptor.segment==0 ||
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cs_descriptor.u.segment.executable==0 ||
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cs_descriptor.dpl>CPL ) {
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cs_descriptor.dpl>CPL )
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{
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BX_DEBUG(("interrupt(): not code segment"));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
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}
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}
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// segment must be present, else #NP(selector + EXT)
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if ( cs_descriptor.p==0 ) {
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BX_DEBUG(("interrupt(): segment not present"));
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exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc, 0);
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}
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}
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// if code segment is non-conforming and DPL < CPL then
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// INTERRUPT TO INNER PRIVILEGE:
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if ( cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl<CPL ) {
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if ( cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl<CPL )
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{
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Bit16u old_SS, old_CS, SS_for_cpl_x;
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Bit32u ESP_for_cpl_x, old_EIP, old_ESP;
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bx_descriptor_t ss_descriptor;
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@ -527,14 +530,13 @@ BX_CPU_THIS_PTR save_esp = ESP;
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BX_PANIC(("interrupt(): SS selector null"));
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/* TS(ext) */
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exception(BX_TS_EXCEPTION, 0, 0);
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}
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}
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// selector index must be within its descriptor table limits
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// else #TS(SS selector + EXT)
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parse_selector(SS_for_cpl_x, &ss_selector);
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// fetch 2 dwords of descriptor; call handles out of limits checks
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fetch_raw_descriptor(&ss_selector, &dword1, &dword2,
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BX_TS_EXCEPTION);
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fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
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parse_descriptor(dword1, dword2, &ss_descriptor);
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// selector rpl must = dpl of code segment,
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@ -542,30 +544,31 @@ BX_CPU_THIS_PTR save_esp = ESP;
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if (ss_selector.rpl != cs_descriptor.dpl) {
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BX_PANIC(("interrupt(): SS.rpl != CS.dpl"));
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exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
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}
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}
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// stack seg DPL must = DPL of code segment,
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// else #TS(SS selector + ext)
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if (ss_descriptor.dpl != cs_descriptor.dpl) {
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BX_PANIC(("interrupt(): SS.dpl != CS.dpl"));
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exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
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}
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}
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// descriptor must indicate writable data segment,
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// else #TS(SS selector + EXT)
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if (ss_descriptor.valid==0 ||
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ss_descriptor.segment==0 ||
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ss_descriptor.u.segment.executable==1 ||
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ss_descriptor.u.segment.r_w==0) {
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ss_descriptor.u.segment.r_w==0)
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{
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BX_PANIC(("interrupt(): SS not writable data segment"));
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exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
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}
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}
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// seg must be present, else #SS(SS selector + ext)
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if (ss_descriptor.p==0) {
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BX_PANIC(("interrupt(): SS not present"));
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exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
||||
}
|
||||
}
|
||||
|
||||
if (gate_descriptor.type>=14) {
|
||||
// 386 int/trap gate
|
||||
@ -576,7 +579,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
bytes = 20;
|
||||
if (v8086_mode())
|
||||
bytes += 16;
|
||||
}
|
||||
}
|
||||
else {
|
||||
// new stack must have room for 10|12 bytes, else #SS(0)
|
||||
if ( is_error_code )
|
||||
@ -586,18 +589,17 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
if (v8086_mode()) {
|
||||
bytes += 8;
|
||||
BX_PANIC(("interrupt: int/trap gate VM"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// 486,Pentium books
|
||||
// new stack must have room for 10/12 bytes, else #SS(0) 486 book
|
||||
// PPro+
|
||||
// new stack must have room for 10/12 bytes, else #SS(seg selector)
|
||||
if ( !can_push(&ss_descriptor, ESP_for_cpl_x, bytes) ) {
|
||||
BX_PANIC(("interrupt(): new stack doesn't have room for %u bytes",
|
||||
(unsigned) bytes));
|
||||
// SS(???)
|
||||
exception(BX_SS_EXCEPTION, 0, 0);
|
||||
// 486,Pentium books
|
||||
// new stack must have room for 10/12 bytes, else #SS(0) 486 book
|
||||
// PPro+
|
||||
// new stack must have room for 10/12 bytes, else #SS(seg selector)
|
||||
if ( !can_push(&ss_descriptor, ESP_for_cpl_x, bytes) )
|
||||
{
|
||||
BX_PANIC(("interrupt(): new stack doesn't have room for %u bytes", (unsigned) bytes));
|
||||
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
||||
}
|
||||
|
||||
// IP must be within CS segment boundaries, else #GP(0)
|
||||
@ -617,7 +619,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
if (ss_descriptor.u.segment.d_b)
|
||||
ESP = ESP_for_cpl_x;
|
||||
else
|
||||
SP = ESP_for_cpl_x; // leave upper 16bits
|
||||
SP = ESP_for_cpl_x; // leave upper 16bits
|
||||
|
||||
// load new CS:IP values from gate
|
||||
// set CPL to new code segment DPL
|
||||
@ -651,7 +653,8 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// push long pointer to old stack onto new stack
|
||||
push_32(old_SS);
|
||||
push_32(old_ESP);
|
||||
@ -665,11 +668,11 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
|
||||
if ( is_error_code )
|
||||
push_32(error_code);
|
||||
}
|
||||
}
|
||||
else { // 286 int/trap gate
|
||||
if (is_v8086_mode) {
|
||||
BX_PANIC(("286 int/trap gate, VM"));
|
||||
}
|
||||
}
|
||||
// push long pointer to old stack onto new stack
|
||||
push_16(old_SS);
|
||||
push_16(old_ESP); // ignores upper 16bits
|
||||
@ -683,18 +686,19 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
|
||||
if ( is_error_code )
|
||||
push_16(error_code);
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (v8086_mode()) {
|
||||
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
||||
}
|
||||
}
|
||||
|
||||
// if code segment is conforming OR code segment DPL = CPL then
|
||||
// INTERRUPT TO SAME PRIVILEGE LEVEL:
|
||||
if ( cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL ) {
|
||||
if ( cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL )
|
||||
{
|
||||
int bytes;
|
||||
Bit32u temp_ESP;
|
||||
|
||||
@ -711,13 +715,13 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
bytes = 16;
|
||||
else
|
||||
bytes = 12;
|
||||
}
|
||||
}
|
||||
else { // 286 gate
|
||||
if ( is_error_code )
|
||||
bytes = 8;
|
||||
else
|
||||
bytes = 6;
|
||||
}
|
||||
}
|
||||
|
||||
if (! can_push(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, temp_ESP, bytes))
|
||||
{
|
||||
@ -729,7 +733,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
|
||||
BX_ERROR(("interrupt(): IP > cs descriptor limit"));
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
}
|
||||
}
|
||||
|
||||
// push flags onto stack
|
||||
// push current CS selector onto stack
|
||||
@ -740,14 +744,14 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
push_32(EIP);
|
||||
if ( is_error_code )
|
||||
push_32(error_code);
|
||||
}
|
||||
}
|
||||
else { // 286 gate
|
||||
push_16(read_flags());
|
||||
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
||||
push_16(IP);
|
||||
if ( is_error_code )
|
||||
push_16(error_code);
|
||||
}
|
||||
}
|
||||
|
||||
// load CS:IP from gate
|
||||
// load CS descriptor
|
||||
@ -763,7 +767,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
BX_CPU_THIS_PTR clear_VM ();
|
||||
BX_CPU_THIS_PTR clear_RF ();
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// else #GP(CS selector + ext)
|
||||
BX_DEBUG(("interrupt: bad descriptor"));
|
||||
@ -778,15 +782,18 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
default:
|
||||
BX_PANIC(("bad descriptor type in interrupt()!"));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{ /* real mode */
|
||||
{ /* real mode */
|
||||
Bit16u cs_selector, ip;
|
||||
|
||||
if ( (vector*4+3) > BX_CPU_THIS_PTR idtr.limit )
|
||||
BX_PANIC(("interrupt(real mode) vector > limit"));
|
||||
{
|
||||
BX_ERROR(("interrupt(real mode) vector > idtr.limit"));
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
}
|
||||
|
||||
push_16(read_flags());
|
||||
|
||||
@ -796,7 +803,7 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
push_16(ip);
|
||||
|
||||
access_linear(BX_CPU_THIS_PTR idtr.base + 4 * vector, 2, 0, BX_READ, &ip);
|
||||
IP = ip;
|
||||
EIP = (Bit32u) ip;
|
||||
access_linear(BX_CPU_THIS_PTR idtr.base + 4 * vector + 2, 2, 0, BX_READ, &cs_selector);
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_selector);
|
||||
|
||||
@ -807,13 +814,12 @@ BX_CPU_THIS_PTR save_esp = ESP;
|
||||
BX_CPU_THIS_PTR clear_AC ();
|
||||
#endif
|
||||
BX_CPU_THIS_PTR clear_RF ();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
|
||||
// vector: 0..255: vector in IDT
|
||||
// error_code: if exception generates and error, push this error code
|
||||
// vector: 0..255: vector in IDT
|
||||
// error_code: if exception generates and error, push this error code
|
||||
void BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
|
||||
{
|
||||
bx_bool push_error;
|
||||
Bit8u exception_type;
|
||||
@ -826,7 +832,7 @@ BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
|
||||
if (bx_guard.special_unwind_stack) {
|
||||
BX_INFO (("exception() returning early because special_unwind_stack is set"));
|
||||
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if BX_EXTERNAL_DEBUGGER
|
||||
@ -844,7 +850,7 @@ BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS] = BX_CPU_THIS_PTR save_ss;
|
||||
EIP = BX_CPU_THIS_PTR save_eip;
|
||||
ESP = BX_CPU_THIS_PTR save_esp;
|
||||
}
|
||||
}
|
||||
|
||||
BX_CPU_THIS_PTR errorno++;
|
||||
if (BX_CPU_THIS_PTR errorno >= 3) {
|
||||
@ -1001,12 +1007,12 @@ BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
|
||||
push_error = 0; // keep compiler happy for now
|
||||
exception_type = 0; // keep compiler happy for now
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (exception_type != BX_ET_PAGE_FAULT) {
|
||||
// Page faults have different format
|
||||
error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
|
||||
}
|
||||
}
|
||||
BX_CPU_THIS_PTR EXT = 1;
|
||||
|
||||
/* if we've already had 1st exception, see if 2nd causes a
|
||||
@ -1049,7 +1055,7 @@ BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
|
||||
// }
|
||||
BX_CPU_THIS_PTR errorno = 0; // error resolved
|
||||
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
||||
}
|
||||
}
|
||||
else // real mode
|
||||
#endif
|
||||
{
|
||||
@ -1142,7 +1148,7 @@ SYSCALL_LEGACY_MODE:
|
||||
bx_address temp_RIP;
|
||||
bx_descriptor_t cs_descriptor,ss_descriptor;
|
||||
bx_selector_t cs_selector,ss_selector;
|
||||
Bit32u dword1, dword2;
|
||||
Bit32u dword1, dword2;
|
||||
|
||||
if (!BX_CPU_THIS_PTR msr.sce) {
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
@ -1326,4 +1332,5 @@ SYSRET_NON_64BIT_MODE:
|
||||
RIP = temp_RIP;
|
||||
}
|
||||
}
|
||||
|
||||
#endif // BX_SUPPORT_X86_64
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: segment_ctrl_pro.cc,v 1.29 2004-11-14 19:29:34 sshwarts Exp $
|
||||
// $Id: segment_ctrl_pro.cc,v 1.30 2005-02-01 21:17:54 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -25,18 +25,11 @@
|
||||
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define NEED_CPU_REG_SHORTCUTS 1
|
||||
#include "bochs.h"
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void BX_CPP_AttrRegparmN(2)
|
||||
BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
{
|
||||
@ -72,7 +65,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
seg->cache.u.segment.avl = 0;
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if BX_CPU_LEVEL >= 2
|
||||
@ -88,7 +81,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
BX_ERROR(("load_seg_reg: SS: new_value == 0"));
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
index = new_value >> 3;
|
||||
ti = (new_value >> 2) & 0x01;
|
||||
@ -102,35 +95,35 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
BX_CPU_THIS_PTR strseg(seg), (unsigned) index, (unsigned) BX_CPU_THIS_PTR gdtr.limit));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
access_linear(BX_CPU_THIS_PTR gdtr.base + index*8, 4, 0,
|
||||
BX_READ, &dword1);
|
||||
access_linear(BX_CPU_THIS_PTR gdtr.base + index*8 + 4, 4, 0,
|
||||
BX_READ, &dword2);
|
||||
}
|
||||
}
|
||||
else { /* LDT */
|
||||
if (BX_CPU_THIS_PTR ldtr.cache.valid==0) { /* ??? */
|
||||
BX_ERROR(("load_seg_reg: LDT invalid"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
if ((index*8 + 7) > BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit) {
|
||||
BX_ERROR(("load_seg_reg ss: LDT: index > limit"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.ldt.base + index*8, 4, 0,
|
||||
BX_READ, &dword1);
|
||||
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.ldt.base + index*8 + 4, 4, 0,
|
||||
BX_READ, &dword2);
|
||||
}
|
||||
}
|
||||
|
||||
/* selector's RPL must = CPL, else #GP(selector) */
|
||||
if (rpl != CPL) {
|
||||
BX_ERROR(("load_seg_reg(): rpl != CPL"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
parse_descriptor(dword1, dword2, &descriptor);
|
||||
|
||||
@ -138,56 +131,58 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
BX_ERROR(("load_seg_reg(): valid bit cleared"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* AR byte must indicate a writable data segment else #GP(selector) */
|
||||
if ( (descriptor.segment==0) ||
|
||||
descriptor.u.segment.executable ||
|
||||
descriptor.u.segment.r_w==0 ) {
|
||||
descriptor.u.segment.r_w==0 )
|
||||
{
|
||||
BX_ERROR(("load_seg_reg(): not writable data segment"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* DPL in the AR byte must equal CPL else #GP(selector) */
|
||||
if (descriptor.dpl != CPL) {
|
||||
BX_ERROR(("load_seg_reg(): dpl != CPL"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* segment must be marked PRESENT else #SS(selector) */
|
||||
if (descriptor.p == 0) {
|
||||
BX_ERROR(("load_seg_reg(): not present"));
|
||||
exception(BX_SS_EXCEPTION, new_value & 0xfffc, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* load SS with selector, load SS cache with descriptor */
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = new_value;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index = index;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti = ti;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = rpl;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache = descriptor;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = new_value;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index = index;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti = ti;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = rpl;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache = descriptor;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
|
||||
|
||||
/* now set accessed bit in descriptor */
|
||||
dword2 |= 0x0100;
|
||||
if (ti == 0) { /* GDT */
|
||||
access_linear(BX_CPU_THIS_PTR gdtr.base + index*8 + 4, 4, 0,
|
||||
BX_WRITE, &dword2);
|
||||
}
|
||||
}
|
||||
else { /* LDT */
|
||||
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.ldt.base + index*8 + 4, 4, 0,
|
||||
BX_WRITE, &dword2);
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
else if ( (seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS]) ||
|
||||
(seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES])
|
||||
#if BX_CPU_LEVEL >= 3
|
||||
|| (seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS]) ||
|
||||
(seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS])
|
||||
#endif
|
||||
) {
|
||||
)
|
||||
{
|
||||
Bit16u index;
|
||||
Bit8u ti;
|
||||
Bit8u rpl;
|
||||
@ -202,7 +197,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
seg->selector.value = 0;
|
||||
seg->cache.valid = 0; /* invalidate null selector */
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
index = new_value >> 3;
|
||||
ti = (new_value >> 2) & 0x01;
|
||||
@ -216,28 +211,28 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
BX_CPU_THIS_PTR strseg(seg), (unsigned) index, (unsigned) BX_CPU_THIS_PTR gdtr.limit));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
access_linear(BX_CPU_THIS_PTR gdtr.base + index*8, 4, 0,
|
||||
BX_READ, &dword1);
|
||||
access_linear(BX_CPU_THIS_PTR gdtr.base + index*8 + 4, 4, 0,
|
||||
BX_READ, &dword2);
|
||||
}
|
||||
}
|
||||
else { /* LDT */
|
||||
if (BX_CPU_THIS_PTR ldtr.cache.valid==0) {
|
||||
BX_ERROR(("load_seg_reg: LDT invalid"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
if ((index*8 + 7) > BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit) {
|
||||
BX_ERROR(("load_seg_reg ds,es: LDT: index > limit"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.ldt.base + index*8, 4, 0,
|
||||
BX_READ, &dword1);
|
||||
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.ldt.base + index*8 + 4, 4, 0,
|
||||
BX_READ, &dword2);
|
||||
}
|
||||
}
|
||||
|
||||
parse_descriptor(dword1, dword2, &descriptor);
|
||||
|
||||
@ -245,43 +240,45 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
BX_ERROR(("load_seg_reg(): valid bit cleared"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* AR byte must indicate data or readable code segment else #GP(selector) */
|
||||
if ( descriptor.segment==0 ||
|
||||
(descriptor.u.segment.executable==1 &&
|
||||
descriptor.u.segment.r_w==0) ) {
|
||||
descriptor.u.segment.r_w==0) )
|
||||
{
|
||||
BX_ERROR(("load_seg_reg(): not data or readable code"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* If data or non-conforming code, then both the RPL and the CPL
|
||||
* must be less than or equal to DPL in AR byte else #GP(selector) */
|
||||
if ( descriptor.u.segment.executable==0 ||
|
||||
descriptor.u.segment.c_ed==0 ) {
|
||||
descriptor.u.segment.c_ed==0 )
|
||||
{
|
||||
if ((rpl > descriptor.dpl) || (CPL > descriptor.dpl)) {
|
||||
BX_ERROR(("load_seg_reg: RPL & CPL must be <= DPL"));
|
||||
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* segment must be marked PRESENT else #NP(selector) */
|
||||
if (descriptor.p == 0) {
|
||||
BX_ERROR(("load_seg_reg: segment not present"));
|
||||
exception(BX_NP_EXCEPTION, new_value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* load segment register with selector */
|
||||
/* load segment register-cache with descriptor */
|
||||
seg->selector.value = new_value;
|
||||
seg->selector.index = index;
|
||||
seg->selector.ti = ti;
|
||||
seg->selector.rpl = rpl;
|
||||
seg->cache = descriptor;
|
||||
seg->cache.valid = 1;
|
||||
seg->selector.value = new_value;
|
||||
seg->selector.index = index;
|
||||
seg->selector.ti = ti;
|
||||
seg->selector.rpl = rpl;
|
||||
seg->cache = descriptor;
|
||||
seg->cache.valid = 1;
|
||||
|
||||
/* now set accessed bit in descriptor */
|
||||
/* wmr: don't bother if it's already set (thus allowing */
|
||||
@ -299,12 +296,12 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
else {
|
||||
BX_PANIC(("load_seg_reg(): invalid segment register passed!"));
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* real mode */
|
||||
/* seg->limit = ; ??? different behaviours depening on seg reg. */
|
||||
@ -346,7 +343,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
|
||||
seg->cache.segment = 1; /* regular segment */
|
||||
seg->cache.u.segment.a = 1; /* accessed */
|
||||
/* set G, D_B, AVL bits here ??? */
|
||||
}
|
||||
}
|
||||
#else /* 8086 */
|
||||
|
||||
seg->selector.value = new_value;
|
||||
@ -406,8 +403,7 @@ BX_CPU_C::parse_descriptor(Bit32u dword1, Bit32u dword2, bx_descriptor_t *temp)
|
||||
temp->u.segment.a = (AR_byte >> 0) & 0x01;
|
||||
|
||||
temp->u.segment.limit = (dword1 & 0xffff);
|
||||
temp->u.segment.base = (dword1 >> 16) |
|
||||
((dword2 & 0xFF) << 16);
|
||||
temp->u.segment.base = (dword1 >> 16) | ((dword2 & 0xFF) << 16);
|
||||
|
||||
#if BX_CPU_LEVEL >= 3
|
||||
temp->u.segment.limit |= (dword2 & 0x000F0000);
|
||||
@ -430,7 +426,7 @@ BX_CPU_C::parse_descriptor(Bit32u dword1, Bit32u dword2, bx_descriptor_t *temp)
|
||||
temp->u.segment.limit_scaled = temp->u.segment.limit;
|
||||
|
||||
temp->valid = 1;
|
||||
}
|
||||
}
|
||||
else { // system & gate segment descriptors
|
||||
switch ( temp->type ) {
|
||||
case 0: // reserved
|
||||
@ -441,14 +437,12 @@ BX_CPU_C::parse_descriptor(Bit32u dword1, Bit32u dword2, bx_descriptor_t *temp)
|
||||
break;
|
||||
case 1: // 286 TSS (available)
|
||||
case 3: // 286 TSS (busy)
|
||||
temp->u.tss286.base = (dword1 >> 16) |
|
||||
((dword2 & 0xff) << 16);
|
||||
temp->u.tss286.base = (dword1 >> 16) | ((dword2 & 0xff) << 16);
|
||||
temp->u.tss286.limit = (dword1 & 0xffff);
|
||||
temp->valid = 1;
|
||||
break;
|
||||
case 2: // LDT descriptor
|
||||
temp->u.ldt.base = (dword1 >> 16) |
|
||||
((dword2 & 0xFF) << 16);
|
||||
temp->u.ldt.base = (dword1 >> 16) | ((dword2 & 0xFF) << 16);
|
||||
#if BX_CPU_LEVEL >= 3
|
||||
temp->u.ldt.base |= (dword2 & 0xff000000);
|
||||
#endif
|
||||
@ -497,11 +491,11 @@ BX_CPU_C::parse_descriptor(Bit32u dword1, Bit32u dword2, bx_descriptor_t *temp)
|
||||
temp->valid = 1;
|
||||
break;
|
||||
#endif
|
||||
default: BX_PANIC(("parse_descriptor(): case %d unfinished",
|
||||
(unsigned) temp->type));
|
||||
default:
|
||||
BX_PANIC(("parse_descriptor(): case %u unfinished", (unsigned) temp->type));
|
||||
temp->valid = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(2)
|
||||
@ -512,17 +506,17 @@ BX_CPU_C::load_ldtr(bx_selector_t *selector, bx_descriptor_t *descriptor)
|
||||
BX_CPU_THIS_PTR ldtr.selector = *selector;
|
||||
BX_CPU_THIS_PTR ldtr.cache.valid = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (!descriptor)
|
||||
BX_PANIC(("load_ldtr(): descriptor == NULL!"));
|
||||
BX_PANIC(("load_ldtr(): descriptor == NULL !"));
|
||||
|
||||
BX_CPU_THIS_PTR ldtr.cache = *descriptor; /* whole structure copy */
|
||||
BX_CPU_THIS_PTR ldtr.selector = *selector;
|
||||
|
||||
if (BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit < 7) {
|
||||
BX_PANIC(("load_ldtr(): ldtr.limit < 7"));
|
||||
}
|
||||
}
|
||||
|
||||
BX_CPU_THIS_PTR ldtr.cache.valid = 1;
|
||||
}
|
||||
@ -549,8 +543,8 @@ BX_CPU_C::load_cs(bx_selector_t *selector, bx_descriptor_t *descriptor,
|
||||
}
|
||||
else {
|
||||
BX_CPU_THIS_PTR cpu_mode = BX_MODE_LONG_COMPAT;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_ICACHE
|
||||
@ -572,14 +566,14 @@ BX_CPU_C::load_ss(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cp
|
||||
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
|
||||
loadSRegLMNominal(BX_SEG_REG_SS, selector->value, 0, cpl);
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
if ( (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value & 0xfffc) == 0 )
|
||||
BX_PANIC(("load_ss(): null selector passed"));
|
||||
|
||||
if ( !BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid ) {
|
||||
BX_PANIC(("load_ss(): invalid selector/descriptor passed."));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if BX_CPU_LEVEL >= 2
|
||||
@ -597,35 +591,33 @@ debug(BX_CPU_THIS_PTR prev_eip);
|
||||
BX_INFO(("-----------------------------------"));
|
||||
exception(exception_no, selector->value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
access_linear(BX_CPU_THIS_PTR gdtr.base + selector->index*8, 4, 0,
|
||||
BX_READ, dword1);
|
||||
access_linear(BX_CPU_THIS_PTR gdtr.base + selector->index*8 + 4, 4, 0,
|
||||
BX_READ, dword2);
|
||||
}
|
||||
}
|
||||
else { /* LDT */
|
||||
if (BX_CPU_THIS_PTR ldtr.cache.valid==0) {
|
||||
BX_PANIC(("fetch_raw_descriptor: LDTR.valid=0"));
|
||||
}
|
||||
}
|
||||
if ((selector->index*8 + 7) > BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit) {
|
||||
BX_ERROR(("fetch_raw_descriptor: LDT: index (%x)%x > limit (%x)",
|
||||
(selector->index*8 + 7), selector->index,
|
||||
BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit));
|
||||
exception(exception_no, selector->value & 0xfffc, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.ldt.base + selector->index*8, 4, 0,
|
||||
BX_READ, dword1);
|
||||
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.ldt.base + selector->index*8 + 4, 4, 0,
|
||||
BX_READ, dword2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
bx_bool BX_CPP_AttrRegparmN(3)
|
||||
BX_CPU_C::fetch_raw_descriptor2(bx_selector_t *selector,
|
||||
Bit32u *dword1, Bit32u *dword2)
|
||||
@ -638,7 +630,7 @@ BX_CPU_C::fetch_raw_descriptor2(bx_selector_t *selector,
|
||||
access_linear(BX_CPU_THIS_PTR gdtr.base + selector->index*8 + 4, 4, 0,
|
||||
BX_READ, dword2);
|
||||
return(1);
|
||||
}
|
||||
}
|
||||
else { /* LDT */
|
||||
if ((selector->index*8 + 7) > BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit)
|
||||
return(0);
|
||||
@ -647,5 +639,5 @@ BX_CPU_C::fetch_raw_descriptor2(bx_selector_t *selector,
|
||||
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.ldt.base + selector->index*8 + 4, 4, 0,
|
||||
BX_READ, dword2);
|
||||
return(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,121 +0,0 @@
|
||||
----------------------------------------------------------------------
|
||||
Patch name: patch.v8086-exception.lightcone
|
||||
Author: LightCone
|
||||
Date: Thu Aug 7 2003
|
||||
Status: Proposed
|
||||
|
||||
Detailed description:
|
||||
This is a reformat of SF patch #704181 CPU interrupt function
|
||||
|
||||
Here is what the author wrote:
|
||||
Since the bug of bochs-2.0.win32 was found and
|
||||
corrected, it reports. cpu/exception.cpp of src : Within
|
||||
an interrupt() function, when present is the V8086 mode,
|
||||
a bug is in the portion which processes 386 (286)
|
||||
int/trap gate. From the V8086 mode, this portion is
|
||||
performed, when it is going to execute an int imm
|
||||
command. The portion in which push_32 () is called in
|
||||
the state of VM=1 is still a mistake. Although this
|
||||
push_32 () tends to write in to the stack of a protected
|
||||
mode, if it is still VM=1 of EFLAGS, the
|
||||
write_virtual_dword() function called out of push_32 () will
|
||||
take out a segment protection exception. After
|
||||
performing clear_VM() etc., it is necessary to make it
|
||||
call push_32 () correctly, since EFLAGS is saved locally.
|
||||
|
||||
Patch was created with:
|
||||
cvs diff -u
|
||||
Apply patch to what version:
|
||||
cvs checked out on Thu Aug 7 2003
|
||||
Instructions:
|
||||
To patch, go to main bochs directory.
|
||||
Type "patch -p0 < THIS_PATCH_FILE".
|
||||
----------------------------------------------------------------------
|
||||
Index: cpu/exception.cc
|
||||
===================================================================
|
||||
RCS file: /cvsroot/bochs/bochs/cpu/exception.cc,v
|
||||
retrieving revision 1.33
|
||||
diff -u -r1.33 exception.cc
|
||||
--- cpu/exception.cc 26 Feb 2003 02:48:12 -0000 1.33
|
||||
+++ cpu/exception.cc 7 Aug 2003 09:02:24 -0000
|
||||
@@ -637,9 +637,23 @@
|
||||
// set RPL of CS to CPL
|
||||
load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
|
||||
EIP = gate_dest_offset;
|
||||
+
|
||||
+ // Modified by LightCone
|
||||
+ Bit32u old_EFLAGS= read_eflags();
|
||||
+ bx_bool bV8086Mode= v8086_mode();
|
||||
+
|
||||
+ // if INTERRUPT GATE set IF to 0
|
||||
+ if ( !(gate_descriptor.type & 1) ) {// even is int-gate
|
||||
+ BX_CPU_THIS_PTR clear_IF ();
|
||||
+ }
|
||||
+ BX_CPU_THIS_PTR clear_TF ();
|
||||
+ BX_CPU_THIS_PTR clear_VM ();
|
||||
+ BX_CPU_THIS_PTR clear_RF ();
|
||||
+ BX_CPU_THIS_PTR clear_NT ();
|
||||
+
|
||||
|
||||
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
||||
- if (v8086_mode()) {
|
||||
+ if (bV8086Mode) {
|
||||
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
||||
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
||||
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
||||
@@ -653,46 +667,43 @@
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0;
|
||||
}
|
||||
+
|
||||
// push long pointer to old stack onto new stack
|
||||
push_32(old_SS);
|
||||
push_32(old_ESP);
|
||||
|
||||
// push EFLAGS
|
||||
- push_32(read_eflags());
|
||||
+ push_32(old_EFLAGS);
|
||||
|
||||
// push long pointer to return address onto new stack
|
||||
push_32(old_CS);
|
||||
push_32(old_EIP);
|
||||
|
||||
- if ( is_error_code )
|
||||
+ if ( is_error_code ) {
|
||||
push_32(error_code);
|
||||
+ }
|
||||
}
|
||||
else { // 286 int/trap gate
|
||||
- if (v8086_mode()) {
|
||||
+ if (bV8086Mode) {
|
||||
BX_PANIC(("286 int/trap gate, VM"));
|
||||
}
|
||||
+
|
||||
// push long pointer to old stack onto new stack
|
||||
push_16(old_SS);
|
||||
push_16(old_ESP); // ignores upper 16bits
|
||||
|
||||
// push FLAGS
|
||||
- push_16(read_flags());
|
||||
+ push_16((Bit16u)old_EFLAGS);
|
||||
|
||||
// push return address onto new stack
|
||||
push_16(old_CS);
|
||||
push_16(old_EIP); // ignores upper 16bits
|
||||
|
||||
- if ( is_error_code )
|
||||
+ if ( is_error_code ) {
|
||||
push_16(error_code);
|
||||
+ }
|
||||
}
|
||||
|
||||
- // if INTERRUPT GATE set IF to 0
|
||||
- if ( !(gate_descriptor.type & 1) ) // even is int-gate
|
||||
- BX_CPU_THIS_PTR clear_IF ();
|
||||
- BX_CPU_THIS_PTR clear_TF ();
|
||||
- BX_CPU_THIS_PTR clear_VM ();
|
||||
- BX_CPU_THIS_PTR clear_RF ();
|
||||
- BX_CPU_THIS_PTR clear_NT ();
|
||||
return;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user