Latest round of patches/fixups to get 64 bit emulation further.
This is an interim update to allow others to test. We have userland code running!!! (up to a point) Able to start executing "sash" as /sbin/init in userland from linux 64 bit kernel until it crashes trying to access a null pointer. No kernel panics though, just a segfault loop.
This commit is contained in:
Peter Tattam
parent
faff1d8715
commit
b968c4e5c8
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.100 2002-10-07 22:51:57 kevinlawton Exp $
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// $Id: cpu.h,v 1.101 2002-10-08 14:43:18 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -2294,6 +2294,9 @@ union {
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BX_SMF void JCXZ64_Jb(bxInstruction_c *);
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#endif // #if BX_SUPPORT_X86_64
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BX_SMF void FXSAVE(bxInstruction_c *i);
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BX_SMF void FXRSTOR(bxInstruction_c *i);
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// mch added
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BX_SMF void INVLPG(bxInstruction_c *);
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BX_SMF void wait_for_interrupt();
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: exception.cc,v 1.27 2002-10-06 22:08:18 kevinlawton Exp $
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// $Id: exception.cc,v 1.28 2002-10-08 14:43:18 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -238,6 +238,9 @@ BX_CPU_THIS_PTR save_esp = ESP;
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// load new CS:IP values from gate
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// set CPL to new code segment DPL
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CPL = cs_descriptor.dpl;
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// set RPL of CS to CPL
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// push long pointer to old stack onto new stack
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.22 2002-10-04 17:04:32 kevinlawton Exp $
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// $Id: fetchdecode64.cc,v 1.23 2002-10-08 14:43:18 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -509,8 +509,8 @@ static BxOpcodeInfo_t BxOpcodeInfo64G9[8] = {
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};
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static BxOpcodeInfo_t BxOpcodeInfo64G15[8] = {
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/* 0 */ { 0, &BX_CPU_C::BxError },
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/* 1 */ { 0, &BX_CPU_C::BxError },
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/* 0 */ { 0, &BX_CPU_C::FXSAVE },
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/* 1 */ { 0, &BX_CPU_C::FXRSTOR },
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/* 2 */ { 0, &BX_CPU_C::BxError },
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/* 3 */ { 0, &BX_CPU_C::BxError },
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/* 4 */ { 0, &BX_CPU_C::BxError },
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@ -1055,7 +1055,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F E4 */ { 0, &BX_CPU_C::BxError },
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/* 0F E5 */ { BxAnotherMMX, &BX_CPU_C::PMULHW_PqQq }, /* MMX */
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/* 0F E6 */ { 0, &BX_CPU_C::BxError },
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/* 0F E7 */ { 0, &BX_CPU_C::BxError },
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/* 0F E7 */ { BxAnother, &BX_CPU_C::NOP }, // MOVNTQ
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/* 0F E8 */ { BxAnotherMMX, &BX_CPU_C::PSUBSB_PqQq }, /* MMX */
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/* 0F E9 */ { BxAnotherMMX, &BX_CPU_C::PSUBSW_PqQq }, /* MMX */
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/* 0F EA */ { 0, &BX_CPU_C::BxError },
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@ -1577,7 +1577,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F E4 */ { 0, &BX_CPU_C::BxError },
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/* 0F E5 */ { BxAnotherMMX, &BX_CPU_C::PMULHW_PqQq }, /* MMX */
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/* 0F E6 */ { 0, &BX_CPU_C::BxError },
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/* 0F E7 */ { 0, &BX_CPU_C::BxError },
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/* 0F E7 */ { BxAnother, &BX_CPU_C::NOP }, // MOVNTQ
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/* 0F E8 */ { BxAnotherMMX, &BX_CPU_C::PSUBSB_PqQq }, /* MMX */
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/* 0F E9 */ { BxAnotherMMX, &BX_CPU_C::PSUBSW_PqQq }, /* MMX */
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/* 0F EA */ { 0, &BX_CPU_C::BxError },
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@ -2098,7 +2098,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F E4 */ { 0, &BX_CPU_C::BxError },
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/* 0F E5 */ { BxAnotherMMX, &BX_CPU_C::PMULHW_PqQq }, /* MMX */
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/* 0F E6 */ { 0, &BX_CPU_C::BxError },
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/* 0F E7 */ { 0, &BX_CPU_C::BxError },
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/* 0F E7 */ { BxAnother, &BX_CPU_C::NOP }, // MOVNTQ
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/* 0F E8 */ { BxAnotherMMX, &BX_CPU_C::PSUBSB_PqQq }, /* MMX */
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/* 0F E9 */ { BxAnotherMMX, &BX_CPU_C::PSUBSW_PqQq }, /* MMX */
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/* 0F EA */ { 0, &BX_CPU_C::BxError },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: paging.cc,v 1.32 2002-10-03 04:53:53 bdenney Exp $
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// $Id: paging.cc,v 1.33 2002-10-08 14:43:18 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -524,6 +524,17 @@ BX_CPU_C::INVLPG(bxInstruction_c* i)
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// Operand must not be a register
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if (i->modC0()) {
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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#warning PRT: check this is right. instruction is "0F 01 F8" see AMD manual.
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if ((i->rm() == 0) && (i->nnn() == 7)) {
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BX_CPU_THIS_PTR SWAPGS(i);
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return;
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}
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}
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#endif
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BX_INFO(("INVLPG: op is a register"));
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UndefinedOpcode(i);
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}
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@ -964,6 +975,9 @@ page_fault_not_present:
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BX_CPU_THIS_PTR cr2 = laddr;
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// Invalidate TLB entry.
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BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = BX_INVALID_TLB_ENTRY;
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#if BX_EXTERNAL_DEBUGGER
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printf("page fault for address %08x%08x\n",(Bit32u)(laddr >> 32),(Bit32u)(laddr & 0xffffffff));
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#endif
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exception(BX_PF_EXCEPTION, error_code, 0);
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return(0); // keep compiler happy
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.55 2002-10-04 17:04:33 kevinlawton Exp $
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// $Id: proc_ctrl.cc,v 1.56 2002-10-08 14:43:18 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1919,7 +1919,7 @@ BX_CPU_C::SWAPGS(bxInstruction_c *i)
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}
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temp_GS_base = MSR_GSBASE;
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MSR_GSBASE = MSR_KERNELGSBASE;
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MSR_KERNELGSBASE = MSR_GSBASE;
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MSR_KERNELGSBASE = temp_GS_base;
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}
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#endif
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@ -2019,3 +2019,15 @@ BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size,
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return(0);
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}
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#endif
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void
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BX_CPU_C::FXSAVE(bxInstruction_c *i)
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{
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BX_ERROR(("FXSAVE is only a stub."));
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}
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void
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BX_CPU_C::FXRSTOR(bxInstruction_c *i)
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{
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BX_ERROR(("FXRSTOR is only a stub."));
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: protect_ctrl.cc,v 1.16 2002-09-25 14:09:08 ptrumpet Exp $
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// $Id: protect_ctrl.cc,v 1.17 2002-10-08 14:43:18 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -459,7 +459,7 @@ BX_CPU_C::LTR_Ew(bxInstruction_c *i)
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bx_descriptor_t descriptor;
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bx_selector_t selector;
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Bit16u raw_selector;
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Bit32u dword1, dword2;
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Bit32u dword1, dword2, dword3;
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/* #GP(0) if the current privilege level is not 0 */
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@ -499,6 +499,16 @@ BX_CPU_C::LTR_Ew(bxInstruction_c *i)
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parse_descriptor(dword1, dword2, &descriptor);
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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// set upper 32 bits of tss base
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access_linear(BX_CPU_THIS_PTR gdtr.base + selector.index*8 + 8, 4, 0,
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BX_READ, &dword3);
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descriptor.u.tss386.base |= ((Bit64u)dword3 << 32);
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}
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#endif
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/* #GP(selector) if object is not a TSS or is already busy */
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if ( (descriptor.valid==0) || descriptor.segment ||
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(descriptor.type!=1 && descriptor.type!=9) ) {
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@ -730,16 +740,6 @@ BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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#warning PRT: check this is right. instruction is "0F 01 F8" see AMD manual.
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if ((i->rm() == 0) && (i->nnn() == 7)) {
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BX_CPU_THIS_PTR SWAPGS(i);
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return;
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}
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}
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#endif
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/* undefined opcode exception */
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BX_PANIC(("SGDT_Ms: use of register is undefined opcode."));
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UndefinedOpcode(i);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: tasking.cc,v 1.15 2002-09-28 00:54:05 kevinlawton Exp $
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// $Id: tasking.cc,v 1.16 2002-10-08 14:43:18 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -984,7 +984,7 @@ BX_CPU_C::get_RSP_from_TSS(unsigned pl, Bit64u *rsp)
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BX_PANIC(("get_RSP_from_TSS: TR.cache invalid"));
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// 32-bit TSS
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Bit32u TSSstackaddr, save_upper;
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Bit32u TSSstackaddr;
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TSSstackaddr = 8*pl + 4;
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if ( (TSSstackaddr+7) >
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