Bochs/bochs/cpu/todo

TODO (know issues in CPU model):
-------------------------------

[!] The following 3DNow! instructions still not implemented:
	PF2IW_PqQq
	PFNACC_PqQq
	PFPNACC_PqQq
	PFCMPGE_PqQq
	PFCMPGT_PqQq
	PFCMPEQ_PqQq
	PFMIN_PqQq
	PFMAX_PqQq
	PFRCP_PqQq
	PFRSQRT_PqQq
	PFSUB_PqQq
	PFSUBR_PqQq
	PFADD_PqQq
	PFACC_PqQq,
	PFMUL_PqQq
	PFRCPIT1_PqQq
	PFRSQIT1_PqQq
	PFRCPIT2_PqQq

[!] CPUID does not report 3DNow! instruction set

[!] Some of APIC functionality still not implemented, for example

    - LVT pins handling
    - Filter interrupts according processor priority (PPR)

[!] REP NOP is PAUSE (on P4/XEON)

    When running in SMP mode, this means that we are in a spin loop.
    This processor should yield to the other one, as we are anyhow waiting
    for a lock, and any other processor is responsible for this.

[!] 32-bit linear address wrap when executing in legacy mode might be
    not implemented correctly for system memory accesses (like descriptor
    tables and etc)

[!] AMD and Intel x86_64 implementations are different.
    Currently Bochs emulation is according to Intel version.
    Do we need to support both ?

[!] VMX:

   - Dual-monitor treatment of SMIs and SMM not implemented yet
   - Posted Interrupts Processing is not implemented yet
   - MTF is not implemented yet

[!] SVM:

   - Decoding assists, pause filter, VMCB clean are not implemented yet
   - Advanced Virtual Interrupt Controller (AVIC) not implemented yet
   - More?

[!] AMD misaligned SSE mode should convert #GP on misaligned SSE access to #AC
    exception when #AC is enabled

[!] TODO: Convert CPUDB to plugins and search for them in runtime

[!] TODO: Find a way to implement HLE and RTM extensions

------------------------------------------------------------------------------------
[!] No plans for MPX, Intel Processor Trace, LWP.
    Their emulation would greatly affect emulation performance.
    Could be implemented through instrumentation if ***really*** needed.
------------------------------------------------------------------------------------
Add todo file to CPU 2005-08-10 23:04:19 +04:00			`TODO (know issues in CPU model):`
			`-------------------------------`

			`[!] The following 3DNow! instructions still not implemented:`
			`PF2IW_PqQq`
			`PFNACC_PqQq`
			`PFPNACC_PqQq`
			`PFCMPGE_PqQq`
			`PFCMPGT_PqQq`
			`PFCMPEQ_PqQq`
			`PFMIN_PqQq`
			`PFMAX_PqQq`
			`PFRCP_PqQq`
			`PFRSQRT_PqQq`
			`PFSUB_PqQq`
			`PFSUBR_PqQq`
			`PFADD_PqQq`
			`PFACC_PqQq,`
			`PFMUL_PqQq`
			`PFRCPIT1_PqQq`
			`PFRSQIT1_PqQq`
			`PFRCPIT2_PqQq`

			`[!] CPUID does not report 3DNow! instruction set`

Remove code duplication in CPU and memory objects initialization 2006-01-11 21:22:12 +03:00			`[!] Some of APIC functionality still not implemented, for example`

1G pages support for CPU 2008-12-12 00:00:01 +03:00			`- LVT pins handling`
Remove code duplication in CPU and memory objects initialization 2006-01-11 21:22:12 +03:00			`- Filter interrupts according processor priority (PPR)`
Add todo file to CPU 2005-08-10 23:04:19 +04:00
PAUSE instruction still should be implemented ... 2005-10-14 02:53:03 +04:00			`[!] REP NOP is PAUSE (on P4/XEON)`

			`When running in SMP mode, this means that we are in a spin loop.`
			`This processor should yield to the other one, as we are anyhow waiting`
			`for a lock, and any other processor is responsible for this.`
Implemented CLFLUSH instruction Set of minor fixes for correctness 2007-01-29 00:27:31 +03:00
Add TODO items 2008-04-08 21:59:51 +04:00			`[!] 32-bit linear address wrap when executing in legacy mode might be`
Fixed MASKMOVDQU instruction decoding 2008-04-16 09:41:43 +04:00			`not implemented correctly for system memory accesses (like descriptor`
Add TODO items 2008-04-08 21:59:51 +04:00			`tables and etc)`

white space cleanup 2008-02-03 00:46:54 +03:00			`[!] AMD and Intel x86_64 implementations are different.`
LSL/LAR fixed in 64-bit mode 2009-10-02 20:09:08 +04:00			`Currently Bochs emulation is according to Intel version.`
Support for Intel LSS/LFS/LGS in 64-bit mode TODO: have both AMD and Intelk versions 2007-04-10 00:28:15 +04:00			`Do we need to support both ?`

updated CPU TODO 2009-01-31 14:34:51 +03:00			`[!] VMX:`

			`- Dual-monitor treatment of SMIs and SMM not implemented yet`
move misaligned_sse from compile time to .bochsrc option 2012-12-20 23:43:11 +04:00			`- Posted Interrupts Processing is not implemented yet`
			`- MTF is not implemented yet`
updated CPU TODO 2009-01-31 14:34:51 +03:00
implemented SVM emulation support for Bochs (incomplete yet) I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation. Of course SVM emulation is incomplete, completely untested and not expected to work. But someone could already take a look one the code and give some suggestions. Also looking for anybody with existing SVM kernels - as simple as possible - for testing. Status: - exceptions intercept is not implemented yet - IO intercept is not implemented yet - MSR intercept is not implemented yet - virtual interrupts are not implemented yet - CPUID is not implemented yet No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference. 2011-12-25 23:35:29 +04:00			`[!] SVM:`

Major commit ! ------------ Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest ! A lot of code duplication was added for now - major cleanup will follow later. ! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled. Some CPUID modules rework done to enable Toliman configuration. Ckean up 'executable' attribute from all CPU source files. 2012-02-14 03:29:01 +04:00			`- Decoding assists, pause filter, VMCB clean are not implemented yet`
updates in CPUID defines after new published AMD SDM 2013-05-17 23:41:57 +04:00			`- Advanced Virtual Interrupt Controller (AVIC) not implemented yet`
implemented SVM emulation support for Bochs (incomplete yet) I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation. Of course SVM emulation is incomplete, completely untested and not expected to work. But someone could already take a look one the code and give some suggestions. Also looking for anybody with existing SVM kernels - as simple as possible - for testing. Status: - exceptions intercept is not implemented yet - IO intercept is not implemented yet - MSR intercept is not implemented yet - virtual interrupts are not implemented yet - CPUID is not implemented yet No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference. 2011-12-25 23:35:29 +04:00			`- More?`

move misaligned_sse from compile time to .bochsrc option 2012-12-20 23:43:11 +04:00			`[!] AMD misaligned SSE mode should convert #GP on misaligned SSE access to #AC`
			`exception when #AC is enabled`
added PIII Katmai to CPUDB 2011-07-30 18:30:35 +04:00
			`[!] TODO: Convert CPUDB to plugins and search for them in runtime`
added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h 2013-09-18 00:49:26 +04:00
preparations and interface definition for memory type support 2015-02-19 23:23:08 +03:00			`[!] TODO: Find a way to implement HLE and RTM extensions`
update TODO 2015-06-29 22:57:04 +03:00
			`------------------------------------------------------------------------------------`
			`[!] No plans for MPX, Intel Processor Trace, LWP.`
			`Their emulation would greatly affect emulation performance.`
			`Could be implemented through instrumentation if *really* needed.`
			`------------------------------------------------------------------------------------`