While the NetBSD entry point is handy as we can use a single uImage
with all 3 blobs, it bypasses U-Boot's own patching of the FDT since
it's not visible to it, so we won't get the RAM size and other things
through it.
CreateThreadEvent::DoDPC() missed a reference release to balance the
acquired reference before queuing the DPC, resulting in the
CreateThreadEvent objects being leaked.
This also removes the destructor that tried to cancel the DPC. Since
the class is reference counted and only destroyed when the DPC has
run and released the last reference, this didn't make much sense.
For cases where a BMessage is passed by area, the remote team id needs
to be passed into BMessage::_SendMessage() so it can transfer the area
to the target team. It falls back to detecting the port owner if said
information is missing. However, since the input_server owns the port
in this situation, the remote team needs to be specified explicitly.
Add the app_server team id to the input acquire message, so input_server
gets the needed info.
As messages that exceed the pass by area threshold are rather rare in
general and shouldn't happen at all in this situation, this does not
fix any immediate problem.
When a message is passed by area, the sender is supposed to transfer
area ownership to the target team. If the area is not mapped within
the current team, accessing the area address would be invalid.
Also mark the area as read-only so accidental writes to the area would
become obvious.
When a message is passed by area, any modification to the message must
first trigger a copy of the message content. The success of this
operation was not checked however, possibly leading to later reallocs
on non-heap memory.
The signal to the team/thread is only actually sent in a deferred
procedure. To ensure that the team/thread stays valid between the DPC
being queued and it actually running, we need to acquire a reference.
Fixes#11390, where the DPC was run after the team was already
destroyed.
* X and Y coordinates of hot point were swapped for 1-bit cursors
* Prefer color cursor over 1-bit one if possible
* Adjust the XOR/AND masks for 1-bit cursors to what the hardware
expects
* Handle switching etween hardware and software cursor.
Patch by Looncraz and Ziusudra, fixes#9261.
This introduces InterruptController and HardwareTimer classes to
handle the SoC specific implementations of timers and ints for
the ARM platform.
These could be improved and moved to a more 'generic' level once
we're confident they are 'good enough'.
NOTE: The OMAP timer implementation is fully untested and probably
completely non-functional....
If we find an FDT (either from uImage or otherwise) we make sure
we map it after mmu_init() and use kernel_args to pass it to the
kernel (so it is available at all times there).
This isn't really a bus_manager yet, but just minimal support so
we can get rid of hardcoded ARM SoC support from the core kernel
code.
Needs lots of work, like proper handling of #address-cells and
the like. Also, generic attribute handling, device_manager
integration, and I could go on for hours ;)
Recent linux behaviour (and also copied by BSD) is to preprocess
DTS files with the C preprpocessor to enable sharing constants between
driver implementation and DTS content for more readability.
- Draw conditional breakpoints in a different color from regular
ones for easy visual differentiation.
- Right clicking on an existing breakpoint marker now brings up the
condition editing window.
- Ask the architecture for a stack trace directly, as we only
need the top frame.
- Properly update thread state before we go into condition
evaluation. Otherwise, other parts of the debugger potentially
wouldn't notice that we had continued execution in the case
where the condition evaluates to false, and would indicate a
program stop at the breakpoint erroneously.
* On UEFI, pages are allocated top-down; previously,
VM would fail to allocate early pages due to
running into pages allocated at the top and
assume it had run out of pages to map.
Signed-off-by: Jessica Hamilton <jessica.l.hamilton@gmail.com>
Jessica Hamilton