* Added overlay register definitions.
* The overlay register update buffer is now created and exported, ready to be used. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17244 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
eea30ef36c
commit
22d4db9280
@ -38,6 +38,8 @@ struct pll_info {
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uint32 divisor_register;
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};
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struct overlay_registers;
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struct intel_shared_info {
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int32 type;
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area_id mode_list_area; // area containing display mode list
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@ -57,6 +59,7 @@ struct intel_shared_info {
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int32 overlay_channel_used;
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uint32 overlay_token;
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uint8* physical_overlay_registers;
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uint32 device_type;
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char device_identifier[32];
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@ -72,6 +75,10 @@ struct intel_info {
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area_id registers_area;
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struct intel_shared_info *shared_info;
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area_id shared_area;
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struct overlay_registers *overlay_registers;
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// update buffer, shares an area with shared_info
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uint8 *graphics_memory;
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area_id graphics_memory_area;
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mem_info *memory_manager;
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@ -168,6 +175,139 @@ struct intel_free_graphics_memory {
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#define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3)
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#define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3)
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#define INTEL_OVERLAY_UPDATE 0x30000
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#define INTEL_OVERLAY_TEST 0x30004
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#define INTEL_OVERLAY_STATUS 0x30008
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#define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c
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#define INTEL_OVERLAY_GAMMA_5 0x30010
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#define INTEL_OVERLAY_GAMMA_4 0x30014
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#define INTEL_OVERLAY_GAMMA_3 0x30018
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#define INTEL_OVERLAY_GAMMA_2 0x3001c
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#define INTEL_OVERLAY_GAMMA_1 0x30020
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#define INTEL_OVERLAY_GAMMA_0 0x30024
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struct overlay_scale {
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uint32 vertical_scale_fraction : 12;
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uint32 _reserved0 : 1;
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uint32 horizontal_downscale_factor : 3;
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uint32 _reserved1 : 1;
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uint32 horizontal_scale_fraction : 12;
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};
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// The real overlay registers are written to using an update buffer
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struct overlay_registers {
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uint32 buffer_rgb0;
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uint32 buffer_rgb1;
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uint32 buffer_u0;
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uint32 buffer_v0;
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uint32 buffer_u1;
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uint32 buffer_v1;
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uint16 stride_rgb;
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uint16 stride_uv;
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uint16 vertical_phase0_rgb;
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uint16 vertical_phase1_rgb;
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uint16 vertical_phase0_uv;
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uint16 vertical_phase1_uv;
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uint16 horizontal_phase_rgb;
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uint16 horizontal_phase_uv;
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uint32 _reserved0 : 8;
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uint32 initial_vertical_phase0_shift_rgb0 : 4;
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uint32 initial_vertical_phase1_shift_rgb0 : 4;
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uint32 initial_horizontal_phase_shift_rgb0 : 4;
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uint32 initial_vertical_phase0_shift_uv : 4;
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uint32 initial_vertical_phase1_shift_uv : 4;
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uint32 initial_horizontal_phase_shift_uv : 4;
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uint16 window_left;
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uint16 window_top;
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uint16 window_width;
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uint16 window_height;
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uint16 source_width_rgb;
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uint16 source_width_uv;
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uint16 source_bytes_per_row_rgb;
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uint16 source_bytes_per_row_uv;
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uint16 source_height_rgb;
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uint16 source_height_uv;
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overlay_scale scale_rgb;
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overlay_scale scale_uv;
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// (0x48) OCLRC0 - overlay color correction 0
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uint32 _reserved1 : 5;
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uint32 contrast_correction : 9;
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uint32 _reserved2 : 10;
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uint32 brightness_correction : 8;
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// (0x4c) OCLRC1 - overlay color correction 1
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uint32 _reserved3 : 5;
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uint32 saturation_sin_correction : 11;
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uint32 _reserved4 : 6;
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uint32 saturation_cos_correction : 10;
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// (0x50) DCLRKV - destination color key value
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uint32 _reserved5 : 8;
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uint32 color_key_red : 8;
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uint32 color_key_green : 8;
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uint32 color_key_blue : 8;
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// (0x54) DCLRKM - destination color key mask
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uint32 color_key_enabled : 1;
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uint32 _reserved6 : 7;
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uint32 color_key_mask_red : 8;
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uint32 color_key_mask_green : 8;
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uint32 color_key_mask_blue : 8;
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// (0x58) SCHRKVH - source chroma key high value
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uint32 _reserved7 : 8;
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uint32 source_chroma_key_high_green : 8;
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uint32 source_chroma_key_high_blue : 8;
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uint32 source_chroma_key_high_red : 8;
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// (0x5c) SCHRKVL - source chroma key low value
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uint32 _reserved8 : 8;
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uint32 source_chroma_key_low_green : 8;
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uint32 source_chroma_key_low_blue : 8;
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uint32 source_chroma_key_low_red : 8;
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// (0x60) SCHRKEN - source chroma key enable
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uint32 _reserved9 : 5;
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uint32 source_chroma_key_green_enabled : 1;
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uint32 source_chroma_key_blue_enabled : 1;
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uint32 source_chroma_key_red_enabled : 1;
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uint32 _reserved10 : 24;
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// (0x64) OCONFIG - overlay configuration
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uint32 _reserved11 : 5;
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uint32 slot_time : 8;
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uint32 _reserved12 : 2;
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uint32 gamma2_enabled : 1;
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uint32 _reserved13 : 11;
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uint32 yuv_to_rgb_bypass : 1;
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uint32 color_control_output_mode : 1;
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uint32 _reserved14 : 3;
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// (0x68) OCOMD - overlay command
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uint32 _reserved15 : 13;
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uint32 mirroring_mode : 2;
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uint32 _reserved16 : 1;
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uint32 ycbcr422_order : 2;
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uint32 _reserved17 : 4;
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uint32 tv_flip_field_parity : 1;
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uint32 _reserved18 : 1;
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uint32 tv_flip_field_enabled : 1;
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uint32 _reserved19 : 1;
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uint32 buffer_field_mode : 1;
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uint32 test_mode : 1;
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uint32 active_buffer : 2;
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uint32 active_field : 1;
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uint32 overlay_enabled : 1;
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uint32 _reserved20;
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// (0x70) AWINPOS - alpha blend window position
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uint32 awinpos;
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// (0x74) AWINSZ - alpha blend window size
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uint32 awinsz;
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uint32 _reserved21[10];
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// (0xa0) FASTHSCALE - fast horizontal downscale
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uint16 horizontal_scale_rgb;
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uint16 horizontal_scale_uv;
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uint16 vertical_scale_rgb;
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uint16 vertical_scale_uv;
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};
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//----------------------------------------------------------
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extern status_t intel_extreme_init(intel_info &info);
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@ -76,7 +76,7 @@ intel_extreme_init(intel_info &info)
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{
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info.shared_area = create_area("intel extreme shared info",
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(void **)&info.shared_info, B_ANY_KERNEL_ADDRESS,
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ROUND_TO_PAGE_SIZE(sizeof(intel_shared_info)),
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ROUND_TO_PAGE_SIZE(sizeof(intel_shared_info)) + B_PAGE_SIZE,
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B_FULL_LOCK, 0);
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if (info.shared_area < B_OK)
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return info.shared_area;
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@ -155,6 +155,13 @@ intel_extreme_init(intel_info &info)
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strcpy(info.shared_info->device_identifier, info.device_identifier);
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#endif
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// setup overlay registers
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info.overlay_registers = (overlay_registers *)((addr_t)info.shared_info + B_PAGE_SIZE);
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physical_entry physicalEntry;
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get_memory_map(info.overlay_registers, sizeof(overlay_registers), &physicalEntry, 1);
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info.shared_info->physical_overlay_registers = (uint8 *)physicalEntry.address;
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info.cookie_magic = INTEL_COOKIE_MAGIC;
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// this makes the cookie valid to be used
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