22d4db9280
* The overlay register update buffer is now created and exported, ready to be used. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17244 a95241bf-73f2-0310-859d-f6bbb57e9c96
317 lines
8.6 KiB
C
317 lines
8.6 KiB
C
/*
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* Copyright 2006, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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*/
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#ifndef INTEL_EXTREME_H
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#define INTEL_EXTREME_H
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#include <memory_manager.h>
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#include <Accelerant.h>
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#include <Drivers.h>
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#include <PCI.h>
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#define VENDOR_ID_INTEL 0x8086
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enum {
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INTEL_TYPE_7xx,
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INTEL_TYPE_8xx,
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INTEL_TYPE_9xx,
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};
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#define DEVICE_NAME "intel_extreme"
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#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
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#define INTEL_COOKIE_MAGIC 'intl'
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#define INTEL_FREE_COOKIE_MAGIC 'itlf'
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// info about PLL on graphics card
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struct pll_info {
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uint32 reference_frequency;
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uint32 max_frequency;
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uint32 min_frequency;
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uint32 divisor_register;
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};
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struct overlay_registers;
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struct intel_shared_info {
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int32 type;
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area_id mode_list_area; // area containing display mode list
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uint32 mode_count;
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display_mode current_mode;
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uint32 bytes_per_row;
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uint32 dpms_mode;
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area_id registers_area; // area of memory mapped registers
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area_id graphics_memory_area;
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uint8 *graphics_memory;
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uint8 *physical_graphics_memory;
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uint32 graphics_memory_size;
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uint32 frame_buffer_offset;
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int32 overlay_channel_used;
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uint32 overlay_token;
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uint8* physical_overlay_registers;
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uint32 device_type;
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char device_identifier[32];
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struct pll_info pll_info;
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};
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struct intel_info {
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uint32 cookie_magic;
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int32 open_count;
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int32 id;
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pci_info *pci;
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uint8 *registers;
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area_id registers_area;
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struct intel_shared_info *shared_info;
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area_id shared_area;
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struct overlay_registers *overlay_registers;
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// update buffer, shares an area with shared_info
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uint8 *graphics_memory;
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area_id graphics_memory_area;
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mem_info *memory_manager;
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const char *device_identifier;
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uint32 device_type;
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};
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//----------------- ioctl() interface ----------------
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// magic code for ioctls
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#define INTEL_PRIVATE_DATA_MAGIC 'itic'
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// list ioctls
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enum {
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INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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INTEL_GET_DEVICE_NAME,
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INTEL_ALLOCATE_GRAPHICS_MEMORY,
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INTEL_FREE_GRAPHICS_MEMORY
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};
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// retrieve the area_id of the kernel/accelerant shared info
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struct intel_get_private_data {
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uint32 magic; // magic number
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area_id shared_info_area;
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};
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// allocate graphics memory
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struct intel_allocate_graphics_memory {
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uint32 magic;
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uint32 size;
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uint32 buffer_offset;
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uint32 handle;
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};
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// free graphics memory
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struct intel_free_graphics_memory {
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uint32 magic;
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uint32 handle;
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};
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//----------------------------------------------------------
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// Register definitions, taken from X driver
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#define INTEL_DISPLAY_HTOTAL 0x60000
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#define INTEL_DISPLAY_HBLANK 0x60004
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#define INTEL_DISPLAY_HSYNC 0x60008
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#define INTEL_DISPLAY_VTOTAL 0x6000c
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#define INTEL_DISPLAY_VBLANK 0x60010
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#define INTEL_DISPLAY_VSYNC 0x60014
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#define INTEL_DISPLAY_IMAGE_SIZE 0x6001c
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#define INTEL_DISPLAY_CONTROL 0x70180
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#define INTEL_DISPLAY_BASE 0x70184
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#define INTEL_DISPLAY_BYTES_PER_ROW 0x70188
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#define DISPLAY_CONTROL_ENABLED (1UL << 31)
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#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
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#define DISPLAY_CONTROL_CMAP8 (2UL << 26)
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#define DISPLAY_CONTROL_RGB15 (4UL << 26)
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#define DISPLAY_CONTROL_RGB16 (5UL << 26)
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#define DISPLAY_CONTROL_RGB32 (7UL << 26)
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#define INTEL_DISPLAY_PIPE_CONTROL 0x70008
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#define DISPLAY_PIPE_ENABLED (1UL << 31)
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#define INTEL_DISPLAY_PLL 0x06014
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#define INTEL_DISPLAY_PLL_DIVISOR_0 0x06040
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#define INTEL_DISPLAY_PLL_DIVISOR_1 0x06044
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#define DISPLAY_PLL_ENABLED (1UL << 31)
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#define DISPLAY_PLL_2X_CLOCK (1UL << 30)
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#define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29)
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#define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28)
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#define DISPLAY_PLL_DIVIDE_4X (1UL << 23)
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#define DISPLAY_PLL_POST_DIVISOR_MASK 0x001f0000
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#define DISPLAY_PLL_POST_DIVISOR_SHIFT 16
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#define DISPLAY_PLL_DIVISOR_1 (1UL << 8)
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#define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000
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#define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00
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#define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f
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#define DISPLAY_PLL_N_DIVISOR_SHIFT 16
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#define DISPLAY_PLL_M1_DIVISOR_SHIFT 8
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#define DISPLAY_PLL_M2_DIVISOR_SHIFT 0
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#define INTEL_DISPLAY_ANALOG_PORT 0x61100
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#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
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#define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15)
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#define DISPLAY_MONITOR_MODE_MASK (3UL << 10)
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#define DISPLAY_MONITOR_ON 0
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#define DISPLAY_MONITOR_SUSPEND (1UL << 10)
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#define DISPLAY_MONITOR_STAND_BY (2UL << 10)
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#define DISPLAY_MONITOR_OFF (3UL << 10)
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#define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3)
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#define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3)
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#define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3)
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#define INTEL_OVERLAY_UPDATE 0x30000
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#define INTEL_OVERLAY_TEST 0x30004
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#define INTEL_OVERLAY_STATUS 0x30008
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#define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c
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#define INTEL_OVERLAY_GAMMA_5 0x30010
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#define INTEL_OVERLAY_GAMMA_4 0x30014
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#define INTEL_OVERLAY_GAMMA_3 0x30018
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#define INTEL_OVERLAY_GAMMA_2 0x3001c
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#define INTEL_OVERLAY_GAMMA_1 0x30020
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#define INTEL_OVERLAY_GAMMA_0 0x30024
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struct overlay_scale {
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uint32 vertical_scale_fraction : 12;
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uint32 _reserved0 : 1;
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uint32 horizontal_downscale_factor : 3;
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uint32 _reserved1 : 1;
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uint32 horizontal_scale_fraction : 12;
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};
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// The real overlay registers are written to using an update buffer
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struct overlay_registers {
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uint32 buffer_rgb0;
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uint32 buffer_rgb1;
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uint32 buffer_u0;
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uint32 buffer_v0;
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uint32 buffer_u1;
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uint32 buffer_v1;
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uint16 stride_rgb;
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uint16 stride_uv;
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uint16 vertical_phase0_rgb;
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uint16 vertical_phase1_rgb;
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uint16 vertical_phase0_uv;
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uint16 vertical_phase1_uv;
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uint16 horizontal_phase_rgb;
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uint16 horizontal_phase_uv;
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uint32 _reserved0 : 8;
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uint32 initial_vertical_phase0_shift_rgb0 : 4;
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uint32 initial_vertical_phase1_shift_rgb0 : 4;
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uint32 initial_horizontal_phase_shift_rgb0 : 4;
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uint32 initial_vertical_phase0_shift_uv : 4;
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uint32 initial_vertical_phase1_shift_uv : 4;
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uint32 initial_horizontal_phase_shift_uv : 4;
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uint16 window_left;
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uint16 window_top;
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uint16 window_width;
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uint16 window_height;
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uint16 source_width_rgb;
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uint16 source_width_uv;
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uint16 source_bytes_per_row_rgb;
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uint16 source_bytes_per_row_uv;
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uint16 source_height_rgb;
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uint16 source_height_uv;
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overlay_scale scale_rgb;
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overlay_scale scale_uv;
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// (0x48) OCLRC0 - overlay color correction 0
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uint32 _reserved1 : 5;
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uint32 contrast_correction : 9;
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uint32 _reserved2 : 10;
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uint32 brightness_correction : 8;
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// (0x4c) OCLRC1 - overlay color correction 1
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uint32 _reserved3 : 5;
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uint32 saturation_sin_correction : 11;
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uint32 _reserved4 : 6;
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uint32 saturation_cos_correction : 10;
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// (0x50) DCLRKV - destination color key value
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uint32 _reserved5 : 8;
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uint32 color_key_red : 8;
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uint32 color_key_green : 8;
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uint32 color_key_blue : 8;
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// (0x54) DCLRKM - destination color key mask
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uint32 color_key_enabled : 1;
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uint32 _reserved6 : 7;
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uint32 color_key_mask_red : 8;
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uint32 color_key_mask_green : 8;
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uint32 color_key_mask_blue : 8;
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// (0x58) SCHRKVH - source chroma key high value
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uint32 _reserved7 : 8;
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uint32 source_chroma_key_high_green : 8;
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uint32 source_chroma_key_high_blue : 8;
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uint32 source_chroma_key_high_red : 8;
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// (0x5c) SCHRKVL - source chroma key low value
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uint32 _reserved8 : 8;
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uint32 source_chroma_key_low_green : 8;
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uint32 source_chroma_key_low_blue : 8;
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uint32 source_chroma_key_low_red : 8;
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// (0x60) SCHRKEN - source chroma key enable
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uint32 _reserved9 : 5;
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uint32 source_chroma_key_green_enabled : 1;
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uint32 source_chroma_key_blue_enabled : 1;
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uint32 source_chroma_key_red_enabled : 1;
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uint32 _reserved10 : 24;
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// (0x64) OCONFIG - overlay configuration
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uint32 _reserved11 : 5;
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uint32 slot_time : 8;
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uint32 _reserved12 : 2;
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uint32 gamma2_enabled : 1;
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uint32 _reserved13 : 11;
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uint32 yuv_to_rgb_bypass : 1;
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uint32 color_control_output_mode : 1;
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uint32 _reserved14 : 3;
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// (0x68) OCOMD - overlay command
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uint32 _reserved15 : 13;
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uint32 mirroring_mode : 2;
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uint32 _reserved16 : 1;
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uint32 ycbcr422_order : 2;
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uint32 _reserved17 : 4;
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uint32 tv_flip_field_parity : 1;
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uint32 _reserved18 : 1;
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uint32 tv_flip_field_enabled : 1;
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uint32 _reserved19 : 1;
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uint32 buffer_field_mode : 1;
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uint32 test_mode : 1;
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uint32 active_buffer : 2;
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uint32 active_field : 1;
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uint32 overlay_enabled : 1;
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uint32 _reserved20;
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// (0x70) AWINPOS - alpha blend window position
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uint32 awinpos;
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// (0x74) AWINSZ - alpha blend window size
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uint32 awinsz;
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uint32 _reserved21[10];
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// (0xa0) FASTHSCALE - fast horizontal downscale
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uint16 horizontal_scale_rgb;
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uint16 horizontal_scale_uv;
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uint16 vertical_scale_rgb;
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uint16 vertical_scale_uv;
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};
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//----------------------------------------------------------
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extern status_t intel_extreme_init(intel_info &info);
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extern void intel_extreme_uninit(intel_info &info);
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#endif /* INTEL_EXTREME_H */
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