diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index 872a7cceb6..d355d63b90 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -38,6 +38,8 @@ struct pll_info { uint32 divisor_register; }; +struct overlay_registers; + struct intel_shared_info { int32 type; area_id mode_list_area; // area containing display mode list @@ -57,6 +59,7 @@ struct intel_shared_info { int32 overlay_channel_used; uint32 overlay_token; + uint8* physical_overlay_registers; uint32 device_type; char device_identifier[32]; @@ -72,6 +75,10 @@ struct intel_info { area_id registers_area; struct intel_shared_info *shared_info; area_id shared_area; + + struct overlay_registers *overlay_registers; + // update buffer, shares an area with shared_info + uint8 *graphics_memory; area_id graphics_memory_area; mem_info *memory_manager; @@ -168,6 +175,139 @@ struct intel_free_graphics_memory { #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) +#define INTEL_OVERLAY_UPDATE 0x30000 +#define INTEL_OVERLAY_TEST 0x30004 +#define INTEL_OVERLAY_STATUS 0x30008 +#define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c +#define INTEL_OVERLAY_GAMMA_5 0x30010 +#define INTEL_OVERLAY_GAMMA_4 0x30014 +#define INTEL_OVERLAY_GAMMA_3 0x30018 +#define INTEL_OVERLAY_GAMMA_2 0x3001c +#define INTEL_OVERLAY_GAMMA_1 0x30020 +#define INTEL_OVERLAY_GAMMA_0 0x30024 + +struct overlay_scale { + uint32 vertical_scale_fraction : 12; + uint32 _reserved0 : 1; + uint32 horizontal_downscale_factor : 3; + uint32 _reserved1 : 1; + uint32 horizontal_scale_fraction : 12; +}; + +// The real overlay registers are written to using an update buffer + +struct overlay_registers { + uint32 buffer_rgb0; + uint32 buffer_rgb1; + uint32 buffer_u0; + uint32 buffer_v0; + uint32 buffer_u1; + uint32 buffer_v1; + uint16 stride_rgb; + uint16 stride_uv; + uint16 vertical_phase0_rgb; + uint16 vertical_phase1_rgb; + uint16 vertical_phase0_uv; + uint16 vertical_phase1_uv; + uint16 horizontal_phase_rgb; + uint16 horizontal_phase_uv; + uint32 _reserved0 : 8; + uint32 initial_vertical_phase0_shift_rgb0 : 4; + uint32 initial_vertical_phase1_shift_rgb0 : 4; + uint32 initial_horizontal_phase_shift_rgb0 : 4; + uint32 initial_vertical_phase0_shift_uv : 4; + uint32 initial_vertical_phase1_shift_uv : 4; + uint32 initial_horizontal_phase_shift_uv : 4; + uint16 window_left; + uint16 window_top; + uint16 window_width; + uint16 window_height; + uint16 source_width_rgb; + uint16 source_width_uv; + uint16 source_bytes_per_row_rgb; + uint16 source_bytes_per_row_uv; + uint16 source_height_rgb; + uint16 source_height_uv; + overlay_scale scale_rgb; + overlay_scale scale_uv; + // (0x48) OCLRC0 - overlay color correction 0 + uint32 _reserved1 : 5; + uint32 contrast_correction : 9; + uint32 _reserved2 : 10; + uint32 brightness_correction : 8; + // (0x4c) OCLRC1 - overlay color correction 1 + uint32 _reserved3 : 5; + uint32 saturation_sin_correction : 11; + uint32 _reserved4 : 6; + uint32 saturation_cos_correction : 10; + // (0x50) DCLRKV - destination color key value + uint32 _reserved5 : 8; + uint32 color_key_red : 8; + uint32 color_key_green : 8; + uint32 color_key_blue : 8; + // (0x54) DCLRKM - destination color key mask + uint32 color_key_enabled : 1; + uint32 _reserved6 : 7; + uint32 color_key_mask_red : 8; + uint32 color_key_mask_green : 8; + uint32 color_key_mask_blue : 8; + // (0x58) SCHRKVH - source chroma key high value + uint32 _reserved7 : 8; + uint32 source_chroma_key_high_green : 8; + uint32 source_chroma_key_high_blue : 8; + uint32 source_chroma_key_high_red : 8; + // (0x5c) SCHRKVL - source chroma key low value + uint32 _reserved8 : 8; + uint32 source_chroma_key_low_green : 8; + uint32 source_chroma_key_low_blue : 8; + uint32 source_chroma_key_low_red : 8; + // (0x60) SCHRKEN - source chroma key enable + uint32 _reserved9 : 5; + uint32 source_chroma_key_green_enabled : 1; + uint32 source_chroma_key_blue_enabled : 1; + uint32 source_chroma_key_red_enabled : 1; + uint32 _reserved10 : 24; + // (0x64) OCONFIG - overlay configuration + uint32 _reserved11 : 5; + uint32 slot_time : 8; + uint32 _reserved12 : 2; + uint32 gamma2_enabled : 1; + uint32 _reserved13 : 11; + uint32 yuv_to_rgb_bypass : 1; + uint32 color_control_output_mode : 1; + uint32 _reserved14 : 3; + // (0x68) OCOMD - overlay command + uint32 _reserved15 : 13; + uint32 mirroring_mode : 2; + uint32 _reserved16 : 1; + uint32 ycbcr422_order : 2; + uint32 _reserved17 : 4; + uint32 tv_flip_field_parity : 1; + uint32 _reserved18 : 1; + uint32 tv_flip_field_enabled : 1; + uint32 _reserved19 : 1; + uint32 buffer_field_mode : 1; + uint32 test_mode : 1; + uint32 active_buffer : 2; + uint32 active_field : 1; + uint32 overlay_enabled : 1; + + uint32 _reserved20; + + // (0x70) AWINPOS - alpha blend window position + uint32 awinpos; + // (0x74) AWINSZ - alpha blend window size + uint32 awinsz; + + uint32 _reserved21[10]; + + // (0xa0) FASTHSCALE - fast horizontal downscale + uint16 horizontal_scale_rgb; + uint16 horizontal_scale_uv; + uint16 vertical_scale_rgb; + uint16 vertical_scale_uv; +}; + //---------------------------------------------------------- extern status_t intel_extreme_init(intel_info &info); diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp index 0c687c8ded..d5e7efd388 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp @@ -76,7 +76,7 @@ intel_extreme_init(intel_info &info) { info.shared_area = create_area("intel extreme shared info", (void **)&info.shared_info, B_ANY_KERNEL_ADDRESS, - ROUND_TO_PAGE_SIZE(sizeof(intel_shared_info)), + ROUND_TO_PAGE_SIZE(sizeof(intel_shared_info)) + B_PAGE_SIZE, B_FULL_LOCK, 0); if (info.shared_area < B_OK) return info.shared_area; @@ -155,6 +155,13 @@ intel_extreme_init(intel_info &info) strcpy(info.shared_info->device_identifier, info.device_identifier); #endif + // setup overlay registers + info.overlay_registers = (overlay_registers *)((addr_t)info.shared_info + B_PAGE_SIZE); + + physical_entry physicalEntry; + get_memory_map(info.overlay_registers, sizeof(overlay_registers), &physicalEntry, 1); + info.shared_info->physical_overlay_registers = (uint8 *)physicalEntry.address; + info.cookie_magic = INTEL_COOKIE_MAGIC; // this makes the cookie valid to be used