2010-04-14 02:35:53 +04:00
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/*
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2011-05-10 06:02:41 +04:00
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* Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
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2010-04-14 02:35:53 +04:00
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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2011-03-22 00:52:01 +03:00
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* Alexander von Gluck IV, kallisti5@unixzen.com
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2010-04-14 02:35:53 +04:00
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*/
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#ifndef RADEON_HD_H
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#define RADEON_HD_H
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#include "lock.h"
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2011-08-06 02:24:57 +04:00
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#include "radeon_reg.h"
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2015-07-16 02:03:02 +03:00
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//#include "r500_reg.h" // Not used atm. DCE 0
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#include "avivo_reg.h" // DCE 1
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#include "r600_reg.h" // DCE 2
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#include "r700_reg.h" // DCE 3
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#include "evergreen_reg.h" // DCE 4
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#include "ni_reg.h" // DCE 5
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#include "si_reg.h" // DCE 6
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#include "sea_reg.h" // DCE 8
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#include "vol_reg.h" // DCE 10
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#include "car_reg.h" // DCE 11
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2011-05-10 06:02:41 +04:00
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2010-04-14 02:35:53 +04:00
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#include <Accelerant.h>
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#include <Drivers.h>
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2011-05-10 06:02:41 +04:00
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#include <edid.h>
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2010-04-14 02:35:53 +04:00
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#include <PCI.h>
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2011-08-08 00:16:32 +04:00
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#define VENDOR_ID_ATI 0x1002
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2011-10-24 21:53:22 +04:00
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// Card chipset flags
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#define CHIP_STD (1 << 0) // Standard chipset
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2013-06-29 22:18:18 +04:00
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#define CHIP_X2 (1 << 1) // Dual cpu
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#define CHIP_IGP (1 << 2) // IGP chipset
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#define CHIP_MOBILE (1 << 3) // Mobile chipset
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#define CHIP_DISCREET (1 << 4) // Discreet chipset
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#define CHIP_APU (1 << 5) // APU chipset
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2011-05-10 06:02:41 +04:00
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2010-04-14 02:35:53 +04:00
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#define DEVICE_NAME "radeon_hd"
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#define RADEON_ACCELERANT_NAME "radeon_hd.accelerant"
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2013-07-16 20:20:24 +04:00
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#define MAX_NAME_LENGTH 32
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2011-05-10 06:02:41 +04:00
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// Used to collect EDID from boot loader
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#define EDID_BOOT_INFO "vesa_edid/v1"
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#define MODES_BOOT_INFO "vesa_modes/v1"
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2011-06-15 19:44:14 +04:00
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#define RHD_POWER_ON 0
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#define RHD_POWER_RESET 1 /* off temporarily */
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#define RHD_POWER_SHUTDOWN 2 /* long term shutdown */
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#define RHD_POWER_UNKNOWN 3 /* initial state */
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2011-03-22 00:52:01 +03:00
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2011-11-08 21:17:43 +04:00
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// Radeon Chipsets
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2013-07-16 20:20:24 +04:00
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// !! Must match chipset names below
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2011-11-08 21:17:43 +04:00
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enum radeon_chipset {
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RADEON_R420 = 0, //r400, Radeon X700-X850
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2011-11-12 21:41:31 +04:00
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RADEON_R423,
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RADEON_RV410,
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RADEON_RS400,
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RADEON_RS480,
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RADEON_RS600,
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RADEON_RS690,
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RADEON_RS740,
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2011-11-08 21:17:43 +04:00
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RADEON_RV515,
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2013-07-09 21:40:29 +04:00
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RADEON_R520, //r500, DCE 1.0
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RADEON_RV530, // DCE 1.0
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RADEON_RV560, // DCE 1.0
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RADEON_RV570, // DCE 1.0
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RADEON_R580, // DCE 1.0
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RADEON_R600, //r600, DCE 2.0
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RADEON_RV610, // DCE 2.0
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RADEON_RV630, // DCE 2.0
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RADEON_RV670, // DCE 2.0
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RADEON_RV620, // DCE 3.0
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RADEON_RV635, // DCE 3.0
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RADEON_RS780, // DCE 3.0
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RADEON_RS880, // DCE 3.0
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RADEON_RV770, //r700, DCE 3.1
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RADEON_RV730, // DCE 3.2
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RADEON_RV710, // DCE 3.2
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RADEON_RV740, // DCE 3.2
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RADEON_CEDAR, //Evergreen, DCE 4.0
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RADEON_REDWOOD, // DCE 4.0
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RADEON_JUNIPER, // DCE 4.0
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RADEON_CYPRESS, // DCE 4.0
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RADEON_HEMLOCK, // DCE 4.0?
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RADEON_PALM, //Fusion APU (NI), DCE 4.1
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RADEON_SUMO, // DCE 4.1
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RADEON_SUMO2, // DCE 4.1
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RADEON_CAICOS, //Nothern Islands, DCE 5.0
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RADEON_TURKS, // DCE 5.0
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RADEON_BARTS, // DCE 5.0
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RADEON_CAYMAN, // DCE 5.0
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RADEON_ANTILLES, // DCE 5.0?
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RADEON_CAPEVERDE, //Southern Islands, DCE 6.0
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RADEON_PITCAIRN, // DCE 6.0
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RADEON_TAHITI, // DCE 6.0
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RADEON_ARUBA, // DCE 6.1 Trinity/Richland
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RADEON_OLAND, // DCE 6.4
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2013-07-16 20:20:24 +04:00
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RADEON_HAINAN, // NO DCE, only compute
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2013-07-09 21:40:29 +04:00
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RADEON_KAVERI, //Sea Islands, DCE 8.1
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RADEON_BONAIRE, // DCE 8.2
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RADEON_KABINI, // DCE 8.3
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2014-05-25 18:03:03 +04:00
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RADEON_MULLINS, // DCE 8.3
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2015-07-07 18:27:29 +03:00
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RADEON_HAWAII, // DCE 8.5
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RADEON_TOPAZ, //Volcanic Islands, NO DCE
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RADEON_TONGA, // DCE 10.0
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2016-06-30 23:09:59 +03:00
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RADEON_CARRIZO, // DCE 11.0
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2017-09-22 23:58:33 +03:00
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RADEON_POLARIS, //Artic Islands, DCE 12.0*
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RADEON_VEGA, // DCE 13.0*
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2011-11-08 21:17:43 +04:00
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};
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2013-07-16 20:20:24 +04:00
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// !! Must match chipset families above
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static const char radeon_chip_name[][MAX_NAME_LENGTH] = {
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"R420",
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"R423",
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"RV410",
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"RS400",
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"RS480",
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"RS600",
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"RS690",
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"RS740",
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"RV515",
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"R520",
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"RV530",
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"RV560",
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"RV570",
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"R580",
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"R600",
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"RV610",
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"RV630",
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"RV670",
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"RV620",
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"RV635",
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"RS780",
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"RS880",
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"RV770",
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"RV730",
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"RV710",
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"RV740",
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"Cedar",
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"Redwood",
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"Juniper",
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"Cypress",
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"Hemlock",
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"Palm",
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"Sumo",
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"Sumo2",
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"Caicos",
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"Turks",
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"Barts",
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"Cayman",
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"Antilles",
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"Cape Verde",
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"Pitcairn",
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"Tahiti",
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"Aruba",
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"Oland",
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"Hainan",
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"Kaveri",
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"Bonaire",
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2014-05-25 18:03:03 +04:00
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"Kabini",
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"Mullins",
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2015-07-07 18:27:29 +03:00
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"Hawaii",
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"Topaz",
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"Tonga",
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2016-06-30 23:09:59 +03:00
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"Carrizo",
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"Polaris"
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2013-07-16 20:20:24 +04:00
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};
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2011-11-08 21:17:43 +04:00
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2010-04-14 02:35:53 +04:00
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struct ring_buffer {
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struct lock lock;
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uint32 register_base;
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uint32 offset;
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uint32 size;
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uint32 position;
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uint32 space_left;
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uint8* base;
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};
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2011-04-03 21:20:05 +04:00
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2010-04-14 02:35:53 +04:00
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struct overlay_registers;
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2011-04-03 21:20:05 +04:00
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2010-04-14 02:35:53 +04:00
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struct radeon_shared_info {
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2011-11-08 23:50:07 +04:00
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uint32 deviceIndex; // accelerant index
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2016-09-28 23:46:14 +03:00
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uint32 pciID; // device pci id
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uint32 pciRev; // device pci revision
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2010-04-14 02:35:53 +04:00
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area_id mode_list_area; // area containing display mode list
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uint32 mode_count;
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2011-08-03 22:16:10 +04:00
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bool has_rom; // was rom mapped?
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2011-08-04 03:23:16 +04:00
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area_id rom_area; // area of mapped rom
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2011-08-02 22:05:52 +04:00
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uint32 rom_phys; // rom base location
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uint32 rom_size; // rom size
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2011-08-03 22:16:10 +04:00
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uint8* rom; // cloned, memory mapped PCI ROM
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2011-08-02 18:58:56 +04:00
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2010-04-14 02:35:53 +04:00
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display_mode current_mode;
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uint32 bytes_per_row;
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uint32 bits_per_pixel;
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uint32 dpms_mode;
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area_id registers_area; // area of memory mapped registers
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uint8* status_page;
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addr_t physical_status_page;
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uint32 graphics_memory_size;
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2011-05-18 22:38:28 +04:00
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2011-05-25 02:08:54 +04:00
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uint8* frame_buffer; // virtual memory mapped FB
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2011-10-26 08:51:51 +04:00
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area_id frame_buffer_area; // area of memory mapped FB
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addr_t frame_buffer_phys; // card PCI BAR address of FB
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uint32 frame_buffer_size; // FB size mapped
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2010-04-14 02:35:53 +04:00
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2011-05-10 06:02:41 +04:00
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bool has_edid;
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edid1_info edid_info;
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2010-04-14 02:35:53 +04:00
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struct lock accelerant_lock;
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struct lock engine_lock;
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ring_buffer primary_ring_buffer;
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int32 overlay_channel_used;
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bool overlay_active;
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uint32 overlay_token;
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addr_t physical_overlay_registers;
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uint32 overlay_offset;
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bool hardware_cursor_enabled;
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sem_id vblank_sem;
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uint8* cursor_memory;
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addr_t physical_cursor_memory;
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uint32 cursor_buffer_offset;
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uint32 cursor_format;
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bool cursor_visible;
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uint16 cursor_hot_x;
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uint16 cursor_hot_y;
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2013-07-16 20:20:24 +04:00
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char deviceName[MAX_NAME_LENGTH];
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2011-11-08 23:50:07 +04:00
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uint16 chipsetID;
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2013-07-16 20:20:24 +04:00
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char chipsetName[MAX_NAME_LENGTH];
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2011-10-24 21:53:22 +04:00
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uint32 chipsetFlags;
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2011-10-21 18:32:01 +04:00
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uint8 dceMajor;
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uint8 dceMinor;
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2013-01-29 05:47:41 +04:00
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uint16 color_data[3 * 256]; // colour lookup table
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2010-04-14 02:35:53 +04:00
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};
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//----------------- ioctl() interface ----------------
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// magic code for ioctls
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#define RADEON_PRIVATE_DATA_MAGIC 'rdhd'
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// list ioctls
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enum {
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RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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RADEON_GET_DEVICE_NAME,
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RADEON_ALLOCATE_GRAPHICS_MEMORY,
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RADEON_FREE_GRAPHICS_MEMORY
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};
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// retrieve the area_id of the kernel/accelerant shared info
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struct radeon_get_private_data {
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uint32 magic; // magic number
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area_id shared_info_area;
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};
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// allocate graphics memory
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struct radeon_allocate_graphics_memory {
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uint32 magic;
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uint32 size;
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uint32 alignment;
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uint32 flags;
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uint32 buffer_base;
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};
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// free graphics memory
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struct radeon_free_graphics_memory {
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uint32 magic;
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uint32 buffer_base;
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};
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2011-05-16 22:10:49 +04:00
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// registers
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#define R6XX_CONFIG_APER_SIZE 0x5430 // r600>
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#define OLD_CONFIG_APER_SIZE 0x0108 // <r600
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2011-10-28 08:30:54 +04:00
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#define CONFIG_MEMSIZE 0x5428 // r600>
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2011-05-27 06:14:54 +04:00
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2011-03-22 00:52:01 +03:00
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// PCI bridge memory management
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2010-04-14 02:35:53 +04:00
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// overlay
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#define RADEON_OVERLAY_UPDATE 0x30000
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#define RADEON_OVERLAY_TEST 0x30004
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#define RADEON_OVERLAY_STATUS 0x30008
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#define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c
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#define RADEON_OVERLAY_GAMMA_5 0x30010
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#define RADEON_OVERLAY_GAMMA_4 0x30014
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#define RADEON_OVERLAY_GAMMA_3 0x30018
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#define RADEON_OVERLAY_GAMMA_2 0x3001c
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#define RADEON_OVERLAY_GAMMA_1 0x30020
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#define RADEON_OVERLAY_GAMMA_0 0x30024
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struct overlay_scale {
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uint32 _reserved0 : 3;
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uint32 horizontal_scale_fraction : 12;
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uint32 _reserved1 : 1;
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uint32 horizontal_downscale_factor : 3;
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uint32 _reserved2 : 1;
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uint32 vertical_scale_fraction : 12;
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};
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#define OVERLAY_FORMAT_RGB15 0x2
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#define OVERLAY_FORMAT_RGB16 0x3
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#define OVERLAY_FORMAT_RGB32 0x1
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#define OVERLAY_FORMAT_YCbCr422 0x8
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#define OVERLAY_FORMAT_YCbCr411 0x9
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#define OVERLAY_FORMAT_YCbCr420 0xc
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#define OVERLAY_MIRROR_NORMAL 0x0
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#define OVERLAY_MIRROR_HORIZONTAL 0x1
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#define OVERLAY_MIRROR_VERTICAL 0x2
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// The real overlay registers are written to using an update buffer
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struct overlay_registers {
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uint32 buffer_rgb0;
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uint32 buffer_rgb1;
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uint32 buffer_u0;
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uint32 buffer_v0;
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uint32 buffer_u1;
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uint32 buffer_v1;
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// (0x18) OSTRIDE - overlay stride
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uint16 stride_rgb;
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uint16 stride_uv;
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// (0x1c) YRGB_VPH - Y/RGB vertical phase
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uint16 vertical_phase0_rgb;
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uint16 vertical_phase1_rgb;
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// (0x20) UV_VPH - UV vertical phase
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uint16 vertical_phase0_uv;
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uint16 vertical_phase1_uv;
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// (0x24) HORZ_PH - horizontal phase
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uint16 horizontal_phase_rgb;
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uint16 horizontal_phase_uv;
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// (0x28) INIT_PHS - initial phase shift
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uint32 initial_vertical_phase0_shift_rgb0 : 4;
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uint32 initial_vertical_phase1_shift_rgb0 : 4;
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uint32 initial_horizontal_phase_shift_rgb0 : 4;
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uint32 initial_vertical_phase0_shift_uv : 4;
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uint32 initial_vertical_phase1_shift_uv : 4;
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uint32 initial_horizontal_phase_shift_uv : 4;
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uint32 _reserved0 : 8;
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// (0x2c) DWINPOS - destination window position
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uint16 window_left;
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uint16 window_top;
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// (0x30) DWINSZ - destination window size
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uint16 window_width;
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uint16 window_height;
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// (0x34) SWIDTH - source width
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uint16 source_width_rgb;
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uint16 source_width_uv;
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// (0x38) SWITDHSW - source width in 8 byte steps
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uint16 source_bytes_per_row_rgb;
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uint16 source_bytes_per_row_uv;
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uint16 source_height_rgb;
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uint16 source_height_uv;
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overlay_scale scale_rgb;
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overlay_scale scale_uv;
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// (0x48) OCLRC0 - overlay color correction 0
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uint32 brightness_correction : 8; // signed, -128 to 127
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uint32 _reserved1 : 10;
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uint32 contrast_correction : 9; // fixed point: 3.6 bits
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uint32 _reserved2 : 5;
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// (0x4c) OCLRC1 - overlay color correction 1
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uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits
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uint32 _reserved3 : 6;
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uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits
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uint32 _reserved4 : 5;
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// (0x50) DCLRKV - destination color key value
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uint32 color_key_blue : 8;
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uint32 color_key_green : 8;
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uint32 color_key_red : 8;
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uint32 _reserved5 : 8;
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// (0x54) DCLRKM - destination color key mask
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uint32 color_key_mask_blue : 8;
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uint32 color_key_mask_green : 8;
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uint32 color_key_mask_red : 8;
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uint32 _reserved6 : 7;
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uint32 color_key_enabled : 1;
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// (0x58) SCHRKVH - source chroma key high value
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uint32 source_chroma_key_high_red : 8;
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uint32 source_chroma_key_high_blue : 8;
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uint32 source_chroma_key_high_green : 8;
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uint32 _reserved7 : 8;
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// (0x5c) SCHRKVL - source chroma key low value
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uint32 source_chroma_key_low_red : 8;
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uint32 source_chroma_key_low_blue : 8;
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uint32 source_chroma_key_low_green : 8;
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uint32 _reserved8 : 8;
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// (0x60) SCHRKEN - source chroma key enable
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uint32 _reserved9 : 24;
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uint32 source_chroma_key_red_enabled : 1;
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uint32 source_chroma_key_blue_enabled : 1;
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uint32 source_chroma_key_green_enabled : 1;
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uint32 _reserved10 : 5;
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// (0x64) OCONFIG - overlay configuration
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uint32 _reserved11 : 3;
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uint32 color_control_output_mode : 1;
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uint32 yuv_to_rgb_bypass : 1;
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uint32 _reserved12 : 11;
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uint32 gamma2_enabled : 1;
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uint32 _reserved13 : 1;
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uint32 select_pipe : 1;
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uint32 slot_time : 8;
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uint32 _reserved14 : 5;
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// (0x68) OCOMD - overlay command
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uint32 overlay_enabled : 1;
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uint32 active_field : 1;
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uint32 active_buffer : 2;
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uint32 test_mode : 1;
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uint32 buffer_field_mode : 1;
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uint32 _reserved15 : 1;
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uint32 tv_flip_field_enabled : 1;
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uint32 _reserved16 : 1;
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uint32 tv_flip_field_parity : 1;
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uint32 source_format : 4;
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uint32 ycbcr422_order : 2;
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uint32 _reserved18 : 1;
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uint32 mirroring_mode : 2;
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uint32 _reserved19 : 13;
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uint32 _reserved20;
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uint32 start_0y;
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uint32 start_1y;
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uint32 start_0u;
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uint32 start_0v;
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uint32 start_1u;
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uint32 start_1v;
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uint32 _reserved21[6];
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#if 0
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// (0x70) AWINPOS - alpha blend window position
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uint32 awinpos;
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// (0x74) AWINSZ - alpha blend window size
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uint32 awinsz;
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uint32 _reserved21[10];
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#endif
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// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
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// the next two registers switch the usual Y/RGB vs. UV order)
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uint16 horizontal_scale_uv;
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uint16 horizontal_scale_rgb;
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// (0xa4) UVSCALEV - vertical downscale
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uint16 vertical_scale_uv;
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uint16 vertical_scale_rgb;
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uint32 _reserved22[86];
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// (0x200) polyphase filter coefficients
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uint16 vertical_coefficients_rgb[128];
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uint16 horizontal_coefficients_rgb[128];
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uint32 _reserved23[64];
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// (0x500)
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uint16 vertical_coefficients_uv[128];
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uint16 horizontal_coefficients_uv[128];
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};
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struct hardware_status {
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uint32 interrupt_status_register;
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uint32 _reserved0[3];
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void* primary_ring_head_storage;
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uint32 _reserved1[3];
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void* secondary_ring_0_head_storage;
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void* secondary_ring_1_head_storage;
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uint32 _reserved2[2];
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void* binning_head_storage;
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uint32 _reserved3[3];
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uint32 store[1008];
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};
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#endif /* RADEON_HD_H */
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