remove a bunch of leftover Intel extreme registers, add in relevant ATI r600 registers from Xorg driver, remove kATIVendorId from driver and use vendor var from global private header
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41073 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
parent
3ca4651192
commit
75f51fc787
@ -4,6 +4,7 @@
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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* Alexander von Gluck IV, kallisti5@unixzen.com
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*/
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#ifndef RADEON_HD_H
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#define RADEON_HD_H
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@ -16,37 +17,16 @@
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#include <PCI.h>
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#define VENDOR_ID_ATI 0x8086
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#define VENDOR_ID_ATI 0x1002
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#define RADEON_TYPE_FAMILY_MASK 0xf000
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#define RADEON_TYPE_GROUP_MASK 0xfff0
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#define RADEON_TYPE_MODEL_MASK 0xffff
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// families
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#define RADEON_TYPE_7xx 0x1000
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#define RADEON_TYPE_8xx 0x2000
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#define RADEON_TYPE_9xx 0x4000
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// groups
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#define RADEON_TYPE_83x (RADEON_TYPE_8xx | 0x0010)
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#define RADEON_TYPE_85x (RADEON_TYPE_8xx | 0x0020)
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#define RADEON_TYPE_91x (RADEON_TYPE_9xx | 0x0040)
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#define RADEON_TYPE_94x (RADEON_TYPE_9xx | 0x0080)
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#define RADEON_TYPE_96x (RADEON_TYPE_9xx | 0x0100)
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#define RADEON_TYPE_Gxx (RADEON_TYPE_9xx | 0x0200)
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#define RADEON_TYPE_G4x (RADEON_TYPE_9xx | 0x0400)
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// models
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#define RADEON_TYPE_MOBILE 0x0008
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#define RADEON_TYPE_915 (RADEON_TYPE_91x)
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#define RADEON_TYPE_945 (RADEON_TYPE_94x)
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#define RADEON_TYPE_945M (RADEON_TYPE_94x | RADEON_TYPE_MOBILE)
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#define RADEON_TYPE_965 (RADEON_TYPE_96x)
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#define RADEON_TYPE_965M (RADEON_TYPE_96x | RADEON_TYPE_MOBILE)
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#define RADEON_TYPE_G33 (RADEON_TYPE_Gxx)
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#define RADEON_TYPE_G45 (RADEON_TYPE_G4x)
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#define RADEON_TYPE_GM45 (RADEON_TYPE_G4x | RADEON_TYPE_MOBILE)
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#define DEVICE_NAME "radeon_hd"
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#define RADEON_ACCELERANT_NAME "radeon_hd.accelerant"
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struct DeviceType {
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uint32 type;
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@ -178,208 +158,46 @@ struct radeon_free_graphics_memory {
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uint32 buffer_base;
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};
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//----------------------------------------------------------
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// ----------------------------------------------------------
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// Register definitions, taken from X driver
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// PCI bridge memory management
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#define RADEON_GRAPHICS_MEMORY_CONTROL 0x52 // GGC - (G)MCH Graphics Control Register
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#define MEMORY_CONTROL_ENABLED 0x0004
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#define MEMORY_MASK 0x0001
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#define STOLEN_MEMORY_MASK 0x00f0
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#define i965_GTT_MASK 0x000e
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#define G33_GTT_MASK 0x0300
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#define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask
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// ATI r600 specific
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enum _r6xxRegs {
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/* MCLK */
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R6_MCLK_PWRMGT_CNTL = 0x620,
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/* I2C */
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R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */
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R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */
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R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */
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R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */
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R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */
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R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */
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R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */
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R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */
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R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */
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R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */
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R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */
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R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */
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R6_DC_I2C_DATA = 0x7D74, /* (RW) */
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R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */
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R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */
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R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */
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R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */
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R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */
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R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */
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R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */
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R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */
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R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */
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R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */
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R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */
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R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */
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R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */
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R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */
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R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */
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R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */
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R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */
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};
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// models i830 and up
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#define i830_LOCAL_MEMORY_ONLY 0x10
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#define i830_STOLEN_512K 0x20
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#define i830_STOLEN_1M 0x30
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#define i830_STOLEN_8M 0x40
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#define i830_FRAME_BUFFER_64M 0x01
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#define i830_FRAME_BUFFER_128M 0x00
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// models i855 and up
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#define i855_STOLEN_MEMORY_1M 0x10
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#define i855_STOLEN_MEMORY_4M 0x20
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#define i855_STOLEN_MEMORY_8M 0x30
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#define i855_STOLEN_MEMORY_16M 0x40
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#define i855_STOLEN_MEMORY_32M 0x50
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#define i855_STOLEN_MEMORY_48M 0x60
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#define i855_STOLEN_MEMORY_64M 0x70
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#define i855_STOLEN_MEMORY_128M 0x80
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#define i855_STOLEN_MEMORY_256M 0x90
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#define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select
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#define G4X_STOLEN_MEMORY_160MB 0xb0
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#define G4X_STOLEN_MEMORY_224MB 0xc0
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#define G4X_STOLEN_MEMORY_352MB 0xd0
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// graphics page translation table
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#define RADEON_PAGE_TABLE_CONTROL 0x02020
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#define PAGE_TABLE_ENABLED 0x00000001
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#define RADEON_PAGE_TABLE_ERROR 0x02024
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#define RADEON_HARDWARE_STATUS_PAGE 0x02080
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#define i915_GTT_BASE 0x1c
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#define i830_GTT_BASE 0x10000 // (- 0x2ffff)
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#define i830_GTT_SIZE 0x20000
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#define i965_GTT_BASE 0x80000 // (- 0xfffff)
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#define i965_GTT_SIZE 0x80000
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#define i965_GTT_128K (2 << 1)
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#define i965_GTT_256K (1 << 1)
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#define i965_GTT_512K (0 << 1)
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#define G33_GTT_1M (1 << 8)
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#define G33_GTT_2M (2 << 8)
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#define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size
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#define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech.
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#define G4X_GTT_2M_NO_IVT 0x300
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#define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech.
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#define G4X_GTT_3M_IVT 0xa00
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#define G4X_GTT_4M_IVT 0xb00
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#define GTT_ENTRY_VALID 0x01
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#define GTT_ENTRY_LOCAL_MEMORY 0x02
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#define GTT_PAGE_SHIFT 12
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// interrupts
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#define RADEON_INTERRUPT_ENABLED 0x020a0
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#define RADEON_INTERRUPT_IDENTITY 0x020a4
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#define RADEON_INTERRUPT_MASK 0x020a8
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#define RADEON_INTERRUPT_STATUS 0x020ac
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#define INTERRUPT_VBLANK (1 << 7)
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// ring buffer
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#define RADEON_PRIMARY_RING_BUFFER 0x02030
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#define RADEON_SECONDARY_RING_BUFFER_0 0x02100
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#define RADEON_SECONDARY_RING_BUFFER_1 0x02110
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// offsets for the ring buffer base registers above
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#define RING_BUFFER_TAIL 0x0
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#define RING_BUFFER_HEAD 0x4
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#define RING_BUFFER_START 0x8
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#define RING_BUFFER_CONTROL 0xc
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#define RADEON_RING_BUFFER_SIZE_MASK 0x001ff000
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#define RADEON_RING_BUFFER_HEAD_MASK 0x001ffffc
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#define RADEON_RING_BUFFER_ENABLED 1
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// display ports
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#define RADEON_DISPLAY_A_ANALOG_PORT 0x61100
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#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
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#define DISPLAY_MONITOR_PIPE_B (1UL << 30)
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#define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15)
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#define DISPLAY_MONITOR_MODE_MASK (3UL << 10)
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#define DISPLAY_MONITOR_ON 0
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#define DISPLAY_MONITOR_SUSPEND (1UL << 10)
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#define DISPLAY_MONITOR_STAND_BY (2UL << 10)
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#define DISPLAY_MONITOR_OFF (3UL << 10)
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#define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3)
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#define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3)
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#define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3)
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#define RADEON_DISPLAY_A_DIGITAL_PORT 0x61120
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#define RADEON_DISPLAY_C_DIGITAL 0x61160
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#define RADEON_DISPLAY_LVDS_PORT 0x61180
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#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
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#define LVDS_POST2_RATE_FAST 7
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#define LVDS_CLKB_POWER_MASK (3 << 4)
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#define LVDS_CLKB_POWER_UP (3 << 4)
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#define LVDS_PORT_EN (1 << 31)
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#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
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#define LVDS_PIPEB_SELECT (1 << 30)
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#define LVDS_B0B3PAIRS_POWER_UP (3 << 2)
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#define LVDS_PLL_MODE_LVDS (2 << 26)
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// PLL flags
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#define DISPLAY_PLL_ENABLED (1UL << 31)
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#define DISPLAY_PLL_2X_CLOCK (1UL << 30)
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#define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29)
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#define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28)
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#define DISPLAY_PLL_MODE_ANALOG (1UL << 26)
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#define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24)
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#define DISPLAY_PLL_DIVIDE_4X (1UL << 23)
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#define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21)
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#define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000
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#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000
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#define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16
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#define DISPLAY_PLL_DIVISOR_1 (1UL << 8)
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#define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000
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#define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00
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#define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f
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#define DISPLAY_PLL_N_DIVISOR_SHIFT 16
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#define DISPLAY_PLL_M1_DIVISOR_SHIFT 8
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#define DISPLAY_PLL_M2_DIVISOR_SHIFT 0
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#define DISPLAY_PLL_PULSE_PHASE_SHIFT 9
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// display A
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#define RADEON_DISPLAY_A_HTOTAL 0x60000
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#define RADEON_DISPLAY_A_HBLANK 0x60004
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#define RADEON_DISPLAY_A_HSYNC 0x60008
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#define RADEON_DISPLAY_A_VTOTAL 0x6000c
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#define RADEON_DISPLAY_A_VBLANK 0x60010
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#define RADEON_DISPLAY_A_VSYNC 0x60014
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#define RADEON_DISPLAY_A_IMAGE_SIZE 0x6001c
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#define RADEON_DISPLAY_A_CONTROL 0x70180
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#define RADEON_DISPLAY_A_BASE 0x70184
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#define RADEON_DISPLAY_A_BYTES_PER_ROW 0x70188
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#define RADEON_DISPLAY_A_SURFACE 0x7019c // i965 and up only
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#define DISPLAY_CONTROL_ENABLED (1UL << 31)
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#define DISPLAY_CONTROL_GAMMA (1UL << 30)
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#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
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#define DISPLAY_CONTROL_CMAP8 (2UL << 26)
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#define DISPLAY_CONTROL_RGB15 (4UL << 26)
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#define DISPLAY_CONTROL_RGB16 (5UL << 26)
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#define DISPLAY_CONTROL_RGB32 (6UL << 26)
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#define RADEON_VGA_DISPLAY_CONTROL 0x71400
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#define VGA_DISPLAY_DISABLED (1UL << 31)
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#define RADEON_DISPLAY_A_PALETTE 0x0a000
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#define RADEON_DISPLAY_A_PIPE_CONTROL 0x70008
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#define DISPLAY_PIPE_ENABLED (1UL << 31)
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#define RADEON_DISPLAY_A_PIPE_STATUS 0x70024
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#define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17)
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#define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1)
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#define RADEON_DISPLAY_A_PLL 0x06014
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#define RADEON_DISPLAY_A_PLL_DIVISOR_0 0x06040
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#define RADEON_DISPLAY_A_PLL_DIVISOR_1 0x06044
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// display B
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#define RADEON_DISPLAY_B_HTOTAL 0x61000
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#define RADEON_DISPLAY_B_HBLANK 0x61004
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#define RADEON_DISPLAY_B_HSYNC 0x61008
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#define RADEON_DISPLAY_B_VTOTAL 0x6100c
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#define RADEON_DISPLAY_B_VBLANK 0x61010
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#define RADEON_DISPLAY_B_VSYNC 0x61014
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#define RADEON_DISPLAY_B_DIGITAL_PORT 0x61140
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#define RADEON_DISPLAY_B_PIPE_SIZE 0x71190
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#define RADEON_DISPLAY_B_PIPE_CONTROL 0x71008
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#define RADEON_DISPLAY_B_CONTROL 0x71180
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#define RADEON_DISPLAY_B_BASE 0x71184
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#define RADEON_DISPLAY_B_BYTES_PER_ROW 0x71188
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#define RADEON_DISPLAY_B_POS 0x7118C
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#define RADEON_DISPLAY_B_IMAGE_SIZE 0x6101c
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#define RADEON_DISPLAY_B_SURFACE 0x7119c // i965 and up only
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#define RADEON_DISPLAY_B_PALETTE 0x0a800
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#define RADEON_DISPLAY_B_PLL 0x06018
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#define RADEON_DISPLAY_B_PLL_MULTIPLIER_DIVISOR 0x06020
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#define RADEON_DISPLAY_B_PLL_DIVISOR_0 0x06048
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#define RADEON_DISPLAY_B_PLL_DIVISOR_1 0x0604c
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// LVDS panel
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#define RADEON_PANEL_STATUS 0x61200
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#define PANEL_STATUS_POWER_ON (1UL << 31)
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#define RADEON_PANEL_CONTROL 0x61204
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#define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0)
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#define RADEON_PANEL_FIT_CONTROL 0x61230
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#define RADEON_PANEL_FIT_RATIOS 0x61234
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// cursor
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#define RADEON_CURSOR_CONTROL 0x70080
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@ -396,14 +214,6 @@ struct radeon_free_graphics_memory {
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#define CURSOR_POSITION_NEGATIVE 0x8000
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#define CURSOR_POSITION_MASK 0x3fff
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// ring buffer commands
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#define COMMAND_NOOP 0x00
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#define COMMAND_WAIT_FOR_EVENT (0x03 << 23)
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#define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16)
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#define COMMAND_FLUSH (0x04 << 23)
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// overlay flip
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#define COMMAND_OVERLAY_FLIP (0x11 << 23)
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#define COMMAND_OVERLAY_CONTINUE (0 << 21)
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@ -425,28 +235,17 @@ struct radeon_free_graphics_memory {
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#define COMMAND_MODE_RGB16 0x01
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#define COMMAND_MODE_RGB32 0x03
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// i2c
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// display
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#define RADEON_I2C_IO_A 0x5010
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#define RADEON_I2C_IO_B 0x5014
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#define RADEON_I2C_IO_C 0x5018
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#define RADEON_I2C_IO_D 0x501c
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#define RADEON_I2C_IO_E 0x5020
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#define RADEON_I2C_IO_F 0x5024
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#define RADEON_I2C_IO_G 0x5028
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#define RADEON_I2C_IO_H 0x502c
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#define DISPLAY_CONTROL_ENABLED (1UL << 31)
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#define DISPLAY_CONTROL_GAMMA (1UL << 30)
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#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
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#define DISPLAY_CONTROL_CMAP8 (2UL << 26)
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#define DISPLAY_CONTROL_RGB15 (4UL << 26)
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#define DISPLAY_CONTROL_RGB16 (5UL << 26)
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#define DISPLAY_CONTROL_RGB32 (6UL << 26)
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#define I2C_CLOCK_DIRECTION_MASK (1 << 0)
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#define I2C_CLOCK_DIRECTION_OUT (1 << 1)
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#define I2C_CLOCK_VALUE_MASK (1 << 2)
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#define I2C_CLOCK_VALUE_OUT (1 << 3)
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#define I2C_CLOCK_VALUE_IN (1 << 4)
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#define I2C_DATA_DIRECTION_MASK (1 << 8)
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#define I2C_DATA_DIRECTION_OUT (1 << 9)
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#define I2C_DATA_VALUE_MASK (1 << 10)
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#define I2C_DATA_VALUE_OUT (1 << 11)
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#define I2C_DATA_VALUE_IN (1 << 12)
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#define I2C_RESERVED ((1 << 13) | (1 << 5))
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// PCI bridge memory management
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// overlay
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@ -628,16 +427,6 @@ struct overlay_registers {
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uint16 horizontal_coefficients_uv[128];
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};
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||||
|
||||
// i965 overlay support is currently realized using its 3D hardware
|
||||
#define RADEON_i965_OVERLAY_STATE_SIZE 36864
|
||||
#define RADEON_i965_3D_CONTEXT_SIZE 32768
|
||||
|
||||
inline bool
|
||||
radeon_uses_physical_overlay(radeon_shared_info &info)
|
||||
{
|
||||
return !info.device_type.InGroup(RADEON_TYPE_Gxx);
|
||||
}
|
||||
|
||||
|
||||
struct hardware_status {
|
||||
uint32 interrupt_status_register;
|
||||
|
||||
@ -83,9 +83,6 @@ const struct supported_device {
|
||||
};
|
||||
|
||||
|
||||
const uint32 kATIVendorId = 0x1002;
|
||||
|
||||
|
||||
int32 api_version = B_CUR_DRIVER_API_VERSION;
|
||||
|
||||
|
||||
@ -104,7 +101,7 @@ get_next_radeon_hd(int32 *_cookie, pci_info &info, uint32 &type)
|
||||
|
||||
for (; gPCI->get_nth_pci_info(index, &info) == B_OK; index++) {
|
||||
// check vendor
|
||||
if (info.vendor_id != kATIVendorId
|
||||
if (info.vendor_id != VENDOR_ID_ATI
|
||||
|| info.class_base != PCI_display
|
||||
|| info.class_sub != PCI_vga)
|
||||
continue;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user