369 lines
11 KiB
C
369 lines
11 KiB
C
/* $NetBSD: dwlpx.c,v 1.23 2001/07/27 00:25:20 thorpej Exp $ */
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/*
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* Copyright (c) 1997 by Matthew Jacob
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* NASA AMES Research Center.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.23 2001/07/27 00:25:20 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <machine/autoconf.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <alpha/tlsb/tlsbreg.h>
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#include <alpha/tlsb/kftxxvar.h>
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#include <alpha/tlsb/kftxxreg.h>
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#include <alpha/pci/dwlpxreg.h>
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#include <alpha/pci/dwlpxvar.h>
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#include <alpha/pci/pci_kn8ae.h>
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#define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr)))
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#define DWLPX_SYSBASE(sc) \
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((((unsigned long)((sc)->dwlpx_node - 4)) << 36) | \
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(((unsigned long) (sc)->dwlpx_hosenum) << 34) | \
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(1LL << 39))
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static int dwlpxmatch __P((struct device *, struct cfdata *, void *));
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static void dwlpxattach __P((struct device *, struct device *, void *));
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struct cfattach dwlpx_ca = {
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sizeof(struct dwlpx_softc), dwlpxmatch, dwlpxattach
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};
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extern struct cfdriver dwlpx_cd;
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static int dwlpxprint __P((void *, const char *));
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void dwlpx_errintr(void *, u_long vec);
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static int
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dwlpxprint(aux, pnp)
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void *aux;
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const char *pnp;
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{
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register struct pcibus_attach_args *pba = aux;
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/* only PCIs can attach to DWLPX's; easy. */
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if (pnp)
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printf("%s at %s", pba->pba_busname, pnp);
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printf(" bus %d", pba->pba_bus);
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return (UNCONF);
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}
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static int
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dwlpxmatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct kft_dev_attach_args *ka = aux;
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if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0)
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return (0);
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return (1);
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}
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static void
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dwlpxattach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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static int once = 0;
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struct dwlpx_softc *sc = (struct dwlpx_softc *)self;
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struct dwlpx_config *ccp = &sc->dwlpx_cc;
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struct kft_dev_attach_args *ka = aux;
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struct pcibus_attach_args pba;
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u_int32_t pcia_present;
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sc->dwlpx_node = ka->ka_node;
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sc->dwlpx_dtype = ka->ka_dtype;
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sc->dwlpx_hosenum = ka->ka_hosenum;
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dwlpx_init(sc);
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dwlpx_dma_init(ccp);
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pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
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printf(": PCIA rev. %d, STD I/O %spresent, %dK S/G entries\n",
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(pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK,
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(pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "",
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sc->dwlpx_sgmapsz == DWLPX_SG128K ? 128 : 32);
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#if 0
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{
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int hpc, slot, slotval;
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const char *str;
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for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) {
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for (slot = 0; slot < 4; slot++) {
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slotval = (pcia_present >>
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PCIA_PRESENT_SLOTSHIFT(hpc, slot)) &
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PCIA_PRESENT_SLOT_MASK;
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if (slotval == PCIA_PRESENT_SLOT_NONE)
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continue;
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switch (slotval) {
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case PCIA_PRESENT_SLOT_25W:
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str = "25";
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break;
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case PCIA_PRESENT_SLOT_15W:
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str = "15";
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break;
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case PCIA_PRESENT_SLOW_7W:
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default: /* XXX gcc */
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str = "7.5";
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break;
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}
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printf("%s: hpc %d slot %d: %s watt module\n",
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sc->dwlpx_dev.dv_xname, hpc, slot, str);
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}
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}
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}
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#endif
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if (once == 0) {
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/*
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* Set up interrupts
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*/
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pci_kn8ae_pickintr(&sc->dwlpx_cc, 1);
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once++;
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} else {
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pci_kn8ae_pickintr(&sc->dwlpx_cc, 0);
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}
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/*
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* Attach PCI bus
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*/
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pba.pba_busname = "pci";
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pba.pba_iot = &sc->dwlpx_cc.cc_iot;
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pba.pba_memt = &sc->dwlpx_cc.cc_memt;
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pba.pba_dmat = /* start with direct, may change... */
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alphabus_dma_get_tag(&sc->dwlpx_cc.cc_dmat_direct, ALPHA_BUS_PCI);
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pba.pba_pc = &sc->dwlpx_cc.cc_pc;
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pba.pba_bus = 0;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
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PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
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config_found(self, &pba, dwlpxprint);
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}
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void
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dwlpx_init(sc)
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struct dwlpx_softc *sc;
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{
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u_int32_t ctl;
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struct dwlpx_config *ccp = &sc->dwlpx_cc;
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unsigned long vec, ls = DWLPX_SYSBASE(sc);
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int i;
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if (ccp->cc_initted == 0) {
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/*
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* On reads, you get a fault if you read a nonexisted HPC.
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* We know the internal KFTIA hose (hose 0) has only 2 HPCs,
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* but we can also actually probe for HPCs.
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* Assume at least one.
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*/
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for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC;
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sc->dwlpx_nhpc++) {
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if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls),
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sizeof (ctl)) != 0) {
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break;
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}
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}
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if (sc->dwlpx_nhpc != NHPC) {
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/* clear (potential) Illegal CSR Address Error */
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REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) =
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PCIA_ERR_ALLERR;
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}
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dwlpx_bus_io_init(&ccp->cc_iot, ccp);
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dwlpx_bus_mem_init(&ccp->cc_memt, ccp);
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}
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dwlpx_pci_init(&ccp->cc_pc, ccp);
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ccp->cc_sc = sc;
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/*
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* Establish a precalculated base for convenience's sake.
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*/
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ccp->cc_sysbase = ls;
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/*
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* If there are only 2 HPCs, then the 'present' register is not
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* implemented, so there will only ever be 32K SG entries. Otherwise
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* any revision greater than zero will have 128K entries.
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*/
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ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
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if (sc->dwlpx_nhpc == 2) {
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sc->dwlpx_sgmapsz = DWLPX_SG32K;
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#if 0
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/*
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* As of 2/25/98- When I enable SG128K, and then have to flip
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* TBIT below, I get bad SGRAM errors. We'll fix this later
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* if this gets important.
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*/
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} else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
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sc->dwlpx_sgmapsz = DWLPX_SG128K;
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#endif
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} else {
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sc->dwlpx_sgmapsz = DWLPX_SG32K;
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}
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/*
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* Set up interrupt stuff for this DWLPX.
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*
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* Note that all PCI interrupt pins are disabled at this time.
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*
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* Do this even for all HPCs- even for the nonexistent
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* one on hose zero of a KFTIA.
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*/
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vec = scb_alloc(dwlpx_errintr, sc);
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if (vec == SCB_ALLOC_FAILED)
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panic("%s: unable to allocate error vector",
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sc->dwlpx_dev.dv_xname);
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printf("%s: error interrupt at vector 0x%lx\n",
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sc->dwlpx_dev.dv_xname, vec);
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for (i = 0; i < NHPC; i++) {
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REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT;
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REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec;
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}
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/*
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* Establish HAE values, as well as make sure of sanity elsewhere.
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*/
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
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ctl &= 0x0fffffff;
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ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
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/*
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* I originally also had it or'ing in 3, which makes no sense.
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*/
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ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB;
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/*
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* Only valid if we're attached to a KFTIA or a KTHA.
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*/
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ctl |= PCIA_CTL_3UP;
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ctl |= PCIA_CTL_CUTENA;
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/*
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* Fit in appropriate S/G Map Ram size.
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*/
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if (sc->dwlpx_sgmapsz == DWLPX_SG32K)
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ctl |= PCIA_CTL_SG32K;
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else if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
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ctl |= PCIA_CTL_SG128K;
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else
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ctl |= PCIA_CTL_SG32K;
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REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl;
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}
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/*
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* Enable TBIT if required
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*/
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if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
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REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1;
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alpha_mb();
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ccp->cc_initted = 1;
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}
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void
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dwlpx_errintr(arg, vec)
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void *arg;
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unsigned long vec;
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{
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struct dwlpx_softc *sc = arg;
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struct dwlpx_config *ccp = &sc->dwlpx_cc;
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int i;
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struct {
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u_int32_t err;
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u_int32_t addr;
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} hpcs[NHPC];
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase);
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hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase);
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}
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printf("%s: node %d hose %d error interrupt\n",
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sc->dwlpx_dev.dv_xname, sc->dwlpx_node, sc->dwlpx_hosenum);
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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if ((hpcs[i].err & PCIA_ERR_ERROR) == 0)
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continue;
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printf("\tHPC %d: ERR=0x%08x; DMA %s Memory, "
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"Failing Address 0x%x\n",
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i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" :
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"read from", hpcs[i].addr & ~3);
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if (hpcs[i].err & PCIA_ERR_SERR_L)
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printf("\t PCI device asserted SERR_L\n");
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if (hpcs[i].err & PCIA_ERR_ILAT)
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printf("\t Incremental Latency Exceeded\n");
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if (hpcs[i].err & PCIA_ERR_SGPRTY)
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printf("\t CPU access of SG RAM Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_ILLCSR)
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printf("\t Illegal CSR Address Error\n");
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if (hpcs[i].err & PCIA_ERR_PCINXM)
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printf("\t Nonexistent PCI Address Error\n");
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if (hpcs[i].err & PCIA_ERR_DSCERR)
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printf("\t PCI Target Disconnect Error\n");
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if (hpcs[i].err & PCIA_ERR_ABRT)
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printf("\t PCI Target Abort Error\n");
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if (hpcs[i].err & PCIA_ERR_WPRTY)
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printf("\t PCI Write Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_DPERR)
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printf("\t PCI Data Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_APERR)
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printf("\t PCI Address Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_DFLT)
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printf("\t SG Map RAM Invalid Entry Error\n");
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if (hpcs[i].err & PCIA_ERR_DPRTY)
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printf("\t DMA access of SG RAM Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_DRPERR)
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printf("\t DMA Read Return Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_MABRT)
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printf("\t PCI Master Abort Error\n");
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if (hpcs[i].err & PCIA_ERR_CPRTY)
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printf("\t CSR Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_COVR)
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printf("\t CSR Overrun Error\n");
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if (hpcs[i].err & PCIA_ERR_MBPERR)
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printf("\t Mailbox Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_MBILI)
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printf("\t Mailbox Illegal Length Error\n");
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REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err;
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}
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}
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