Aren/NetBSD
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11 Commits

Author SHA1 Message Date
matt
f82647e665 Make the 85xx get closer to spinning up the secondary CPUs. 
Don't assume TLB1[0] has the mapping for VA/PA 0.
Make sure the TLB1 entries that map physical memory have the M (memory
coherent) bit set.
 2012-11-27 19:24:45 +00:00
matt
95b282e26a When dealing with kernel invalidations, make sure to use context-synchronizing 
instructions.
 2012-07-25 22:11:36 +00:00
matt
1d4f8f38c8 Don't assume 1:1 PA:VA mapping 2012-07-18 18:50:46 +00:00
matt
ab37920fbd Fix some SHIFTOUT to SHIFTIN 
Add a lookup of tlb1 by pa.  fix comparisions of xtlb entries by using
masks.  (since xtlb can looked up by pa & va and va may not equal pa).
 2012-07-18 18:29:22 +00:00
matt
f461970939 Add support PMAP_MINIMALTLB option. This changes the default use of TLB1 
entries to map all of physical memory to using two TLB1 entries, one for
mapping text and one for data.  The rest of memory is mapped using the
page table which is updated as needed.  This is used to trap memory
corruption issues.
 2012-03-29 15:48:20 +00:00
matt
4a40b01453 Modify mapiodev to take a third argument indicating whether the space 
should be prefetchable (true) or not (false).
 2011-06-30 00:52:55 +00:00
matt
198d4bce95 Don't use TLB1 entries for device access if they are writethrough or not 
cache-inhibited.
 2011-06-29 23:15:55 +00:00
matt
79492abbce Cleanup comments in pmap_tlb.c. Attach tlb evcnts. 
eliminate ti_mask
Cleanup some of the MP code.  Conditionalize shootdown code.
 2011-06-23 05:42:27 +00:00
matt
8b35e8e3c4 Switch to using the common <common/pmap/tlb/tlb.h> 2011-06-23 01:27:20 +00:00
matt
01fd92550a Remove <machine/atomic.h>; use <sys/atomic.h> instead. 
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
 2011-06-05 16:52:22 +00:00
matt
b8ea2c8cad Add support for BookE Freescale MPC85xx (e500 core) processors. 
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.
 2011-01-18 01:02:52 +00:00