Make the 85xx get closer to spinning up the secondary CPUs.
Don't assume TLB1[0] has the mapping for VA/PA 0. Make sure the TLB1 entries that map physical memory have the M (memory coherent) bit set.
This commit is contained in:
matt
parent
9dc12b580b
commit
f82647e665
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@ -1,3 +1,31 @@
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/*-
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* Copyright (c) 2011, 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* r3 = fdt pointer (ignored)
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@ -11,8 +39,6 @@
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.p2align 5
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ENTRY_NOPROFILE(e500_spinup_trampoline)
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stw %r7, 4(%r0) /* r7 to 4 */
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lis %r31, 0xdeadbeef@h
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ori %r31, %r31, 0xdeadbeef@l
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mr %r30, %r31
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@ -49,16 +75,38 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
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*/
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lis %r20, _C_LABEL(cpu_hatch_data)@h
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ori %r20, %r20, _C_LABEL(cpu_hatch_data)@l
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sync
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/*
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* Ensure that the TLB entry we are using is memory coherent.
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*/
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lis %r0, (MASX_TLBSEL_MAKE(1)|MAS0_ESEL_MAKE(0))@h
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mtspr SPR_MAS0, %r0 /* setup MAS0 */
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lis %r3, (MAS1_V|MAS1_IPROT)@h /* V | IPROT */
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ori %r3, %r3, MASX_TSIZE_64MB /* and 64MB */
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mtspr SPR_MAS1, %r3 /* save MAS1 */
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li %r3, MAS2_M /* set M bit */
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mtspr SPR_MAS2, %r3 /* save MAS2 */
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li %r3, MAS3_SX|MAS3_SR|MAS3_SW /* set kernel RWX */
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mtspr SPR_MAS3, %r3 /* save MAS3 */
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tlbwe /* update entry */
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isync /* flush i-stream */
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sync /* sync memory. */
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li %r0, 0
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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eieio
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sync
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#if 0
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dcbf 0, %r20
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#endif
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lwz %r1, HATCH_SP(%r20) /* get hatch SP */
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lwz %r21, HATCH_CI(%r20) /* get cpu_info */
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mtsprg0 %r21 /* save cpu_info */
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lwz %r13, CI_CURLWP(%r21) /* load r13 with curlwp */
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mtsprg2 %r13 /* save it in sprg2 */
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addi %r0,%r21,CI_SAVELIFO /* get SAVE area start */
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mtsprg3 %r0 /* save it in sprg3 */
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/*
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* Now to synchronize timebase values. First to make sure HID0 is
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@ -102,6 +150,7 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
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li %r0, 2
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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sync
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/*
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* We have to setup the IVOR SPRs since the ones u-boot setup
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@ -146,15 +195,11 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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/*
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* Let's find out what TLB1[0] entry we are supposed to use.
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* Let's find out what TLB1 entry we are supposed to use.
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*/
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li %r3, 0
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lwz %r3, HATCH_TLBIDX(%r20)
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bl _C_LABEL(e500_tlb1_fetch)
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lwz %r28, 0(%r3) /* load the saved TLB1 entry */
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mtspr SPR_MAS0, %r28 /* place into SPRs */
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mtspr SPR_MAS1, %r29
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mtspr SPR_MAS2, %r30
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mtspr SPR_MAS3, %r31
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lmw %r28, 0(%r3) /* load the saved TLB1 entry */
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li %r0, 6
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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@ -182,6 +227,30 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
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li %r0, 8
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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/*
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* Let's clear TBL1[0] and TBL1[1]
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*/
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li %r8, 0
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mtspr SPR_MAS1, %r8
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mtspr SPR_MAS2, %r8
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mtspr SPR_MAS3, %r8
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mtspr SPR_MAS7, %r8
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lis %r8, (MASX_TLBSEL_MAKE(1)|MAS0_ESEL_MAKE(0))@h
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mtspr SPR_MAS0, %r8
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tlbwe
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lis %r8, (MASX_TLBSEL_MAKE(1)|MAS0_ESEL_MAKE(1))@h
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mtspr SPR_MAS0, %r8
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tlbwe
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/*
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* Now load the new TLB data into the MAS registers.
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*/
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mtspr SPR_MAS0, %r28 /* place into SPRs */
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mtspr SPR_MAS1, %r29
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mtspr SPR_MAS2, %r30
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mtspr SPR_MAS3, %r31
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tlbwe
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mtsrr0 %r5
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@ -196,13 +265,23 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
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li %r0, 10
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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/*
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* We now have our TLB1[0] in place. Now we need to load the rest of
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* TLB1 with our entries. After this is done, we should have access
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* to everything.
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*/
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bl _C_LABEL(e500_tlb1_sync)
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li %r0, 11
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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/*
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* Now we can use our stack...
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*/
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lwz %r0, CI_CURPCB(%r21)
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lwz %r1, PCB_SP(%r0)
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li %r0, 11
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li %r0, 12
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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/*
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@ -211,16 +290,6 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
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li %r0, 0
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stw %r0, HATCH_SP(%r20)
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li %r0, 12
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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/*
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* We now have our TLB1[0] in place. Now we need to load the rest of
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* TLB1 with our entries. After this is done, we should have access
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* to everything.
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*/
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bl _C_LABEL(e500_tlb1_sync)
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li %r0, 13
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stw %r0, HATCH_RUNNING(%r20) /* progress */
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@ -1,4 +1,4 @@
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/* $NetBSD: e500_tlb.c,v 1.11 2012/07/25 22:11:36 matt Exp $ */
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/* $NetBSD: e500_tlb.c,v 1.12 2012/11/27 19:24:46 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -38,7 +38,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.11 2012/07/25 22:11:36 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.12 2012/11/27 19:24:46 matt Exp $");
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#include <sys/param.h>
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@ -202,6 +202,7 @@ hwtlb_write(const struct e500_hwtlb hwtlb, bool needs_sync)
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*/
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if (hwtlb.hwtlb_mas1 & MAS1_V) {
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mtspr(SPR_MAS3, hwtlb.hwtlb_mas3);
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//mtspr(SPR_MAS7, 0);
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}
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#if 0
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@ -543,6 +544,7 @@ e500_tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert)
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}
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mtspr(SPR_MAS2, hwtlb.hwtlb_mas2);
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mtspr(SPR_MAS3, hwtlb.hwtlb_mas3);
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//mtspr(SPR_MAS7, 0);
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__asm volatile("tlbwe");
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if (asid == KERNEL_PID)
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__asm volatile("isync\n\tsync");
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@ -641,11 +643,6 @@ e500_tlb_walk(void *ctx, bool (*func)(void *, vaddr_t, uint32_t, uint32_t))
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mtspr(SPR_MAS2, epn);
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__asm volatile("tlbre");
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hwtlb.hwtlb_mas1 = mfspr(SPR_MAS1);
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/*
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* If this is a valid entry for AS space 1 and
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* its asid matches the constraints of the caller,
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* clear its valid bit.
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*/
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if (hwtlb.hwtlb_mas1 & MAS1_V) {
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hwtlb.hwtlb_mas2 = mfspr(SPR_MAS2);
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hwtlb.hwtlb_mas3 = mfspr(SPR_MAS3);
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@ -682,7 +679,7 @@ e500_tlb_lookup_xtlb_pa(vaddr_t pa, u_int *slotp)
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return NULL;
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}
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static struct e500_xtlb *
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struct e500_xtlb *
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e500_tlb_lookup_xtlb(vaddr_t va, u_int *slotp)
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{
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struct e500_tlb1 * const tlb1 = &e500_tlb1;
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@ -942,6 +939,15 @@ e500_tlb_init(vaddr_t endkernel, psize_t memsize)
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if (xtlb->e_tlb.tlb_va == 0
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|| xtlb->e_tlb.tlb_va + xtlb->e_tlb.tlb_size <= memsize) {
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memmapped += xtlb->e_tlb.tlb_size;
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/*
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* Let make sure main memory is setup so it's memory
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* coherent. For some reason u-boot doesn't set it up
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* that way.
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*/
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if ((xtlb->e_hwtlb.hwtlb_mas2 & MAS2_M) == 0) {
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xtlb->e_hwtlb.hwtlb_mas2 |= MAS2_M;
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hwtlb_write(xtlb->e_hwtlb, true);
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}
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}
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}
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.9 2012/08/01 16:19:43 matt Exp $
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# $NetBSD: genassym.cf,v 1.10 2012/11/27 19:24:46 matt Exp $
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#-
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# Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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@ -110,4 +110,5 @@ define HATCH_RUNNING offsetof(struct cpu_hatch_data, hatch_running)
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define HATCH_SP offsetof(struct cpu_hatch_data, hatch_sp)
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define HATCH_TBU offsetof(struct cpu_hatch_data, hatch_tbu)
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define HATCH_TBL offsetof(struct cpu_hatch_data, hatch_tbl)
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define HATCH_TLBIDX offsetof(struct cpu_hatch_data, hatch_tlbidx)
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endif
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@ -1,4 +1,4 @@
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/* $NetBSD: e500var.h,v 1.6 2012/07/27 22:24:13 matt Exp $ */
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/* $NetBSD: e500var.h,v 1.7 2012/11/27 19:24:47 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -91,6 +91,9 @@ void e500_tlb1_sync(void);
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void e500_ipi_halt(void);
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void e500_spinup_trampoline(void);
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void e500_cpu_hatch(struct cpu_info *);
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struct e500_xtlb *
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e500_tlb_lookup_xtlb(vaddr_t, u_int *);
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void pq3gpio_attach(device_t, device_t, void *);
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.94 2012/10/20 14:42:15 kiyohara Exp $ */
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/* $NetBSD: cpu.h,v 1.95 2012/11/27 19:24:45 matt Exp $ */
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/*
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* Copyright (C) 1999 Wolfgang Solfrank.
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@ -170,6 +170,7 @@ struct cpu_hatch_data {
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#endif
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#if defined(PPC_BOOKE)
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vaddr_t hatch_sp;
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u_int hatch_tlbidx;
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#endif
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};
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