Add support PMAP_MINIMALTLB option. This changes the default use of TLB1
entries to map all of physical memory to using two TLB1 entries, one for mapping text and one for data. The rest of memory is mapped using the page table which is updated as needed. This is used to trap memory corruption issues.
This commit is contained in:
matt
parent
271a309329
commit
f461970939
@ -1,4 +1,4 @@
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/* $NetBSD: booke_pmap.c,v 1.12 2012/02/02 18:59:44 para Exp $ */
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/* $NetBSD: booke_pmap.c,v 1.13 2012/03/29 15:48:20 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -38,7 +38,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: booke_pmap.c,v 1.12 2012/02/02 18:59:44 para Exp $");
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__KERNEL_RCSID(0, "$NetBSD: booke_pmap.c,v 1.13 2012/03/29 15:48:20 matt Exp $");
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#include <sys/param.h>
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#include <sys/kcore.h>
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@ -59,6 +59,8 @@ __KERNEL_RCSID(0, "$NetBSD: booke_pmap.c,v 1.12 2012/02/02 18:59:44 para Exp $")
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CTASSERT(sizeof(struct pmap_segtab) == NBPG);
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struct pmap_segtab pmap_kernel_segtab;
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void
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pmap_procwr(struct proc *p, vaddr_t va, size_t len)
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{
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@ -120,30 +122,46 @@ pmap_md_direct_mapped_vaddr_to_paddr(vaddr_t va)
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return (paddr_t) va;
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}
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#ifdef PMAP_MINIMALTLB
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static pt_entry_t *
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kvtopte(const struct pmap_segtab *stp, vaddr_t va)
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{
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pt_entry_t * const ptep = stp->seg_tab[va >> SEGSHIFT];
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if (ptep == NULL)
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return NULL;
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return &ptep[(va & SEGOFSET) >> PAGE_SHIFT];
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}
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vaddr_t
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pmap_kvptefill(vaddr_t sva, vaddr_t eva, pt_entry_t pt_entry)
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{
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const struct pmap_segtab * const stp = pmap_kernel()->pm_segtab;
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KASSERT(sva == trunc_page(sva));
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pt_entry_t *ptep = kvtopte(stp, sva);
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for (; sva < eva; sva += NBPG) {
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*ptep++ = pt_entry ? (sva | pt_entry) : 0;
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}
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return sva;
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}
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#endif
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/*
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* Bootstrap the system enough to run with virtual memory.
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* firstaddr is the first unused kseg0 address (not page aligned).
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*/
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void
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vaddr_t
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pmap_bootstrap(vaddr_t startkernel, vaddr_t endkernel,
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const phys_ram_seg_t *avail, size_t cnt)
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phys_ram_seg_t *avail, size_t cnt)
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{
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for (size_t i = 0; i < cnt; i++) {
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printf(" uvm_page_physload(%#lx,%#lx,%#lx,%#lx,%d)",
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atop(avail[i].start),
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atop(avail[i].start + avail[i].size) - 1,
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atop(avail[i].start),
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atop(avail[i].start + avail[i].size) - 1,
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VM_FREELIST_DEFAULT);
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uvm_page_physload(
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atop(avail[i].start),
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atop(avail[i].start + avail[i].size) - 1,
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atop(avail[i].start),
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atop(avail[i].start + avail[i].size) - 1,
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VM_FREELIST_DEFAULT);
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}
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struct pmap_segtab * const stp = &pmap_kernel_segtab;
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pmap_tlb_info_init(&pmap_tlb0_info); /* init the lock */
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/*
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* Initialize the kernel segment table.
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*/
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pmap_kernel()->pm_segtab = stp;
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curcpu()->ci_pmap_kern_segtab = stp;
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KASSERT(endkernel == trunc_page(endkernel));
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/*
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* Compute the number of pages kmem_arena will have.
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@ -160,7 +178,7 @@ pmap_bootstrap(vaddr_t startkernel, vaddr_t endkernel,
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vsize_t bufsz = buf_memcalc();
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buf_setvalimit(bufsz);
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vsize_t nsegtabs = pmap_round_seg(VM_PHYS_SIZE
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vsize_t kv_nsegtabs = pmap_round_seg(VM_PHYS_SIZE
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+ (ubc_nwins << ubc_winshift)
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+ bufsz
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+ 16 * NCARGS
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@ -169,7 +187,7 @@ pmap_bootstrap(vaddr_t startkernel, vaddr_t endkernel,
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#ifdef SYSVSHM
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+ NBPG * shminfo.shmall
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#endif
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+ NBPG * nkmempages);
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+ NBPG * nkmempages) >> SEGSHIFT;
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/*
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* Initialize `FYI' variables. Note we're relying on
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@ -179,68 +197,100 @@ pmap_bootstrap(vaddr_t startkernel, vaddr_t endkernel,
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*/
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pmap_limits.avail_start = vm_physmem[0].start << PGSHIFT;
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pmap_limits.avail_end = vm_physmem[vm_nphysseg - 1].end << PGSHIFT;
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const vsize_t max_nsegtabs =
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const size_t max_nsegtabs =
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(pmap_round_seg(VM_MAX_KERNEL_ADDRESS)
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- pmap_trunc_seg(VM_MIN_KERNEL_ADDRESS)) / NBSEG;
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if (nsegtabs >= max_nsegtabs) {
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if (kv_nsegtabs >= max_nsegtabs) {
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pmap_limits.virtual_end = VM_MAX_KERNEL_ADDRESS;
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nsegtabs = max_nsegtabs;
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kv_nsegtabs = max_nsegtabs;
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} else {
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pmap_limits.virtual_end = VM_MIN_KERNEL_ADDRESS
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+ nsegtabs * NBSEG;
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+ kv_nsegtabs * NBSEG;
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}
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pmap_pvlist_lock_init(curcpu()->ci_ci.dcache_line_size);
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/*
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* Now actually allocate the kernel PTE array (must be done
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* after virtual_end is initialized).
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*/
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vaddr_t segtabs =
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uvm_pageboot_alloc(NBPG * nsegtabs + sizeof(struct pmap_segtab));
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const vaddr_t kv_segtabs = avail[0].start;
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KASSERT(kv_segtabs == endkernel);
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KASSERT(avail[0].size >= NBPG * kv_nsegtabs);
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printf(" kv_nsegtabs=%#"PRIxVSIZE, kv_nsegtabs);
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printf(" kv_segtabs=%#"PRIxVADDR, kv_segtabs);
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avail[0].start += NBPG * kv_nsegtabs;
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avail[0].size -= NBPG * kv_nsegtabs;
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endkernel += NBPG * kv_nsegtabs;
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/*
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* Initialize the kernel's two-level page level. This only wastes
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* an extra page for the segment table and allows the user/kernel
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* access to be common.
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*/
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struct pmap_segtab * const stp = (void *)segtabs;
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segtabs += round_page(sizeof(struct pmap_segtab));
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pt_entry_t **ptp = &stp->seg_tab[VM_MIN_KERNEL_ADDRESS >> SEGSHIFT];
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for (u_int i = 0; i < nsegtabs; i++, segtabs += NBPG) {
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*ptp++ = (void *)segtabs;
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pt_entry_t *ptep = (void *)kv_segtabs;
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memset(ptep, 0, NBPG * kv_nsegtabs);
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for (size_t i = 0; i < kv_nsegtabs; i++, ptep += NPTEPG) {
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*ptp++ = ptep;
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}
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pmap_kernel()->pm_segtab = stp;
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curcpu()->ci_pmap_kern_segtab = stp;
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printf(" kern_segtab=%p", stp);
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#if 0
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nsegtabs = (physmem + NPTEPG - 1) / NPTEPG;
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segtabs = uvm_pageboot_alloc(NBPG * nsegtabs);
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#if PMAP_MINIMALTLB
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const vsize_t dm_nsegtabs = (physmem + NPTEPG - 1) / NPTEPG;
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const vaddr_t dm_segtabs = avail[0].start;
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printf(" dm_nsegtabs=%#"PRIxVSIZE, dm_nsegtabs);
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printf(" dm_segtabs=%#"PRIxVADDR, dm_segtabs);
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KASSERT(dm_segtabs == endkernel);
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KASSERT(avail[0].size >= NBPG * dm_nsegtabs);
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avail[0].start += NBPG * dm_nsegtabs;
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avail[0].size -= NBPG * dm_nsegtabs;
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endkernel += NBPG * dm_nsegtabs;
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ptp = stp->seg_tab;
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pt_entry_t pt_entry = PTE_M|PTE_xX|PTE_xR;
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pt_entry_t *ptep = (void *)segtabs;
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printf("%s: allocated %lu page table pages for mapping %u pages\n",
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__func__, nsegtabs, physmem);
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for (u_int i = 0; i < nsegtabs; i++, segtabs += NBPG, ptp++) {
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ptep = (void *)dm_segtabs;
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memset(ptep, 0, NBPG * dm_nsegtabs);
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for (size_t i = 0; i < dm_nsegtabs; i++, ptp++, ptep += NPTEPG) {
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*ptp = ptep;
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for (u_int j = 0; j < NPTEPG; j++, ptep++) {
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*ptep = pt_entry;
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pt_entry += NBPG;
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}
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printf(" [%u]=%p (%#x)", i, *ptp, **ptp);
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pt_entry |= PTE_xW;
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pt_entry &= ~PTE_xX;
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}
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/*
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* Now make everything before the kernel inaccessible.
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*/
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for (u_int i = 0; i < startkernel / NBPG; i += NBPG) {
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stp->seg_tab[i >> SEGSHIFT][(i & SEGOFSET) >> PAGE_SHIFT] = 0;
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}
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extern uint32_t _fdata[], _etext[];
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vaddr_t va;
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/* Now make everything before the kernel inaccessible. */
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va = pmap_kvptefill(NBPG, startkernel, 0);
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/* Kernel text is readonly & executable */
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va = pmap_kvptefill(va, round_page((vaddr_t)_etext),
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PTE_M | PTE_xR | PTE_xX);
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/* Kernel .rdata is readonly */
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va = pmap_kvptefill(va, trunc_page((vaddr_t)_fdata), PTE_M | PTE_xR);
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/* Kernel .data/.bss + page tables are read-write */
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va = pmap_kvptefill(va, round_page(endkernel), PTE_M | PTE_xR | PTE_xW);
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/* message buffer page table pages are read-write */
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(void) pmap_kvptefill(msgbuf_paddr, msgbuf_paddr+round_page(MSGBUFSIZE),
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PTE_M | PTE_xR | PTE_xW);
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#endif
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for (size_t i = 0; i < cnt; i++) {
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printf(" uvm_page_physload(%#lx,%#lx,%#lx,%#lx,%d)",
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atop(avail[i].start),
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atop(avail[i].start + avail[i].size) - 1,
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atop(avail[i].start),
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atop(avail[i].start + avail[i].size) - 1,
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VM_FREELIST_DEFAULT);
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uvm_page_physload(
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atop(avail[i].start),
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atop(avail[i].start + avail[i].size) - 1,
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atop(avail[i].start),
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atop(avail[i].start + avail[i].size) - 1,
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VM_FREELIST_DEFAULT);
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}
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pmap_pvlist_lock_init(curcpu()->ci_ci.dcache_line_size);
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/*
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* Initialize the pools.
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*/
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@ -250,6 +300,8 @@ pmap_bootstrap(vaddr_t startkernel, vaddr_t endkernel,
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&pmap_pv_page_allocator, IPL_NONE);
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tlb_set_asid(0);
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return endkernel;
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}
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struct vm_page *
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@ -261,38 +313,69 @@ pmap_md_alloc_poolpage(int flags)
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return uvm_pagealloc(NULL, 0, NULL, flags);
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}
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vaddr_t
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pmap_md_map_poolpage(paddr_t pa, vsize_t size)
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{
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const vaddr_t sva = (vaddr_t) pa;
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#ifdef PMAP_MINIMALTLB
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const vaddr_t eva = sva + size;
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pmap_kvptefill(sva, eva, PTE_M | PTE_xR | PTE_xW);
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#endif
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return sva;
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}
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void
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pmap_md_unmap_poolpage(vaddr_t va, vsize_t size)
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{
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#ifdef PMAP_MINIMALTLB
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struct pmap * const pm = pmap_kernel();
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const vaddr_t eva = va + size;
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pmap_kvptefill(va, eva, 0);
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for (;va < eva; va += NBPG) {
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pmap_tlb_invalidate_addr(pm, va);
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}
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pmap_update(pm);
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#endif
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}
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void
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pmap_zero_page(paddr_t pa)
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{
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dcache_zero_page(pa);
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vaddr_t va = pmap_md_map_poolpage(pa, NBPG);
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dcache_zero_page(va);
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KASSERT(!VM_PAGEMD_EXECPAGE_P(VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(pa))));
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KASSERT(!VM_PAGEMD_EXECPAGE_P(VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(va))));
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pmap_md_unmap_poolpage(va, NBPG);
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}
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void
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pmap_copy_page(paddr_t src, paddr_t dst)
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{
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const size_t line_size = curcpu()->ci_ci.dcache_line_size;
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const paddr_t end = src + PAGE_SIZE;
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vaddr_t src_va = pmap_md_map_poolpage(src, NBPG);
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vaddr_t dst_va = pmap_md_map_poolpage(dst, NBPG);
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const vaddr_t end = src_va + PAGE_SIZE;
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while (src < end) {
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while (src_va < end) {
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__asm(
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"dcbt %2,%1" "\n\t" /* touch next src cachline */
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"dcba 0,%1" "\n\t" /* don't fetch dst cacheline */
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:: "b"(src), "b"(dst), "b"(line_size));
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:: "b"(src_va), "b"(dst_va), "b"(line_size));
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for (u_int i = 0;
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i < line_size;
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src += 32, dst += 32, i += 32) {
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src_va += 32, dst_va += 32, i += 32) {
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__asm(
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"lmw 24,0(%0)" "\n\t"
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"stmw 24,0(%1)"
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:: "b"(src), "b"(dst)
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:: "b"(src_va), "b"(dst_va)
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: "r24", "r25", "r26", "r27",
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"r28", "r29", "r30", "r31");
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}
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}
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pmap_md_unmap_poolpage(src_va, NBPG);
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pmap_md_unmap_poolpage(dst_va, NBPG);
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KASSERT(!VM_PAGEMD_EXECPAGE_P(VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst - PAGE_SIZE))));
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KASSERT(!VM_PAGEMD_EXECPAGE_P(VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst))));
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}
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void
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@ -1,4 +1,4 @@
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/* $NetBSD: e500_tlb.c,v 1.7 2011/06/30 00:52:58 matt Exp $ */
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/* $NetBSD: e500_tlb.c,v 1.8 2012/03/29 15:48:20 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -34,9 +34,11 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define __PMAP_PRIVATE
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.7 2011/06/30 00:52:58 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.8 2012/03/29 15:48:20 matt Exp $");
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#include <sys/param.h>
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@ -45,6 +47,7 @@ __KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.7 2011/06/30 00:52:58 matt Exp $");
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#include <powerpc/spr.h>
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#include <powerpc/booke/spr.h>
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#include <powerpc/booke/cpuvar.h>
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#include <powerpc/booke/e500reg.h>
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#include <powerpc/booke/e500var.h>
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#include <powerpc/booke/pmap.h>
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@ -257,7 +260,7 @@ tlb_to_hwtlb(const struct e500_tlb tlb)
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KASSERT(cntlz <= 19);
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hwtlb.hwtlb_mas0 = MAS0_TLBSEL_TLB1;
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/*
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* TSIZE is defined (4^TSIZE) Kbytes except a TSIZE of is not
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* TSIZE is defined (4^TSIZE) Kbytes except a TSIZE of 0 is not
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* allowed. So 1K would be 0x00000400 giving 21 leading zero
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* bits. Subtracting the leading number of zero bits from 21
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* and dividing by 2 gives us the number that the MMU wants.
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@ -316,7 +319,7 @@ e500_alloc_tlb1_entry(void)
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KASSERT((tlb1->tlb1_entries[slot].e_hwtlb.hwtlb_mas1 & MAS1_V) == 0);
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tlb1->tlb1_entries[slot].e_hwtlb.hwtlb_mas0 =
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MAS0_TLBSEL_TLB1 | __SHIFTOUT(slot, MAS0_ESEL);
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return slot;
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return (int)slot;
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}
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static void
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@ -1018,3 +1021,87 @@ e500_tlb_init(vaddr_t endkernel, psize_t memsize)
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*/
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e500_tlb_invalidate_all();
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}
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void
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e500_tlb_minimize(vaddr_t endkernel)
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{
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#ifdef PMAP_MINIMALTLB
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struct e500_tlb1 * const tlb1 = &e500_tlb1;
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extern uint32_t _fdata[];
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u_int slot;
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paddr_t boot_page = cpu_read_4(GUR_BPTR);
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if (boot_page & BPTR_EN) {
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/*
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* shift it to an address
|
||||
*/
|
||||
boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT;
|
||||
pmap_kvptefill(boot_page, boot_page + NBPG,
|
||||
PTE_M | PTE_xR | PTE_xW | PTE_xX);
|
||||
}
|
||||
|
||||
|
||||
KASSERT(endkernel - (uintptr_t)_fdata < 0x400000);
|
||||
KASSERT((uintptr_t)_fdata == 0x400000);
|
||||
|
||||
struct e500_xtlb *xtlb = e500_tlb_lookup_xtlb(endkernel, &slot);
|
||||
|
||||
KASSERT(xtlb == e500_tlb_lookup_xtlb2(0, endkernel));
|
||||
const u_int tmp_slot = e500_alloc_tlb1_entry();
|
||||
KASSERT(tmp_slot != (u_int) -1);
|
||||
|
||||
struct e500_xtlb * const tmp_xtlb = &tlb1->tlb1_entries[tmp_slot];
|
||||
tmp_xtlb->e_tlb = xtlb->e_tlb;
|
||||
tmp_xtlb->e_hwtlb = tlb_to_hwtlb(tmp_xtlb->e_tlb);
|
||||
tmp_xtlb->e_hwtlb.hwtlb_mas1 |= MAS1_TS;
|
||||
KASSERT((tmp_xtlb->e_hwtlb.hwtlb_mas0 & MAS0_TLBSEL) == MAS0_TLBSEL_TLB1);
|
||||
tmp_xtlb->e_hwtlb.hwtlb_mas0 |= __SHIFTIN(tmp_slot, MAS0_ESEL);
|
||||
hwtlb_write(tmp_xtlb->e_hwtlb, true);
|
||||
|
||||
const u_int text_slot = e500_alloc_tlb1_entry();
|
||||
KASSERT(text_slot != (u_int)-1);
|
||||
struct e500_xtlb * const text_xtlb = &tlb1->tlb1_entries[text_slot];
|
||||
text_xtlb->e_tlb.tlb_va = 0;
|
||||
text_xtlb->e_tlb.tlb_size = 0x400000;
|
||||
text_xtlb->e_tlb.tlb_pte = PTE_M | PTE_xR | PTE_xX | text_xtlb->e_tlb.tlb_va;
|
||||
text_xtlb->e_tlb.tlb_asid = 0;
|
||||
text_xtlb->e_hwtlb = tlb_to_hwtlb(text_xtlb->e_tlb);
|
||||
KASSERT((text_xtlb->e_hwtlb.hwtlb_mas0 & MAS0_TLBSEL) == MAS0_TLBSEL_TLB1);
|
||||
text_xtlb->e_hwtlb.hwtlb_mas0 |= __SHIFTIN(text_slot, MAS0_ESEL);
|
||||
|
||||
const u_int data_slot = e500_alloc_tlb1_entry();
|
||||
KASSERT(data_slot != (u_int)-1);
|
||||
struct e500_xtlb * const data_xtlb = &tlb1->tlb1_entries[data_slot];
|
||||
data_xtlb->e_tlb.tlb_va = 0x400000;
|
||||
data_xtlb->e_tlb.tlb_size = 0x400000;
|
||||
data_xtlb->e_tlb.tlb_pte = PTE_M | PTE_xR | PTE_xW | data_xtlb->e_tlb.tlb_va;
|
||||
data_xtlb->e_tlb.tlb_asid = 0;
|
||||
data_xtlb->e_hwtlb = tlb_to_hwtlb(data_xtlb->e_tlb);
|
||||
KASSERT((data_xtlb->e_hwtlb.hwtlb_mas0 & MAS0_TLBSEL) == MAS0_TLBSEL_TLB1);
|
||||
data_xtlb->e_hwtlb.hwtlb_mas0 |= __SHIFTIN(data_slot, MAS0_ESEL);
|
||||
|
||||
const register_t msr = mfmsr();
|
||||
const register_t ts_msr = (msr | PSL_DS | PSL_IS) & ~PSL_EE;
|
||||
|
||||
__asm __volatile(
|
||||
"mtmsr %[ts_msr]" "\n\t"
|
||||
"sync" "\n\t"
|
||||
"isync"
|
||||
:: [ts_msr] "r" (ts_msr));
|
||||
|
||||
#if 0
|
||||
hwtlb_write(text_xtlb->e_hwtlb, false);
|
||||
hwtlb_write(data_xtlb->e_hwtlb, false);
|
||||
e500_free_tlb1_entry(xtlb, slot, true);
|
||||
#endif
|
||||
|
||||
__asm __volatile(
|
||||
"mtmsr %[msr]" "\n\t"
|
||||
"sync" "\n\t"
|
||||
"isync"
|
||||
:: [msr] "r" (msr));
|
||||
|
||||
e500_free_tlb1_entry(tmp_xtlb, tmp_slot, true);
|
||||
#endif /* PMAP_MINIMALTLB */
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user