it) looks truncated. At least the return(1) is missing, which I now add as
a first stopgap. Somebody needs to find out if anything else is missing for
these boards.
* Add a MIPS-I (r3000) exception handler to the Pica locore.S.
Change the names of the masks used to extract the exception code
to the new MIPS_xxx names.
* Rename the vector code from MachException() to
mips_r4000_exception, in both locore and in the init_main()
code that copies it from locore to the exception vector locations.
* Change the locore and C code to use the new MIPS_SR_INT_IE
name for the Status register master interrupt-enable bit.
Similar changes to the pmax equivalents are in progress.
arch/pica/pica/trap.c, a generic mips trap handler
arch/pica/pica/pica_trap.c, a handler for Pica interrupts.
so that the common pmax and pica trap handling can eventually be
merged and moved to arch/mips/mips/trap.c
* Add cast to hardclock when it's used directly as an interrupt handler.
* Add a null-interrupt-establish function, to avoid int vs void lint
in pica/dev/dma.c.
* fix include in pica/include/pccons.h to work with "standard"
kernel-compile include path.
* add "MIPS_3k_" for the MIPS-I r[23]000-specific register definitions.
* add "MIPS_4k_" for the MIPS-II/III r4000-specific register definitions.
* add #defines that provide the old values for locore and user
code, so the existing code continues to compile.
Regression-tested against the old headers by grepping for #define's,
editing out the defined symbols, and preprocessing with both the previous
machConst.h headers and this version.
Some unused symbols (CPU and FPU must-be-zero constants) are no longer defined.
Pica interrupt masks are now constant expressions instead of constant
values.
TODO:
* factor out the common #defines into src/sys/arch/mips.
* Get rid of the Sprite coding-style names (MACH_xxx).
* Separate out the r3k/r4k differences from the Pica/pmax differences.
* Figure out how to have a run-time choice of r3k vs. r4k support,
instead of a compile-time choice.
bus memory and I/O space access functions/macros, to be used by
machine-independent code for more sane access to bus resources.
New functions will be added to this set, in the future, as appropriate,
but this is a good starting set. Defines:
bus_{io,mem}_{map,unmap}
bus_{io,mem}_{read,write}_{1,2,4,8}
functions, and several types to go with them.
(soon to be documented on mailing lists; eventually in section 9 manual
pages), most importantly:
(1) support interrupt pin swizzling on non-i386 systems with
PCI-PCI bridges (per PPB spec; done, but meaningless, on i386).
(2) provide pci_{io,mem}_find(), to determine what I/O or memory
space is described by a given PCI configuration space
mapping register.
(3) provide pci_intr_map(), pci_intr_string(), and
pci_intr_{,dis}establish() to manipulate and print info about
PCI interrupts.
(4) make pci functions take as an argument a machine-dependent
cookie, to allow more flexibility in implementation.
(1) use pci_{io,mem}_find(), to determine what I/O or memory
space is described by a given PCI configuration space
mapping register, and bus_{io,mem}_map() to map it.
(2) use pci_intr_map(), pci_intr_string(), and
pci_intr_{,dis}establish() to manipulate and print info about
PCI interrupts.
(5) make pci functions take as an argument a machine-dependent
cookie, to allow more flexibility in implementation.
(1) make pci functions take as an argument a machine-dependent
cookie, to allow more flexibility in implementation.
(use of other PCI functions, etc., left unchanged.)
(soon to be documented on mailing lists; eventually in section 9 manual
pages), most importantly:
(1) support interrupt pin swizzling on non-i386 systems with
PCI-PCI bridges (per PPB spec; done, but meaningless, on i386).
(2) provide pci_{io,mem}_find(), to determine what I/O or memory
space is described by a given PCI configuration space
mapping register.
(3) provide pci_intr_map(), pci_intr_string(), and
pci_intr_{,dis}establish() to manipulate and print info about
PCI interrupts.
(4) deprecate the pci_map_* functions, and provide them only
as compatibility interfaces (in pci_compat.c) which will
eventually go away, implemented as wrappers around
the functions described above.
(5) make pci functions take as an argument a machine-dependent
cookie, to allow more flexibility in implementation.
- getcontext() fills the stack_t portion of the context with an 8k size
stack, 0 flags, and below our current stack pointer. I am not sure where
to set the pointer. Thanks pk [2-2] for noticing that.
Now netscape and java work...
to {mainbus,tc,ioasic}_cd.
Change ioasic config name from "lance " to "lance". Correct for
pmaxes, perhaps not for Alphas.
Boots and runs under load on a 5000/200. Hangs during boot on an ioasic
decstation; pmax autoconfig needs fixing.
Add Decstation-3100 baseboard support (untested).
or for which the Pica port is an older revision of the pmax branch.
A merged version with the NetBSD/pmax revision history is in mips/mips/.
cpu_exec.c
elf.c
mem.c
process_machdep.c
* Delete pmax-specific functions and declarations from trap.c
* Delete mips-geeneric functions and declaratinos from pmax_trap.c
* Rename the function pointer used to handle hardware interrupts to
"mips_hardware_intr". Define it in trap.c. Change references elsewhere,
including machdep.c.
Verified to boot on a 5000/200.
* Add spl4() and spl5() functions from the Pica port.
* Add MachFPTrap() as an alternate entry point for MachFPInterrupt.
The r4k reports floating-point execptions as a trap, not an interrupt,
and the Pica port uses the name MachFPTrap().
* Add nops to the Mach_spl?() functions and MachFPInterrupt, as required
for the r4k port.
Commit "floppy" interrupt counter for vmstat -i.
always be eight digits.
Copy the kn02 memory-interrupt reporting function to the kn03 (5k/240)
memory-error handler, since the 3MAXPLUS seems to use the same ECC hardware
as the 3MAX.
to mips/include/asm.h.
Until all references to <machine/machAsmDefs.h> in the pmax and
pica tree are changed to use <mips/asm.h> directly, just do
#include <mips/asm.h>, for compatibility.
Update the include-idempotency preprocessor token to match.
References to machAsmDefs in vendor (sprite, 4.4bsd) headers left unchanged,
for historical accuracy.
* Display as much revision info as we can get.
* Fix a race condition that could cause interrupts to be lost.
* Handle `out of mailbox' conditions (much) more gracefully.
* Schedule timeouts more safely.
* Add diagnostic code to (correctly) detect if a CCB times out before its
outgoing mailbox is emptied.
christos