Split Per Fogelstrom's Pica trap handler into two parts:
arch/pica/pica/trap.c, a generic mips trap handler arch/pica/pica/pica_trap.c, a handler for Pica interrupts. so that the common pmax and pica trap handling can eventually be merged and moved to arch/mips/mips/trap.c
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jonathan
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@ -1,3 +1,5 @@
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/* $NetBSD: trap.c,v 1.2 1996/03/28 12:40:33 jonathan Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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@ -37,8 +39,7 @@
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*
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* from: Utah Hdr: trap.c 1.32 91/04/06
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*
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* from: @(#)trap.c 8.5 (Berkeley) 1/11/94
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* $Id: trap.c,v 1.1.1.1 1996/03/13 04:58:13 jonathan Exp $
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* @(#)trap.c 8.5 (Berkeley) 1/11/94
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*/
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#include <sys/param.h>
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@ -69,22 +70,34 @@
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#include <vm/vm_kern.h>
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#include <vm/vm_page.h>
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#include <pica/pica/pica.h>
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#include <sys/cdefs.h>
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#include <sys/syslog.h>
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struct proc *machFPCurProcPtr; /* pointer to last proc to use FP */
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extern void MachKernGenException();
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extern void MachUserGenException();
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extern void MachKernIntr();
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extern void MachUserIntr();
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extern void MachTLBModException();
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extern void MachTLBInvalidException();
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extern unsigned MachEmulateBranch();
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/*
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* Port-specific hardware interrupt handler
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*/
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void (*machExceptionTable[])() = {
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int (*mips_hardware_intr) __P((u_int mask, u_int pc, u_int status,
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u_int cause)) =
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( int (*) __P((u_int, u_int, u_int, u_int)) ) 0;
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/*
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* Exception-handling functions, called via machExceptionTable from locore
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*/
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extern void MachKernGenException __P((void));
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extern void MachUserGenException __P((void));
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extern void MachKernIntr __P((void));
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extern void MachUserIntr __P((void));
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extern void MachTLBModException __P((void));
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extern void MachTLBInvalidException __P((void));
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extern unsigned MachEmulateBranch __P((unsigned *regsPtr,
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unsigned instPC,
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unsigned fpcCSR,
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int allowNonBranch));
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void (*machExceptionTable[]) __P((void)) = {
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/*
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* The kernel exception handlers.
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*/
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@ -102,7 +115,7 @@ void (*machExceptionTable[])() = {
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MachKernGenException, /* coprocessor unusable */
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MachKernGenException, /* arithmetic overflow */
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MachKernGenException, /* trap exception */
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MachKernGenException, /* viritual coherence exception inst */
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MachKernGenException, /* virtual coherence exception inst */
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MachKernGenException, /* floating point exception */
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MachKernGenException, /* reserved */
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MachKernGenException, /* reserved */
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@ -119,7 +132,7 @@ void (*machExceptionTable[])() = {
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MachKernGenException, /* reserved */
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MachKernGenException, /* reserved */
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MachKernGenException, /* reserved */
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MachKernGenException, /* viritual coherence exception data */
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MachKernGenException, /* virtual coherence exception data */
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/*
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* The user exception handlers.
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*/
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@ -171,9 +184,9 @@ char *trap_type[] = {
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"reserved instruction",
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"coprocessor unusable",
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"arithmetic overflow",
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"trap",
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"viritual coherency instruction",
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"floating point",
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"r4k trap/r3k reserved 13",
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"r4k virtual coherency instruction/r3k reserved 14",
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"r4k floating point/ r3k reserved 15",
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"reserved 16",
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"reserved 17",
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"reserved 18",
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@ -181,7 +194,7 @@ char *trap_type[] = {
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"reserved 20",
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"reserved 21",
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"reserved 22",
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"watch",
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"r4000 watch",
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"reserved 24",
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"reserved 25",
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"reserved 26",
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@ -189,16 +202,9 @@ char *trap_type[] = {
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"reserved 28",
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"reserved 29",
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"reserved 30",
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"viritual coherency data",
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"r4000 virtual coherency data",
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};
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struct {
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int int_mask;
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int (*int_hand)();
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} cpu_int_tab[8];
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int cpu_int_mask; /* External cpu interrupt mask */
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#ifdef DEBUG
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#define TRAPSIZE 10
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struct trapdebug { /* trap history buffer for debugging */
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@ -210,6 +216,8 @@ struct trapdebug { /* trap history buffer for debugging */
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u_int sp;
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u_int code;
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} trapdebug[TRAPSIZE], *trp = trapdebug;
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void trapDump __P((char * msg));
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#endif /* DEBUG */
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#ifdef DEBUG /* stack trace code, also useful for DDB one day */
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@ -219,13 +227,13 @@ extern void logstacktrace();
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/* extern functions printed by name in stack backtraces */
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extern void idle(), cpu_switch(), splx(), MachEmptyWriteBuffer();
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extern void MachTLBMiss();
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extern int main __P((void*));
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#endif /* DEBUG */
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static void pica_errintr();
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extern const struct callback *callv;
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extern volatile struct chiptime *Mach_clock_addr;
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extern u_long intrcnt[];
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/*
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* Handle an exception.
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* Called from MachKernGenException() or MachUserGenException()
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@ -506,7 +514,7 @@ trap(statusReg, causeReg, vadr, pc, args)
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if (code >= numsys)
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callp += p->p_emul->e_nosys; /* (illegal) */
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else
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callp += code;
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callp += code;
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i = callp->sy_argsize / sizeof(int);
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args.i[0] = locr0[A2];
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args.i[1] = locr0[A3];
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@ -593,6 +601,7 @@ trap(statusReg, causeReg, vadr, pc, args)
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trp->vadr = locr0[SP];
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trp->pc = locr0[PC];
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trp->ra = locr0[RA];
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/*trp->sp = (int)&args;*/ /* XXX */
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trp->code = -code;
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if (++trp == &trapdebug[TRAPSIZE])
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trp = trapdebug;
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@ -763,9 +772,9 @@ trap(statusReg, causeReg, vadr, pc, args)
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#endif
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panic("trap");
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}
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p->p_md.md_regs[PC] = pc;
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p->p_md.md_regs[CAUSE] = causeReg;
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p->p_md.md_regs[BADVADDR] = vadr;
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p->p_md.md_regs [PC] = pc;
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p->p_md.md_regs [CAUSE] = causeReg;
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p->p_md.md_regs [BADVADDR] = vadr;
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trapsignal(p, i, ucode);
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out:
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/*
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@ -814,6 +823,7 @@ out:
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* Called from MachKernIntr() or MachUserIntr()
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* Note: curproc might be NULL.
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*/
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void
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interrupt(statusReg, causeReg, pc, what, args)
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unsigned statusReg; /* status register at time of the exception */
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unsigned causeReg; /* cause register at time of exception */
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@ -838,19 +848,7 @@ interrupt(statusReg, causeReg, pc, what, args)
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cnt.v_intr++;
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mask = causeReg & statusReg; /* pending interrupts & enable mask */
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/*
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* Check off all enabled interrupts. Called interrupt routine
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* returns mask of interrupts to reenable.
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*/
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for(i = 0; i < 5; i++) {
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if(cpu_int_tab[i].int_mask & mask) {
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causeReg &= (*cpu_int_tab[i].int_hand)(mask, pc, statusReg, causeReg);
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}
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}
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/*
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* Reenable all non served hardware levels.
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*/
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splx((statusReg & ~causeReg & MACH_HARD_INT_MASK) | MACH_SR_INT_ENAB);
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splx(pica_hardware_intr(mask, pc, statusReg, causeReg));
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if (mask & MACH_SOFT_INT_MASK_0) {
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@ -890,12 +888,13 @@ interrupt(statusReg, causeReg, pc, what, args)
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#endif
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#include "ppp.h"
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#if NPPP > 0
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if(netisr & (1 << NETISR_PPP)) {
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if (netisr & (1 << NETISR_PPP)) {
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netisr &= ~(1 << NETISR_PPP);
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pppintr();
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}
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#endif
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}
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if (mask & MACH_SOFT_INT_MASK_0) {
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clearsoftclock();
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intrcnt[0]++;
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@ -905,31 +904,11 @@ interrupt(statusReg, causeReg, pc, what, args)
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}
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set_intr(mask, int_hand, prio)
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int mask;
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int (*int_hand)();
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int prio;
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{
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if(prio > 4)
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panic("set_intr: to high priority");
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if(cpu_int_tab[prio].int_mask != 0)
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panic("set_intr: int already set");
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cpu_int_tab[prio].int_hand = int_hand;
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cpu_int_tab[prio].int_mask = mask;
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cpu_int_mask |= mask >> 10;
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/*
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* Update external interrupt mask but dont enable clock.
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*/
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out32(PICA_SYS_EXT_IMASK, cpu_int_mask & (~MACH_INT_MASK_4 >> 10));
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}
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/*
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* This is called from MachUserIntr() if astpending is set.
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* This is very similar to the tail of trap().
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*/
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void
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softintr(statusReg, pc)
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unsigned statusReg; /* status register at time of the exception */
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unsigned pc; /* program counter where to continue */
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}
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#ifdef DEBUG
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void
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trapDump(msg)
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char *msg;
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{
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@ -995,41 +975,6 @@ trapDump(msg)
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}
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#endif
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/*
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*----------------------------------------------------------------------
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*
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* MemErrorInterrupts --
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* pica_errintr - for the ACER PICA_61
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*
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* Handler an interrupt for the control register.
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*
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* Results:
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* None.
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*
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* Side effects:
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* None.
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*
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*----------------------------------------------------------------------
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*/
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static void
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pica_errintr()
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{
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#if 0
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volatile u_short *sysCSRPtr =
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(u_short *)MACH_PHYS_TO_UNCACHED(KN01_SYS_CSR);
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u_short csr;
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csr = *sysCSRPtr;
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if (csr & KN01_CSR_MERR) {
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printf("Memory error at 0x%x\n",
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*(unsigned *)MACH_PHYS_TO_UNCACHED(KN01_SYS_ERRADR));
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panic("Mem error interrupt");
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}
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*sysCSRPtr = (csr & ~KN01_CSR_MBZ) | 0xff;
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#endif
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}
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/*
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* Return the resulting PC as if the branch was executed.
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* We do this by storing a break instruction after the current instruction,
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* resuming execution, and then restoring the old instruction.
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*/
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int
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cpu_singlestep(p)
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register struct proc *p;
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{
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@ -1215,6 +1161,7 @@ cpu_singlestep(p)
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return (EFAULT);
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}
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p->p_md.md_ss_addr = va;
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/*
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* Fetch what's at the current location.
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*/
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@ -1242,7 +1189,7 @@ cpu_singlestep(p)
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uio.uio_rw = UIO_WRITE;
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uio.uio_procp = curproc;
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i = procfs_domem(curproc, p, NULL, &uio);
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MachFlushCache();
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MachFlushCache(); /* XXX memory barrier followed by flush icache? */
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if (i < 0)
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return (EFAULT);
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@ -1255,6 +1202,7 @@ cpu_singlestep(p)
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}
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#ifdef DEBUG
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int
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kdbpeek(addr)
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{
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if (addr & 3) {
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@ -1529,6 +1477,9 @@ finish:
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#define Name(_fn) { _fn, "_fn"}
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#endif
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static struct { void *addr; char *name;} names[] = {
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Name(stacktrace),
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Name(stacktrace_subr),
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Name(main),
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Name(interrupt),
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Name(trap),
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Name(MachKernGenException),
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