This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.
Currently this is a no-op on most platforms, so they should see no difference.
Reviewed by Jason.
- pmap_enter()
- pmap_remove()
- pmap_protect()
- pmap_kenter_pa()
- pmap_kremove()
as described in pmap(9).
These calls are relatively conservative. It may be possible to
optimize these a little more.
tweak esp glue to read xfer_len from dma map
add some debugging checks for dma driver invariants
read DD_LIMIT instead of DD_SAVED_LIMIT on scsi dma shutdowns
keep receive ethernet crc and set M_HASFCS
change bus_dma MD fields to keep xfer_len for entire map
instead of per segment
turn off automatic dma restarts in preparation for changing
scsi driver to handle them.
add dma debugging routines to keep history of dma states
tweak checking for unusual dma limit register
<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>
also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.
"off_t" and the return value is a "paddr_t" to allow mappings
at offsets past 2^31 bytes. Somewhat inspired by FreeBSD, which
only changed the offset to a "vm_offset_t".
Includes updates for the i386, pc532 and sh3 mmmmap from Jason Thorpe.
and scsipi_device respectively, with size reduction of ncr53c9x_softc.
Specifying NULL instructs the driver to use default adapter and default
device codes. Every target port has ncr53c9x_attach(sc, NULL, NULL) anyway.
I've fixed the problem that's been keeping me from using anything newer than
1.4.1 now. I tracked down the problem checkin, it's the big reorg of
nextdma.c between 1.19 and 1.20. It didn't introduce a new bug but it
activated a check which wasn't activated before. It's the
is-the-limit-in-the-right-window-check which was ifdeffed before because
some DMA-regs would sometimes have strange values. I think I've fixed the
DMA-reg stuff for now: at the end of nextdma_intr, when the csr is poked
to make DMA do something, I think the check for the ENABLE bit introduces a
race condition. I fixed this by unconditionally setting DMACSR_SETENABLE,
this seems to work and also makes the code more readable. I've also tried
setting DMACSR_SETSUPDATE unconditionally and this also works well, but I
don't know what it implies. Unless you have reasons to not set SUPDATE all
the time, I'd suggest making this change as well, it makes the code cleaner
and faster...
I've tested this patch and it does stop the panics, although I don't think setting
SUPDATE all the tima as he suggests is a good idea. The "SUPDATE" bit implies
a single update (i.e. the end of a dma chain.)
now uses the DMACSR_READ bit and no longer keeps _nd_dmadir in softc
unified transfer cleanup code, now in routine next_dma_finish_xfer()
fixed bounds checking on registers after transfer.
removed checking for bus errors since the bit is always set on some nexts
(specifically, on mourning, a 25mhz 68040 mono slab)
fixed a couple of dma bugs involving chaining dma buffers.
DMACSR_READ is now a CSR status bit which can be used to know if current transfer is
from cpu to device.
the old DMACSR_READ bit is renamed DMACSR_SETREAD. This is a control bit that tells
the dma transfer to be from cpu to device.
jdolecek