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fix logic error in bus_dmamap_sync that was preventing from flush/purging

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full pages instead of only by cache lines
This commit is contained in:
dbj 2000-12-26 07:27:01 +00:00
parent b0a406db08
commit e992baf394
2 changed files with 8 additions and 8 deletions
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8
sys/arch/mvme68k/mvme68k/bus_dma.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_dma.c,v 1.8 2000/08/20 17:07:43 scw Exp $ */
/* $NetBSD: bus_dma.c,v 1.9 2000/12/26 07:27:01 dbj Exp $ */
/*
* This file was taken from from next68k/dev/bus_dma.c, which was originally
@ -46,7 +46,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.8 2000/08/20 17:07:43 scw Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.9 2000/12/26 07:27:01 dbj Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -487,7 +487,7 @@ _bus_dmamap_sync_0460(t, map, offset, len, ops)
}
#endif
while((p<e)&&(!p%NBPG)) {
while((p<e)&&(p%NBPG)) {
DCFL_40(p); /* flush cache line (060 too) */
p += 16;
}
@ -515,7 +515,7 @@ _bus_dmamap_sync_0460(t, map, offset, len, ops)
}
#endif
while((p<e)&&(!p%NBPG)) {
while((p<e)&&(p%NBPG)) {
DCPL_40(p); /* purge cache line */
p += 16;
}

8
sys/arch/next68k/dev/bus_dma.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_dma.c,v 1.16 2000/06/29 07:58:50 mrg Exp $ */
/* $NetBSD: bus_dma.c,v 1.17 2000/12/26 07:27:01 dbj Exp $ */
/*
* This file was taken from from alpha/common/bus_dma.c
@ -46,7 +46,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.16 2000/06/29 07:58:50 mrg Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.17 2000/12/26 07:27:01 dbj Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -460,7 +460,7 @@ _bus_dmamap_sync(t, map, offset, len, ops)
"address=0x%08x, end=0x%08x, ops=0x%x",p,e,ops);
}
#endif
while((p<e)&&(!p%NBPG)) {
while((p<e)&&(p%NBPG)) {
DCFL(p); /* flush cache line */
p += 16;
}
@ -492,7 +492,7 @@ _bus_dmamap_sync(t, map, offset, len, ops)
"address=0x%08x, end=0x%08x, ops=0x%x", p,e,ops);
}
#endif
while((p<e)&&(!p%NBPG)) {
while((p<e)&&(p%NBPG)) {
DCPL(p); /* purge cache line */
p += 16;
}