is still not working.)
cpu.h:
- add a pointer for DDB regs in SMP environment to struct cpu_info
- remove the #defines for mp_pause_cpus() and mp_resume_cpus()
cpuset.h:
- remove CPUSET_ALL() and rename CPUSET_ALL_BUT() to CPUSET_EXCEPT()
from petrov.
db_machdep.h:
- rename the members of db_regs_t to be the same as sparc
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- redo DDB_REGS to no longer be a pointer to a fixed data structure
but to one allocated per-cpu when ddb is entered
- move a bunch of prototypes in here
intr.h:
- remove SPARC64_IPI_* macros, no longer used
db_interface.c:
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- make "nil" a 64 bit entity
- change the ddb register access methods to work in multiprocessor
environment, it is now very much like sparc does it
- in kdb_trap() avoid accessing ddb_regp when it is NULL
- update several messages to include the cpu number
- unpause other cpus much later when resuming from ddb
- rename db_lock() to db_lock_cmd(), as the sparc-like code has
db_lock as a simple lock
- remove "mach cpus" command, and replace it with "mach cpu" (which
does the same) and also implement "mach cpu N" to switch to
another cpus saved trapframe
db_trace.c:
- update for the ddb_regs -> ddb_regp change
genassym.cf:
- add TF_KSTACK as offsetof(struct trapframe64, tf_kstack)
ipifuncs.c:
- overhaul extensively
- remove all normal interrupt handlers as IPI's, we now handle
them all specially in locore.s:interrupt_vector
- add a simplelock around all ipi functions - it's not safe for
multiple cpus to be sending IPI's to each other right now
- rename sparc64_ipi_pause() to sparc64_ipi_pause_thiscpu() and,
if DDB is configured, enable it to save the passed-in trapframe
to a db_regs_t for this cpu's saved DDB registers.
- remove the "ipimask" system (SPARC64_IPI_* macros) and instead
pass functions directly
- in sparc64_send_ipi() always set the interrupt arguments to 0,
the address and argument of the to be called function. (the
argument right now is the address of ipi_tlb_args variable, and
part of the reason why only one CPU can send IPI's at a time.)
don't wait forever for an IPI to complete. some of this is
from petrov.
- rename sparc64_ipi_{halt,pause,resume}_cpus() to
mp_{halt,pause,resume}_cpus()
- new function mp_cpu_is_paused() used to avoid access missing
saved DDB registers
- actually broadcast the flush in smp_tlb_flush_pte(),
smp_tlb_flush_ctx() and smp_tlb_flush_all(). the other end may
not do anything yet in the pte/ctx cases yet...
kgdb_machdep.c:
- rework for changed member names in db_regs_t.
locore.s:
- shave an instruction from syscall_setup() (set + ld -> sethi + ld)
- remove some old dead debug code
- add new sparc64_ipi_halt IPI entry point, it just calls the C
vector to shutdown.
- add new sparc64_ipi_pause IPI entry point, which just traps into
the debugger using the normal breakpoint trap. these cpus usually
lose the race in db_interface.c:db_suspend_others() and end up
calling the C vector sparc64_ipi_pause_thiscpu().
- add #if 0'ed code to sparc64_ipi_flush_{pte,ctx}() IPI entry
points to call the sp_ version of these functions.
- in rft_kernel (return from trap, kernel), check to see if the
%tpc is at the sparc64_ipi_pause_trap_point and if so, call
"done" not "retry"
- rework cpu_switch slightly: save the passed-in lwp instead of
using the one in curlwp
- in cpu_loadproc(), save the new lwp not the old lwp, to curlwp
- in cpu_initialize(), set %tl to zero as well. from petrov.
- in cpu_exit(), fix a load register confusion. from petrov.
- change some "set" in delay branch to "mov".
machdep.c:
- deal with function renames
pmap.c:
- remove a spurious space
trap.c:
- remove unused "trapstats" variable
- add cpu number to a couple of messages
modifies machine/db_machdep.h: BKPT_SET(inst) to BKPT_SET(inst, addr) for all archs ie; passess the
breakpoint address as well.
Patch from cherry@mahiti.org
breakpoint address before it's used. Currently a no-op on all but sh5.
This is useful on sh5, for example, to mask off the instruction
type encoding in the bottom two address bits, and makes it possible
to do "db> break $rXX" instead of manually munging the address.
Fix a bug causing interrmittent panics in interrupt dispatch.
Use interrupt vectors for softints.
Add a new send_softint interface.
Improved D$ flushing.
Improve traptrace and other debugging enhancements.
