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It slices. It dices. It does everything except exec a sparc32_compat init.

This commit is contained in:
eeh 1998-09-05 23:57:24 +00:00
parent 484ce04810
commit a112a2a4cc
37 changed files with 700 additions and 618 deletions
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7
sys/arch/sparc64/Makefile
View File

@ -1,4 +1,4 @@
# $NetBSD: Makefile,v 1.2 1998/08/13 02:10:40 eeh Exp $
# $NetBSD: Makefile,v 1.3 1998/09/05 23:57:24 eeh Exp $
# Makefile for sparc64 tags file and boot blocks
@ -17,6 +17,11 @@ tags:
>> tags
sort -o ${TSPARC64} ${TSPARC64}
TAGS:
@find ../.. -name '*.[chsS]' -print | grep -v CVS >filist
etags `grep sparc64 filist` `grep -v arch filist`
-${RM} fillist
links:
-for i in ${DSPARC64}; do \
cd $$i && rm -f tags; ln -s ../tags tags; done

3
sys/arch/sparc64/dev/bwtwo.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bwtwo.c,v 1.4 1998/09/05 16:50:37 pk Exp $ */
/* $NetBSD: bwtwo.c,v 1.5 1998/09/05 23:57:24 eeh Exp $ */
/*
* Copyright (c) 1996 Jason R. Thorpe. All rights reserved.
@ -72,7 +72,6 @@
#include <machine/eeprom.h>
#include <machine/ctlreg.h>
#include <machine/conf.h>
#include <sparc64/sparc64/asm.h>
#include <sparc64/dev/btreg.h>
#include <sparc64/dev/bwtworeg.h>

295
sys/arch/sparc64/dev/sbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sbus.c,v 1.7 1998/09/05 16:50:38 pk Exp $ */
/* $NetBSD: sbus.c,v 1.8 1998/09/05 23:57:24 eeh Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -83,6 +83,7 @@
/*
* Sbus stuff.
*/
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/malloc.h>
@ -94,11 +95,11 @@
#include <sparc64/sparc64/vaddrs.h>
#include <sparc64/dev/sbusreg.h>
#include <dev/sbus/sbusvar.h>
#include <sparc64/sparc64/asm.h>
#include <machine/autoconf.h>
#include <machine/ctlreg.h>
#include <machine/cpu.h>
#include <machine/sparc64.h>
/* XXXXX -- Needed to allow dvma_mapin to work -- need to switch to bus_dma_* */
struct sbus_softc *sbus0;
@ -149,7 +150,7 @@ extern struct cfdriver sbus_cd;
* DVMA routines
*/
void sbus_enter __P((struct sbus_softc *, vaddr_t, int64_t, int));
void sbus_remove __P((struct sbus_softc *, vaddr_t, int));
void sbus_remove __P((struct sbus_softc *, vaddr_t, size_t));
int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int));
void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t));
@ -209,11 +210,14 @@ sbus_print(args, busname)
if (busname)
printf("%s at %s", sa->sa_name, busname);
printf(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset);
printf(" slot %ld offset 0x%lx", (long)sa->sa_slot,
(u_long)sa->sa_offset);
for (i=0; i<sa->sa_nintr; i++) {
struct sbus_intr *sbi = &sa->sa_intr[i];
printf(" vector %x ipl %d", (int)sbi->sbi_vec, (int)INTLEV(sbi->sbi_pri));
printf(" vector %lx ipl %ld",
(u_long)sbi->sbi_vec,
(long)INTLEV(sbi->sbi_pri));
}
return (UNCONF);
}
@ -251,7 +255,7 @@ sbus_attach(parent, self, aux)
sc->sc_bustag = ma->ma_bustag;
sc->sc_dmatag = ma->ma_dmatag;
sc->sc_sysio = (struct sysioreg*)(long)ma->ma_address[0]; /* Use prom mapping for sysio. */
sc->sc_sysio = (struct sysioreg*)(u_long)ma->ma_address[0]; /* Use prom mapping for sysio. */
sc->sc_ign = ma->ma_interrupts[0] & INTMAP_IGN; /* Find interrupt group no */
/* Setup interrupt translation tables */
@ -324,10 +328,12 @@ sbus_attach(parent, self, aux)
sc->sc_tsb = iotsb;
sc->sc_ptsb = iotsbp;
}
#if 0
#if 1
/* Need to do 64-bit stores */
sc->sc_sysio->sys_iommu.iommu_cr = (IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN);
sc->sc_sysio->sys_iommu.iommu_tsb = sc->sc_ptsb;
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_iommu.iommu_cr,
0, (IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN));
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_iommu.iommu_tsb,
0, sc->sc_ptsb);
#else
stxa(&sc->sc_sysio->sys_iommu.iommu_cr,ASI_NUCLEUS,(IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN));
stxa(&sc->sc_sysio->sys_iommu.iommu_tsb,ASI_NUCLEUS,sc->sc_ptsb);
@ -338,11 +344,11 @@ sbus_attach(parent, self, aux)
/* Probe the iommu */
int64_t cr, tsb;
printf("iommu regs at: cr=%x tsb=%x flush=%x\n", &sc->sc_sysio->sys_iommu.iommu_cr,
printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", &sc->sc_sysio->sys_iommu.iommu_cr,
&sc->sc_sysio->sys_iommu.iommu_tsb, &sc->sc_sysio->sys_iommu.iommu_flush);
cr = sc->sc_sysio->sys_iommu.iommu_cr;
tsb = sc->sc_sysio->sys_iommu.iommu_tsb;
printf("iommu cr=%x:%x tsb=%x:%x\n", (long)(cr>>32), (long)cr, (long)(tsb>>32), (long)tsb);
printf("iommu cr=%lx tsb=%lx\n", (long)cr, (long)tsb);
printf("sysio base %p phys %p TSB base %p phys %p",
(long)sc->sc_sysio, (long)pmap_extract(pmap_kernel(), (vaddr_t)sc->sc_sysio),
(long)sc->sc_tsb, (long)sc->sc_ptsb);
@ -354,8 +360,9 @@ sbus_attach(parent, self, aux)
* Initialize streaming buffer.
*/
sc->sc_flushpa = pmap_extract(pmap_kernel(), (vaddr_t)&sc->sc_flush);
#if 0
sc->sc_sysio->sys_strbuf.strbuf_ctl = STRBUF_EN; /* Enable diagnostics mode? */
#if 1
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_strbuf.strbuf_ctl,
0, STRBUF_EN); /* Enable diagnostics mode? */
#else
stxa(&sc->sc_sysio->sys_strbuf.strbuf_ctl,ASI_NUCLEUS,STRBUF_EN);
#endif
@ -449,7 +456,7 @@ sbus_destroy_attach_args(sa)
free(sa->sa_intr, M_DEVBUF);
if (sa->sa_promvaddrs)
free(sa->sa_promvaddrs, M_DEVBUF);
free((void *)sa->sa_promvaddrs, M_DEVBUF);
bzero(sa, sizeof(struct sbus_attach_args));/*DEBUG*/
}
@ -480,8 +487,8 @@ _sbus_bus_map(t, btype, offset, size, flags, vaddr, hp)
paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32);
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("\n_sbus_bus_map: mapping paddr slot %x offset %x:%x poffset %x paddr %x:%x\n",
(int)slot, (int)(offset>>32), (int)offset, (int)sc->sc_range[i].poffset, (int)(paddr>>32), (int)paddr);
printf("\n_sbus_bus_map: mapping paddr slot %lx offset %lx poffset %lx paddr %lx\n",
(long)slot, (long)offset, (long)sc->sc_range[i].poffset, (long)paddr);
#endif
return (bus_space_map2(sc->sc_bustag, 0, paddr,
size, flags, vaddr, hp));
@ -573,11 +580,14 @@ sbusreset(sbus)
printf(" %s", dev->dv_xname);
}
}
#if 0
#if 1
/* Reload iommu regs */
sc->sc_sysio->sys_iommu.iommu_cr = (IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN);
sc->sc_sysio->sys_iommu.iommu_tsb = sc->sc_ptsb;
sc->sc_sysio->sys_strbuf.strbuf_ctl = STRBUF_EN; /* Enable diagnostics mode? */
bus_space_write_8(sc->ma_bustag, &sc->sc_sysio->sys_iommu.iommu_cr,
0, (IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN));
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_iommu.iommu_tsb,
0, sc->sc_ptsb);
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_strbuf.strbuf_ctl,
0, STRBUF_EN); /* Enable diagnostics mode? */
#else
/* Reload iommu regs */
stxa(&sc->sc_sysio->sys_iommu.iommu_cr,ASI_NUCLEUS,(IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN));
@ -600,31 +610,33 @@ sbus_enter(sc, va, pa, flags)
#ifdef DIAGNOSTIC
if (va < sc->sc_dvmabase)
panic("sbus_enter: va 0x%x not in DVMA space",va);
panic("sbus_enter: va 0x%lx not in DVMA space",va);
#endif
tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE),
!(flags&BUS_DMA_COHERENT));
/* Is the streamcache flush really needed? */
#if 0
sc->sc_sysio->sys_strbuf.strbuf_pgflush = va;
#if 1
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_strbuf.strbuf_pgflush,
0, va);
#else
stxa(&(sc->sc_sysio->sys_strbuf.strbuf_pgflush), ASI_NUCLEUS, va);
#endif
sbus_flush(sc);
sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)] = tte;
#if 0
sc->sc_sysio->sys_iommu.iommu_flush = va;
#if 1
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_iommu.iommu_flush,
0, va);
#else
stxa(&sc->sc_sysio->sys_iommu.iommu_flush,ASI_NUCLEUS,va);
#endif
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_enter: va %x pa %x:%x TSB[%x]@%p=%x:%x\n",
va, (int)(pa>>32), (int)pa, IOTSBSLOT(va,sc->sc_tsbsize),
printf("sbus_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n",
va, (long)pa, IOTSBSLOT(va,sc->sc_tsbsize),
&sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)],
(int)(tte>>32), (int)tte);
(long)tte);
#endif
}
@ -637,15 +649,17 @@ void
sbus_remove(sc, va, len)
struct sbus_softc *sc;
vaddr_t va;
int len;
size_t len;
{
#ifdef DIAGNOSTIC
if (va < sc->sc_dvmabase)
panic("sbus_remove: va 0x%x not in DVMA space", (int)va);
if ((int)(va + len) < (int)va)
panic("sbus_remove: va 0x%x + len 0x%x wraps",
(int) va, (int) len);
panic("sbus_remove: va 0x%lx not in DVMA space", (long)va);
if ((long)(va + len) < (long)va)
panic("sbus_remove: va 0x%lx + len 0x%lx wraps",
(long) va, (long) len);
if (len & ~0xfffffff)
panic("sbus_remove: rediculous len 0x%lx", (long)len);
#endif
va = trunc_page(va);
@ -662,29 +676,37 @@ sbus_remove(sc, va, len)
*
* If it takes more than .5 sec, something went wrong.
*/
#if 0
sc->sc_sysio->sys_strbuf.strbuf_pgflush = va;
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n",
(long)va, (long)IOTSBSLOT(va,sc->sc_tsbsize),
(long)&sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)],
(long)(sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)]),
(u_long)len);
#endif
#if 1
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_strbuf.strbuf_pgflush, 0, va);
#else
stxa(&(sc->sc_sysio->sys_strbuf.strbuf_pgflush), ASI_NUCLEUS, va);
#endif
if (len <= NBPG) {
sbus_flush(sc);
}
len = 0;
} else len -= NBPG;
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_remove: flushed va %p TSB[%x]@%p=%lx:%lx\n",
(long)va, (int)IOTSBSLOT(va,sc->sc_tsbsize),
printf("sbus_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n",
(long)va, (long)IOTSBSLOT(va,sc->sc_tsbsize),
(long)&sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)],
(long)((sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)])>>32),
(long)(sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)]));
(long)(sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)]),
(u_long)len);
#endif
sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)] = 0;
#if 0
sc->sc_sysio->sys_iommu.iommu_flush = va;
#if 1
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_iommu.iommu_flush, 0, va);
#else
stxa(&sc->sc_sysio->sys_iommu.iommu_flush, ASI_NUCLEUS, va);
#endif
len -= NBPG;
va += NBPG;
}
}
@ -697,33 +719,38 @@ sbus_flush(sc)
u_int64_t flushtimeout;
sc->sc_flush = 0;
/*
* KLUGE ALERT KLUGE ALERT
*
* In order not to bother with pmap_extract() to do the vtop
* translation, flushdone is a static variable that resides in
* the kernel's 4MB locked TTE. This means that this routine
* is NOT re-entrant. Since we're single-threaded and poll
* on this value, this is currently not a problem.
*/
#ifdef NOTDEF_DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_remove: flush = %x at va = %x pa = %x:%x\n",
(int)sc->sc_flush, (int)&sc->sc_flush,
(int)(sc->sc_flushpa>>32), (int)sc->sc_flushpa);
#endif
#if 0
sc->sc_sysio->sys_strbuf.strbuf_flushsync = sc->sc_flushpa;
membar_sync();
#if 1
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_strbuf.strbuf_flushsync, 0, sc->sc_flushpa);
#else
stxa(&sc->sc_sysio->sys_strbuf.strbuf_flushsync, ASI_NUCLEUS, sc->sc_flushpa);
#endif
membar_sync();
flushtimeout = tick() + cpu_clockrate/2; /* .5 sec after *now* */
while( !sc->sc_flush && flushtimeout > tick()) membar_sync();
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_flush: flush = %lx at va = %lx pa = %lx now=%lx until = %lx\n",
(long)sc->sc_flush, (long)&sc->sc_flush,
(long)sc->sc_flushpa, (long)tick(), flushtimeout);
#endif
/* Bypass non-coherent D$ */
#if 0
while( !ldxa(sc->sc_flushpa, ASI_PHYS_CACHED) && flushtimeout > tick()) membar_sync();
#else
{ int i; for(i=140000000/2; !ldxa(sc->sc_flushpa, ASI_PHYS_CACHED) && i; i--) membar_sync(); }
#endif
#ifdef DIAGNOSTIC
if( !sc->sc_flush )
printf("sbus_remove: flush timeout %p at %p\n", (long)sc->sc_flush,
if( !sc->sc_flush ) {
printf("sbus_flush: flush timeout %p at %p\n", (long)sc->sc_flush,
(long)sc->sc_flushpa); /* panic? */
#ifdef DDB
Debugger();
#endif
}
#endif
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_flush: flushed\n");
#endif
return (sc->sc_flush);
}
@ -824,6 +851,7 @@ sbus_intr_establish(t, level, flags, handler, arg)
struct sbus_softc *sc = t->cookie;
struct intrhand *ih;
int ipl;
long vec = level;
ih = (struct intrhand *)
malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT);
@ -831,55 +859,54 @@ sbus_intr_establish(t, level, flags, handler, arg)
return (NULL);
if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0)
ipl = level;
else if ((level & SBUS_INTR_COMPAT) != 0)
ipl = level & ~SBUS_INTR_COMPAT;
ipl = vec;
else if ((vec & SBUS_INTR_COMPAT) != 0)
ipl = vec & ~SBUS_INTR_COMPAT;
else {
/* Decode and remove IPL */
ipl = INTLEV(level);
level = INTVEC(level);
ipl = INTLEV(vec);
vec = INTVEC(vec);
#ifdef DEBUG
if (sbusdebug & SDB_INTR) {
printf("\nsbus: intr[%d]%x: %x\n", ipl, level,
intrlev[level]);
printf("\nsbus: intr[%ld]%lx: %lx\n", (long)ipl, (long)vec,
intrlev[vec]);
printf("Hunting for IRQ...\n");
}
#endif
if ((level & INTMAP_OBIO) == 0) {
if ((vec & INTMAP_OBIO) == 0) {
/* We're in an SBUS slot */
/* Register the map and clear intr registers */
#ifdef DEBUG
if (sbusdebug & SDB_INTR) {
int64_t *intrptr = &(&sc->sc_sysio->sbus_slot0_int)[INTSLOT(level)];
int64_t *intrptr = &(&sc->sc_sysio->sbus_slot0_int)[INTSLOT(vec)];
int64_t intrmap = *intrptr;
printf("Found SBUS %x IRQ as %x:%x in slot %d\n",
level, (int)(intrmap>>32), (int)intrmap,
INTSLOT(level));
printf("Found SBUS %lx IRQ as %llx in slot %ld\n",
(long)vec, (long)intrmap,
(long)INTSLOT(vec));
}
#endif
ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[INTSLOT(level)];
ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[INTVEC(level)];
ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[INTSLOT(vec)];
ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[INTVEC(vec)];
/* Enable the interrupt */
level |= INTMAP_V;
stxa(ih->ih_map, ASI_NUCLEUS, level);
vec |= INTMAP_V;
bus_space_write_8(sc->sc_bustag, ih->ih_map, 0, vec);
} else {
int64_t *intrptr = &sc->sc_sysio->scsi_int_map;
int64_t intrmap = 0;
int i;
/* Insert IGN */
level |= sc->sc_ign;
vec |= sc->sc_ign;
for (i=0;
&intrptr[i] <= (int64_t *)&sc->sc_sysio->reserved_int_map &&
INTVEC(intrmap=intrptr[i]) != INTVEC(level);
INTVEC(intrmap=intrptr[i]) != INTVEC(vec);
i++);
if (INTVEC(intrmap) == INTVEC(level)) {
if (INTVEC(intrmap) == INTVEC(vec)) {
#ifdef DEBUG
if (sbusdebug & SDB_INTR)
printf("Found OBIO %x IRQ as %x:%x in slot %d\n",
level, (int)(intrmap>>32), (int)intrmap,
i);
printf("Found OBIO %lx IRQ as %lx in slot %d\n",
vec, (long)intrmap, i);
#endif
/* Register the map and clear intr registers */
ih->ih_map = &intrptr[i];
@ -887,17 +914,17 @@ sbus_intr_establish(t, level, flags, handler, arg)
ih->ih_clr = &intrptr[i];
/* Enable the interrupt */
intrmap |= INTMAP_V;
stxa(ih->ih_map, ASI_NUCLEUS, intrmap);
bus_space_write_8(sc->sc_bustag, ih->ih_map, 0, (u_long)intrmap);
} else panic("IRQ not found!");
}
}
#ifdef DEBUG
if (sbusdebug & SDB_INTR) { int i; for (i=0; i<140000000; i++); }
if (sbusdebug & SDB_INTR) { long i; for (i=0; i<1400000000; i++); }
#endif
ih->ih_fun = handler;
ih->ih_arg = arg;
ih->ih_number = level;
ih->ih_number = vec;
ih->ih_pil = (1<<ipl);
if ((flags & BUS_INTR_ESTABLISH_FASTTRAP) != 0)
intr_fasttrap(ipl, (void (*)__P((void)))handler);
@ -1012,8 +1039,8 @@ sbus_dmamap_load(t, map, buf, buflen, p, flags)
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_dmamap_load: map %p loading va %x at pa %x\n",
map, (int)dvmaddr, (int)(curaddr & ~(NBPG-1)));
printf("sbus_dmamap_load: map %p loading va %lx at pa %lx\n",
map, (long)dvmaddr, (long)(curaddr & ~(NBPG-1)));
#endif
sbus_enter(sc, trunc_page(dvmaddr), trunc_page(curaddr), flags);
@ -1041,8 +1068,8 @@ sbus_dmamap_unload(t, map)
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_dmamap_unload: map %p removing va %x size %x\n",
map, (int)addr, (int)len);
printf("sbus_dmamap_unload: map %p removing va %lx size %lx\n",
map, (long)addr, (long)len);
#endif
sbus_remove(sc, addr, len);
bus_dmamap_unload(t->_parent, map);
@ -1060,18 +1087,29 @@ sbus_dmamap_sync(t, map, offset, len, ops)
struct sbus_softc *sc = (struct sbus_softc *)t->_cookie;
vaddr_t va = map->dm_segs[0].ds_addr + offset;
/*
* We only support one DMA segment; supporting more makes this code
* too unweildy.
*/
if (ops&BUS_DMASYNC_PREREAD)
if (ops&BUS_DMASYNC_PREREAD) {
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_dmamap_sync: syncing va %p len %lu BUS_DMASYNC_PREREAD\n",
(long)va, (u_long)len);
#endif
/* Nothing to do */;
}
if (ops&BUS_DMASYNC_POSTREAD) {
/*
* We should sync the IOMMU streaming caches here first.
*/
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_dmamap_sync: syncing va %p len %lu BUS_DMASYNC_POSTREAD\n",
(long)va, (u_long)len);
#endif
while (len > 0) {
/*
@ -1085,25 +1123,47 @@ sbus_dmamap_sync(t, map, offset, len, ops)
*
* If it takes more than .5 sec, something went wrong.
*/
#if 0
sc->sc_sysio->sys_strbuf.strbuf_pgflush = va;
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_dmamap_sync: flushing va %p, %lu bytes left\n",
(long)va, (u_long)len);
#endif
#if 1
bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_strbuf.strbuf_pgflush, 0, va);
#else
stxa(&(sc->sc_sysio->sys_strbuf.strbuf_pgflush), ASI_NUCLEUS, va);
#endif
if (len <= NBPG) {
sbus_flush(sc);
}
len -= NBPG;
len = 0;
} else
len -= NBPG;
va += NBPG;
}
}
if (ops&BUS_DMASYNC_PREWRITE)
if (ops&BUS_DMASYNC_PREWRITE) {
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_dmamap_sync: syncing va %p len %lu BUS_DMASYNC_PREWRITE\n",
(long)va, (u_long)len);
#endif
/* Nothing to do */;
if (ops&BUS_DMASYNC_POSTWRITE)
/* Nothing to do */;
}
if (ops&BUS_DMASYNC_POSTWRITE) {
#ifdef DEBUG
if (sbusdebug & SDB_DVMA)
printf("sbus_dmamap_sync: syncing va %p len %lu BUS_DMASYNC_POSTWRITE\n",
(long)va, (u_long)len);
#endif
/* Nothing to do */;
}
bus_dmamap_sync(t->_parent, map, offset, len, ops);
}
/*
* Take memory allocated by our parent bus and generate DVMA mappings for it.
*/
int
sbus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags)
bus_dma_tag_t t;
@ -1125,8 +1185,17 @@ sbus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags)
boundary, segs, nsegs, rsegs, flags)))
return (error);
/*
* Allocate a DVMA mapping for our new memory.
*/
for (n=0; n<*rsegs; n++) {
dvmaddr = segs[n].ds_addr;
dvmaddr = dvmamap_alloc(segs[0].ds_len, flags);
if (dvmaddr == (bus_addr_t)-1) {
/* Free what we got and exit */
bus_dmamem_free(t->_parent, segs, nsegs);
return (ENOMEM);
}
segs[n].ds_addr = dvmaddr;
size = segs[n].ds_len;
mlist = segs[n]._ds_mlist;
@ -1156,12 +1225,13 @@ sbus_dmamem_free(t, segs, nsegs)
addr = segs[n].ds_addr;
len = segs[n].ds_len;
sbus_remove(sc, addr, len);
dvmamap_free(addr, len);
}
bus_dmamem_free(t->_parent, segs, nsegs);
}
/*
* Call bus_dmamem_map() to map it into the kernel, then map it into the IOTSB.
* Map the DVMA mappings into the kernel pmap.
* Check the flags to see whether we're streaming or coherent.
*/
int
@ -1179,13 +1249,6 @@ sbus_dmamem_map(t, segs, nsegs, size, kvap, flags)
struct pglist *mlist;
struct sbus_softc *sc = (struct sbus_softc *)t->_cookie;
int cbit;
int rval;
/*
* First have the parent driver allocate some address space in DVMA space.
*/
if ((rval = bus_dmamem_map(t->_parent, segs, nsegs, size, kvap, flags)))
return (rval);
/*
* digest flags:
@ -1196,9 +1259,10 @@ sbus_dmamem_map(t, segs, nsegs, size, kvap, flags)
if (flags & BUS_DMA_NOCACHE) /* sideffects */
cbit |= PMAP_NC;
/*
* Now take this and map it both into the CPU and into the IOMMU.
* Now take this and map it into the CPU since it should already
* be in the the IOMMU.
*/
va = (vaddr_t)*kvap;
*kvap = (caddr_t)va = segs[0].ds_addr;
mlist = segs[0]._ds_mlist;
for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) {
@ -1208,7 +1272,6 @@ sbus_dmamem_map(t, segs, nsegs, size, kvap, flags)
addr = VM_PAGE_TO_PHYS(m);
pmap_enter(pmap_kernel(), va, addr | cbit,
VM_PROT_READ | VM_PROT_WRITE, TRUE);
sbus_enter(sc, va, addr, flags);
va += PAGE_SIZE;
size -= PAGE_SIZE;
}
@ -1217,8 +1280,7 @@ sbus_dmamem_map(t, segs, nsegs, size, kvap, flags)
}
/*
* Common function for unmapping DMA-safe memory. May be called by
* bus-specific DMA memory unmapping functions.
* Unmap DVMA mappings from kernel
*/
void
sbus_dmamem_unmap(t, kva, size)
@ -1234,6 +1296,5 @@ sbus_dmamem_unmap(t, kva, size)
#endif
size = round_page(size);
sbus_remove(sc, (vaddr_t)kva, size);
bus_dmamem_unmap(t->_parent, kva, size);
pmap_remove(pmap_kernel(), (vaddr_t)kva, size);
}

6
sys/arch/sparc64/dev/sbusreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: sbusreg.h,v 1.2 1998/08/13 02:10:42 eeh Exp $ */
/* $NetBSD: sbusreg.h,v 1.3 1998/09/05 23:57:25 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@ -254,10 +254,10 @@ struct sysioreg {
#define MAKEIOTTE(pa,w,c,s) (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K))
#if 0
/* This version generates a pointer to a int64_t */
#define IOTSBSLOT(va,sz) ((((((vaddr_t)(va))-(0xff800000<<(sz))))>>(13-3))&(~7))
#define IOTSBSLOT(va,sz) ((((((vaddr_t)(va))-(((vaddr_t)0xff800000)<<(sz))))>>(13-3))&(~7))
#else
/* Here we just try to create an array index */
#define IOTSBSLOT(va,sz) ((((((vaddr_t)(va))-(0xff800000<<(sz))))>>(13)))
#define IOTSBSLOT(va,sz) ((u_int)((((((vaddr_t)(va))-(((vaddr_t)0xff800000)<<(sz))))>>(13))))
#endif
/*

11
sys/arch/sparc64/dev/sbusvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: sbusvar.h,v 1.4 1998/09/05 16:44:39 pk Exp $ */
/* $NetBSD: sbusvar.h,v 1.5 1998/09/05 23:57:25 eeh Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -108,15 +108,16 @@ struct sbus_softc {
int *sc_intr_compat; /* `intr' property to sbus compat */
struct sysioreg* sc_sysio; /* SBUS control registers */
u_int sc_pagesize;
u_int sc_dvmabase;
paddr_t sc_ptsb; /* TSB physaddr */
int64_t *sc_tsb; /* TSB vaddr */
int sc_tsbsize;
paddr_t sc_ptsb; /* TSB physaddr */
u_int sc_pagesize;
u_int sc_dvmabase;
int sc_hasiocache;
int sc_ign; /* Interrupt group number for this sysio */
int32_t sc_flushpa; /* used to flush the SBUS */
paddr_t sc_flushpa; /* used to flush the SBUS */
volatile /* Needs to be volatile or egcs optimizes away loads */
int64_t sc_flush;
};

3
sys/arch/sparc64/dev/upa.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: upa.c,v 1.3 1998/09/05 16:23:09 pk Exp $ */
/* $NetBSD: upa.c,v 1.4 1998/09/05 23:57:25 eeh Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -94,7 +94,6 @@
#include <machine/bus.h>
#include <sparc64/dev/upavar.h>
#include <sparc64/sparc64/asm.h>
#include <machine/autoconf.h>
#include <machine/ctlreg.h>

38
sys/arch/sparc64/dev/zs.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.4 1998/09/02 05:51:37 eeh Exp $ */
/* $NetBSD: zs.c,v 1.5 1998/09/05 23:57:25 eeh Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -109,7 +109,7 @@ int zs_major = 12;
# error "no suitable software interrupt bit"
#endif
#define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2))
#define ZS_DELAY() (0)
/* The layout of this is hardware-dependent (padding, order). */
struct zschan {
@ -256,6 +256,9 @@ zs_match_obio(parent, cf, aux)
struct cfdata *cf;
void *aux;
{
#ifdef SUN4U
return 0;
#else
union obio_attach_args *uoba = aux;
struct obio4_attach_args *oba;
@ -271,6 +274,7 @@ zs_match_obio(parent, cf, aux)
oba = &uoba->uoba_oba4;
return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr,
1, 0, 0, NULL, NULL));
#endif
}
static void
@ -279,6 +283,9 @@ zs_attach_mainbus(parent, self, aux)
struct device *self;
void *aux;
{
#ifdef SUN4U
return 0;
#else
struct zsc_softc *zsc = (void *) self;
struct mainbus_attach_args *ma = aux;
int zs_unit = zsc->zsc_dev.dv_unit;
@ -289,9 +296,10 @@ zs_attach_mainbus(parent, self, aux)
/* Use the mapping setup by the Sun PROM. */
if (zsaddr[zs_unit] == NULL)
zsaddr[zs_unit] = findzs(zs_unit);
if ((void*)zsaddr[zs_unit] != (void*)(long)ma->ma_address[0])
if ((void*)zsaddr[zs_unit] != (void*)(u_long)ma->ma_address[0])
panic("zsattach_mainbus");
zs_attach(zsc, ma->ma_pri);
#endif
}
@ -320,6 +328,7 @@ zs_attach_obio(parent, self, aux)
struct device *self;
void *aux;
{
#ifndef SUN4U
struct zsc_softc *zsc = (void *) self;
union obio_attach_args *uoba = aux;
int zs_unit = zsc->zsc_dev.dv_unit;
@ -339,6 +348,7 @@ zs_attach_obio(parent, self, aux)
zsc->zsc_dmatag = oba->oba_dmatag;
zs_attach(zsc, oba->oba_pri);
}
#endif
}
/*
* Attach a found zs.
@ -815,7 +825,7 @@ zs_putc(arg, c)
static void zscninit __P((struct consdev *));
static int zscngetc __P((dev_t));
static void zscnputc __P((dev_t, int));
static void zscnpollc __P((dev_t, int));
/*
* Console table shared by ttya, ttyb
*/
@ -824,7 +834,7 @@ struct consdev consdev_tty = {
zscninit,
zscngetc,
zscnputc,
nullcnpollc,
zscnpollc,
};
static void
@ -854,6 +864,24 @@ zscnputc(dev, c)
zs_putc(zs_conschan, c);
}
int swallow_zsintrs;
static void
zscnpollc(dev, on)
dev_t dev;
int on;
{
/*
* Need to tell zs driver to acknowledge all interrupts or we get
* annoying spurious interrupt messages. This is because mucking
* with spl() levels during polling does not prevent interrupts from
* being generated.
*/
if (on) swallow_zsintrs++;
else swallow_zsintrs--;
}
/*****************************************************************/
static void prom_cninit __P((struct consdev *));

36
sys/arch/sparc64/include/autoconf.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.h,v 1.4 1998/09/05 16:23:09 pk Exp $ */
/* $NetBSD: autoconf.h,v 1.5 1998/09/05 23:57:25 eeh Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@ -86,7 +86,7 @@
#include <machine/bus.h>
#include <sparc64/dev/upavar.h>
#include <sparc64/dev/sbusvar.h>
#include <dev/sbus/sbusvar.h>
/* This is used to map device classes to IPLs */
struct intrmap {
@ -113,8 +113,8 @@ struct mainbus_attach_args {
bus_dma_tag_t ma_dmatag;
char *ma_name; /* PROM node name */
struct upa_reg *ma_reg; /* "reg" properties */
int *ma_address; /* "address" properties -- 32 bits */
int *ma_interrupts; /* "interrupts" properties */
u_int *ma_address; /* "address" properties -- 32 bits */
u_int *ma_interrupts; /* "interrupts" properties */
struct bootpath *ma_bp; /* used for locating boot device */
int ma_node; /* PROM handle */
int ma_nreg; /* Counts for those properties */
@ -123,34 +123,6 @@ struct mainbus_attach_args {
int ma_pri; /* priority (IPL) */
};
/* Attach arguments presented to devices by obio_attach() (sun4 only) */
struct obio4_attach_args {
int oba_placeholder;/* obio/sbus attach args sharing */
bus_space_tag_t oba_bustag; /* parent bus tag */
bus_dma_tag_t oba_dmatag;
bus_addr_t oba_paddr; /* register physical address */
int oba_pri; /* interrupt priority (IPL) */
struct bootpath *oba_bp; /* used for locating boot device */
};
union obio_attach_args {
/* sun4m obio space is treated like an sbus slot */
int uoba_isobio4;
struct sbus_attach_args uoba_sbus; /* Sbus view */
struct obio4_attach_args uoba_oba4; /* sun4 on-board view */
};
#define obio_bus_map(t, a, o, s, f, v, hp) \
bus_space_map2(t, 0, (long)(a) + o, s, f, (vaddr_t)v, hp)
/* obio specific bus flag */
#define OBIO_BUS_MAP_USE_ROM BUS_SPACE_MAP_BUS1
/* obio bus helper that finds ROM mappings; exported for autoconf.c */
int obio_find_rom_map __P((bus_addr_t, int,
bus_space_handle_t *));
/*
* length; the others convert or make some other guarantee.
*/

42
sys/arch/sparc64/include/bus.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus.h,v 1.5 1998/09/02 05:51:37 eeh Exp $ */
/* $NetBSD: bus.h,v 1.6 1998/09/05 23:57:25 eeh Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -351,7 +351,7 @@ int bus_space_probe __P((
* Read a 1, 2, 4, or 8 byte quantity from bus space
* described by tag/handle/offset.
*/
#if 0
#define bus_space_read_1(t, h, o) \
lduba((h) + (o), (t)->type)
@ -363,7 +363,20 @@ int bus_space_probe __P((
#define bus_space_read_8(t, h, o) \
ldxa((h) + (o), (t)->type)
#else
/* For the time being don't use address spaces */
#define bus_space_read_1(t, h, o) \
(*(volatile u_int8_t *)((h) + (o)))
#define bus_space_read_2(t, h, o) \
(*(volatile u_int16_t *)((h) + (o)))
#define bus_space_read_4(t, h, o) \
(*(volatile u_int32_t *)((h) + (o)))
#define bus_space_read_8(t, h, o) \
(*(volatile u_int64_t *)((h) + (o)))
#endif
/*
* void bus_space_read_multi_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
@ -409,7 +422,7 @@ int bus_space_probe __P((
* Write the 1, 2, 4, or 8 byte value `value' to bus space
* described by tag/handle/offset.
*/
#if 0
#define bus_space_write_1(t, h, o, v) \
((void)(stba((h) + (o), (t)->type, (v))))
@ -421,7 +434,24 @@ int bus_space_probe __P((
#define bus_space_write_8(t, h, o, v) \
((void)(stxa((h) + (o), (t)->type, (v))))
#else
/* Use primary ASI for now for debug */
#define bus_space_write_1(t, h, o, v) do { \
((void)(*(volatile u_int8_t *)((h) + (o)) = (v))); \
} while (0)
#define bus_space_write_2(t, h, o, v) do { \
((void)(*(volatile u_int16_t *)((h) + (o)) = (v))); \
} while (0)
#define bus_space_write_4(t, h, o, v) do { \
((void)(*(volatile u_int32_t *)((h) + (o)) = (v))); \
} while (0)
#define bus_space_write_8(t, h, o, v) do { \
((void)(*(volatile u_int64_t *)((h) + (o)) = (v))); \
} while (0)
#endif
/*
* void bus_space_write_multi_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
@ -700,4 +730,10 @@ int _bus_dmamem_alloc_range __P((bus_dma_tag_t tag, bus_size_t size,
vaddr_t low, vaddr_t high));
#endif /* _SPARC_BUS_DMA_PRIVATE */
/*
* DVMA alloc/free until each bus gets its own map in 64-bit land.
*/
bus_addr_t dvmamap_alloc __P((int, int));
void dvmamap_free __P((bus_addr_t, bus_size_t));
#endif /* _SPARC_BUS_H_ */

4
sys/arch/sparc64/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
/* $NetBSD: cpu.h,v 1.2 1998/09/05 23:57:25 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@ -237,8 +237,6 @@ void zs_kgdb_init __P((void));
#endif
/* fb.c */
void fb_unblank __P((void));
/* cache.c */
int cache_flush __P((caddr_t, u_int));
/* kgdb_stub.c */
#ifdef KGDB
void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *));

42
sys/arch/sparc64/include/ctlreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ctlreg.h,v 1.2 1998/09/02 05:51:37 eeh Exp $ */
/* $NetBSD: ctlreg.h,v 1.3 1998/09/05 23:57:26 eeh Exp $ */
/*
* Copyright (c) 1996
@ -272,7 +272,39 @@
#define SFSR_FV 0x00001 /* Fault is valid */
#define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV)
#if 0
/* Old bits */
#define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV"
#else
/* New bits */
#define SFSR_BITS "\177\20" \
"f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \
"b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0"
#endif
/* ASFR bits */
#define ASFR_ME 0x100000000LL
#define ASFR_PRIV 0x080000000LL
#define ASFR_ISAP 0x040000000LL
#define ASFR_ETP 0x020000000LL
#define ASFR_IVUE 0x010000000LL
#define ASFR_TO 0x008000000LL
#define ASFR_BERR 0x004000000LL
#define ASFR_LDP 0x002000000LL
#define ASFR_CP 0x001000000LL
#define ASFR_WP 0x000800000LL
#define ASFR_EDP 0x000400000LL
#define ASFR_UE 0x000200000LL
#define ASFR_CE 0x000100000LL
#define ASFR_ETS 0x0000f0000LL
#define ASFT_P_SYND 0x00000ffffLL
#define AFSR_BITS "\177\20" \
"b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \
"b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \
"b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \
"b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0"
/*
* Here's the spitfire TSB control register bits.
*
@ -528,16 +560,16 @@
#ifdef _LP64
/* read 64-bit %tick register */
#define tick() ({ \
register long _tick_tmp; \
register u_long _tick_tmp; \
__asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \
_tick_tmp; \
})
#else
/* native load 64-bit int from alternate address space w/32-bit compiler*/
#define tick() ({ \
volatile register long _tick_tmp = 0; \
volatile int64_t _tick_v; \
volatile int64_t *_tick_a = &_tick_v; \
volatile register u_long _tick_tmp = 0; \
volatile u_int64_t _tick_v; \
volatile u_int64_t *_tick_a = &_tick_v; \
__asm __volatile("rdpr %%tick, %0; stx %0,[%1]; membar #StoreLoad" : "=r" (_tick_tmp) : \
"r" ((long)(_tick_a))); \
_tick_v; \

4
sys/arch/sparc64/include/db_machdep.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_machdep.h,v 1.4 1998/09/02 05:51:37 eeh Exp $ */
/* $NetBSD: db_machdep.h,v 1.5 1998/09/05 23:57:26 eeh Exp $ */
/*
* Mach Operating System
@ -87,7 +87,7 @@ db_regs_t ddb_regs; /* register state */
#define PC_REGS(regs) ((db_addr_t)(regs)->ddb_tf.tf_pc)
#endif
#define PC_ADVANCE(regs) do { \
int n = (regs)->ddb_tf.tf_npc; \
vaddr_t n = (regs)->ddb_tf.tf_npc; \
(regs)->ddb_tf.tf_pc = n; \
(regs)->ddb_tf.tf_npc = n + 4; \
} while(0)

4
sys/arch/sparc64/include/idprom.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: idprom.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
/* $NetBSD: idprom.h,v 1.2 1998/09/05 23:57:26 eeh Exp $ */
/*
* Copyright (c) 1993 Adam Glass
@ -42,7 +42,7 @@ struct idprom {
u_char id_format; /* format identifier (= 1) */
u_char id_machine; /* machine type (see param.h) */
u_char id_ether[6]; /* ethernet address */
long id_date; /* date of manufacture */
int id_date; /* date of manufacture */
u_char id_hostid[3]; /* ``host id'' bytes */
u_char id_checksum; /* xor of everything else */
char id_undef[16]; /* undefined */

10
sys/arch/sparc64/include/psl.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: psl.h,v 1.4 1998/08/30 15:32:17 eeh Exp $ */
/* $NetBSD: psl.h,v 1.5 1998/09/05 23:57:26 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@ -96,10 +96,10 @@
*
*/
#define ICC_C 0x01
#define ICC_V 0x02
#define ICC_Z 0x04
#define ICC_N 0x08
#define ICC_C 0x01L
#define ICC_V 0x02L
#define ICC_Z 0x04L
#define ICC_N 0x08L
#define XCC_SHIFT 4
#define XCC_C (ICC_C<<XCC_SHIFT)
#define XCC_V (ICC_V<<XCC_SHIFT)

10
sys/arch/sparc64/include/pte.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pte.h,v 1.2 1998/08/13 02:10:45 eeh Exp $ */
/* $NetBSD: pte.h,v 1.3 1998/09/05 23:57:26 eeh Exp $ */
/*
* Copyright (c) 1996
@ -208,6 +208,14 @@ extern void tlb_flush_ctx __P((int ctx));
#define TTE_W 0x0000000000000002
#define TTE_G 0x0000000000000001
#define TTE_DATA_BITS "\177\20" \
"b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \
"=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \
"b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \
"f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \
"b\6L\0" "b\5CP\0" "b\4CV\0" \
"b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0"
#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid) \
(((valid)?TLB_V:0LL)|(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\
((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\

17
sys/arch/sparc64/sparc64/autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.c,v 1.7 1998/09/05 17:43:18 pk Exp $ */
/* $NetBSD: autoconf.c,v 1.8 1998/09/05 23:57:26 eeh Exp $ */
/*
* Copyright (c) 1996
@ -78,7 +78,6 @@
#include <machine/cpu.h>
#include <machine/ctlreg.h>
#include <machine/pmap.h>
#include <sparc64/sparc64/asm.h>
#include <sparc64/sparc64/timerreg.h>
#ifdef DDB
@ -452,6 +451,11 @@ configure()
OF_set_callback(sync_crash);
#endif
/* block clock interrupts and anything below */
splclock();
/* Enable device interrupts */
setpstate(getpstate()|PSTATE_IE);
if (config_rootfound("mainbus", NULL) == NULL)
panic("mainbus not configured");
@ -517,7 +521,7 @@ mbprint(aux, name)
if (name)
printf("%s at %s", ma->ma_name, name);
if (ma->ma_address)
printf(" addr 0x%x", (int)ma->ma_address[0]);
printf(" addr 0x%08lx", (u_long)ma->ma_address[0]);
if (ma->ma_pri)
printf(" ipl %d", ma->ma_pri);
return (UNCONF);
@ -864,7 +868,7 @@ findzs(zs)
int zs;
{
int node, n;
unsigned long addr;
unsigned int addr;
node = firstchild(findroot());
/* Ultras have zs on the sbus */
@ -877,8 +881,9 @@ findzs(zs)
/* There is no way to identify a node by its number */
if ( n++ == zs ) {
if ((addr = getpropint(node, "address", 0)) == 0)
/* We really should just map it in ourselves */
panic("findzs: zs%d not mapped by PROM", zs);
return ((void *)addr);
return ((void *)(unsigned long)addr);
}
node = nextsibling(node);
}
@ -962,7 +967,6 @@ getprop(node, name, size, nitem, bufp)
long len;
len = getproplen(node, name);
if (len <= 0 || ((len % size) != 0)) printf("getprop(%s): len = %lx size = %lx\n", name, len, size);
if (len <= 0)
return (ENOENT);
@ -973,7 +977,6 @@ if (len <= 0 || ((len % size) != 0)) printf("getprop(%s): len = %lx size = %lx\n
if (buf == NULL) {
/* No storage provided, so we allocate some */
buf = malloc(len, M_DEVBUF, M_NOWAIT);
if (!buf) printf("getprop(%s): malloc of %lx failed\n", name, len);
if (buf == NULL)
return (ENOMEM);
}

20
sys/arch/sparc64/sparc64/cache.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cache.c,v 1.1.1.1 1998/06/20 04:58:52 eeh Exp $ */
/* $NetBSD: cache.c,v 1.2 1998/09/05 23:57:26 eeh Exp $ */
/*
* Copyright (c) 1996
@ -64,7 +64,6 @@
#include <machine/ctlreg.h>
#include <machine/pte.h>
#include <sparc64/sparc64/asm.h>
#include <sparc64/sparc64/cache.h>
enum vactype vactype;
@ -93,7 +92,7 @@ cache_enable()
*/
int
cache_flush_page(va)
u_int va;
vaddr_t va;
{
register int i, j, ls;
register char *p;
@ -138,11 +137,12 @@ cache_flush_page(va)
int
cache_flush(base, len)
caddr_t base;
register u_int len;
size_t len;
{
register int i, j, ls, baseoff;
register char *p;
register int *kp;
int i, j, ls;
vaddr_t baseoff;
char *p;
int *kp;
#ifdef DEBUG
if (cachedebug)
@ -152,18 +152,18 @@ cache_flush(base, len)
/* Don't flush if not enabled or not probed. */
if (!cacheinfo.c_enabled) return 0;
baseoff = (int)base & PGOFSET;
baseoff = (vaddr_t)base & PGOFSET;
i = (baseoff + len + PGOFSET) >> PGSHIFT;
cachestats.cs_nraflush++;
i = min(i,CACHE_FLUSH_MAGIC);
p = (char *)((int)base & ~baseoff);
p = (char *)((vaddr_t)base & ~baseoff);
ls = cacheinfo.dc_linesize;
i >>= cacheinfo.dc_l2linesize;
/* Pick right physical color for E$ */
kp = (int *)(((int)p & (cacheinfo.ec_totalsize - 1)) + KERNBASE);
kp = (int *)(((vaddr_t)p & (cacheinfo.ec_totalsize - 1)) + KERNBASE);
j = 0; /* defeat optimizer? */
for (; --i >= 0; p += ls) {
flush(p); /* Take care of I$. */

8
sys/arch/sparc64/sparc64/cache.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cache.h,v 1.1.1.1 1998/06/20 04:58:52 eeh Exp $ */
/* $NetBSD: cache.h,v 1.2 1998/09/05 23:57:26 eeh Exp $ */
/*
* Copyright (c) 1996
@ -135,11 +135,11 @@ extern enum vactype vactype; /* XXX move into cacheinfo struct */
* Routines for dealing with the cache.
*/
void cache_enable __P((void)); /* turn it on */
int cache_flush_page __P((u_int va)); /* flush page from E$ */
int cache_flush __P((caddr_t, u_int)); /* flush region */
int cache_flush_page __P((vaddr_t va)); /* flush page from E$ */
int cache_flush __P((caddr_t, size_t)); /* flush region */
/* The following two are for I$ and D$ flushes and are in locore.s */
void dcache_flush_page __P((u_int va)); /* flush page from D$ */
void dcache_flush_page __P((vaddr_t va)); /* flush page from D$ */
void blast_vcache __P((void)); /* Clear entire contents of I$ and D$ */
/*

65
sys/arch/sparc64/sparc64/clock.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: clock.c,v 1.6 1998/09/05 16:52:02 pk Exp $ */
/* $NetBSD: clock.c,v 1.7 1998/09/05 23:57:27 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@ -87,7 +87,6 @@
#include <sparc64/sparc64/timerreg.h>
#include <sparc64/dev/sbusreg.h>
#include <dev/sbus/sbusvar.h>
#include <sparc64/sparc64/asm.h>
#include "kbd.h"
/*
@ -244,7 +243,7 @@ clockattach(parent, self, aux)
h |= idp->id_hostid[1] << 8;
h |= idp->id_hostid[2];
hostid = h;
printf(" hostid %x\n", hostid);
printf(" hostid %lx\n", (long)hostid);
clockreg = cl;
}
@ -270,7 +269,7 @@ timerattach(parent, self, aux)
struct mainbus_attach_args *ma = aux;
bus_space_handle_t bh;
struct upa_reg *ur = NULL;
int *va = NULL;
u_int *va = NULL;
int nreg;
volatile int64_t *cnt = NULL, *lim = NULL;
/* XXX: must init to NULL to avoid stupid gcc -Wall warning */
@ -297,9 +296,9 @@ timerattach(parent, self, aux)
/* Get address property */
if (getprop(ma->ma_node, "address", sizeof(*va),
&nreg, (void **)&va) == 0) {
timerreg_4u.t_timer = (struct timer_4u *)(long)va[0];
timerreg_4u.t_clrintr = (int64_t *)(long)va[1];
timerreg_4u.t_mapintr = (int64_t *)(long)va[2];
timerreg_4u.t_timer = (struct timer_4u *)(u_long)va[0];
timerreg_4u.t_clrintr = (int64_t *)(u_long)va[1];
timerreg_4u.t_mapintr = (int64_t *)(u_long)va[2];
} else {
/* Map the system timer -- Not an SBUS device */
if (bus_space_map2(ma->ma_bustag, 0,
@ -324,10 +323,14 @@ timerattach(parent, self, aux)
/* Install the appropriate interrupt vector here */
level10.ih_number = ma->ma_interrupts[0];
level10.ih_clr = timerreg_4u.t_clrintr[0];
intr_establish(10, &level10);
level14.ih_number = ma->ma_interrupts[1];
level14.ih_clr = timerreg_4u.t_clrintr[1];
intr_establish(14, &level14);
printf(" irq vectors %x and %x\n", (int)level10.ih_number, (int)level14.ih_number);
printf(" irq vectors %lx and %lx\n",
(u_long)level10.ih_number,
(u_long)level14.ih_number);
timerok = 1;
@ -438,22 +441,29 @@ void
cpu_initclocks()
{
register int statint, minint;
#ifdef DEBUG
extern int intrdebug;
#endif
if (1000000 % hz) {
printf("cannot get %d Hz clock; using 100 Hz\n", hz);
hz = 100;
tick = 1000000 / hz;
}
#ifdef INTR_DEBUG
/* Set a 1/4s clock */
tick = 200000;
#endif
if (stathz == 0)
stathz = hz;
if (1000000 % stathz) {
printf("cannot get %d Hz statclock; using 100 Hz\n", stathz);
stathz = 100;
}
#ifdef DEBUG
/* Set a 1s clock */
if (intrdebug) {
hz = 1;
tick = 1000000;
}
#endif
profhz = stathz; /* always */
statint = 1000000 / stathz;
@ -476,14 +486,13 @@ cpu_initclocks()
timerreg_4u.t_mapintr[1] |= INTMAP_V;
#else
stxa(&timerreg_4u.t_timer[0].t_limit, ASI_NUCLEUS, tmr_ustolim(tick)|TMR_LIM_IEN|TMR_LIM_PERIODIC|TMR_LIM_RELOAD);
/* stxa(&timerreg_4u.t_timer[0].t_limit, ASI_NUCLEUS, tmr_ustolim(tick)|TMR_LIM_PERIODIC|TMR_LIM_RELOAD); */
stxa(&timerreg_4u.t_mapintr[0], ASI_NUCLEUS, timerreg_4u.t_mapintr[0]|INTMAP_V);
#ifdef INTR_DEBUG
/* Neglect to enable profile timer */
stxa(&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, tmr_ustolim(statint)|TMR_LIM_RELOAD);
#else
stxa(&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, tmr_ustolim(statint)|TMR_LIM_IEN|TMR_LIM_RELOAD);
#endif
if (intrdebug)
/* Neglect to enable timer */
stxa(&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, tmr_ustolim(statint)|TMR_LIM_RELOAD);
else
stxa(&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, tmr_ustolim(statint)|TMR_LIM_IEN|TMR_LIM_RELOAD);
stxa(&timerreg_4u.t_mapintr[1], ASI_NUCLEUS, timerreg_4u.t_mapintr[1]|INTMAP_V);
#endif
statmin = statint - (statvar >> 1);
@ -518,6 +527,8 @@ clockintr(cap)
extern int rom_console_input;
#endif
#if 0
/* Let locore.s clear the interrupt for us. */
/*
* Protect the clearing of the clock interrupt. If we don't
* do this, and we're interrupted (by the zs, for example),
@ -531,17 +542,9 @@ clockintr(cap)
timerreg_4u.t_clrintr[0] = 0;
#else
stxa(&timerreg_4u.t_clrintr[0], ASI_NUCLEUS, 0LL);
#endif
#if 0
/* reset timer interrupt?!?!?! */
#if 0
timerreg_4u.t_timer[0].t_limit = tmr_ustolim(tick)|TMR_LIM_IEN|TMR_LIM_PERIODIC;
#else
stxa(&timerreg_4u.t_timer[0].t_limit, ASI_NUCLEUS, tmr_ustolim(tick)|TMR_LIM_IEN|TMR_LIM_PERIODIC);
#endif
#endif
splx(s);
#endif
hardclock((struct clockframe *)cap);
#if NKBD > 0
@ -561,7 +564,6 @@ statintr(cap)
{
register u_long newint, r, var;
/* read the limit register to clear the interrupt */
#ifdef NOT_DEBUG
printf("statclock: count %x:%x, limit %x:%x\n",
timerreg_4u.t_timer[1].t_count, timerreg_4u.t_timer[1].t_limit);
@ -569,13 +571,16 @@ statintr(cap)
#ifdef NOT_DEBUG
prom_printf("!");
#endif
#if 0
/* Let locore.s clear the interrupt for us. */
/* read the limit register to clear the interrupt */
#if 0
timerreg_4u.t_clrintr[1]=0;
#else
stxa(&timerreg_4u.t_clrintr[1], ASI_NUCLEUS, 0LL);
#endif
#endif
statclock((struct clockframe *)cap);
#ifdef NOTDEF_DEBUG
/* Don't re-schedule the IRQ */
return 1;

3
sys/arch/sparc64/sparc64/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.2 1998/09/02 05:51:38 eeh Exp $ */
/* $NetBSD: cpu.c,v 1.3 1998/09/05 23:57:27 eeh Exp $ */
/*
* Copyright (c) 1996
@ -65,7 +65,6 @@
#include <machine/pmap.h>
#include <sparc64/sparc64/cache.h>
#include <sparc64/sparc64/asm.h>
/* This is declared here so that you must include a CPU for the cache code. */
struct cacheinfo cacheinfo;

30
sys/arch/sparc64/sparc64/db_disasm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_disasm.c,v 1.2 1998/08/13 02:10:46 eeh Exp $ */
/* $NetBSD: db_disasm.c,v 1.3 1998/09/05 23:57:27 eeh Exp $ */
/*
* Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu
@ -100,7 +100,7 @@
#define COND2(x) (((x) & 0xf) << 14)
struct sparc_insn {
unsigned long int match;
unsigned int match;
char* name;
char* format;
};
@ -801,7 +801,7 @@ db_disasm(loc, altfmt)
{
struct sparc_insn* i_ptr = (struct sparc_insn *)&sparc_i;
unsigned long int insn, you_lose, bitmask;
unsigned int insn, you_lose, bitmask;
int matchp;
char* f_ptr, *cp;
@ -891,19 +891,19 @@ db_disasm(loc, altfmt)
db_printf("%%%s", regs[((insn >> 25) & 0x1f)]);
break;
case '3':
db_printf("%%f%ld", ((insn >> 14) & 0x1f));
db_printf("%%f%d", ((insn >> 14) & 0x1f));
break;
case '4':
db_printf("%%f%ld", (insn & 0x1f));
db_printf("%%f%d", (insn & 0x1f));
break;
case 'e':
db_printf("%%f%ld", ((insn >> 25) & 0x1f));
db_printf("%%f%d", ((insn >> 25) & 0x1f));
break;
case 'i':
db_printf("0x%lx", (insn & 0x1fff));
db_printf("0x%x", (insn & 0x1fff));
break;
case 'j':
db_printf("0x%lx", (insn & 0x7ff));
db_printf("0x%x", (insn & 0x7ff));
break;
case 'l':
db_printsym(
@ -930,7 +930,7 @@ db_disasm(loc, altfmt)
db_printf("%%asi");
break;
case 't':
db_printf("0x%-2.2lx", ((insn >> 5) & 0xff));
db_printf("0x%-2.2x", ((insn >> 5) & 0xff));
break;
case 'o':
db_printf("%%fcc%ld", ((insn >> 25) & 0x3));
@ -945,7 +945,7 @@ db_disasm(loc, altfmt)
break;
case 'q':
case '8':
db_printf("[%%%s %c 0x%lx]",
db_printf("[%%%s %c 0x%x]",
regs[((insn >> 14) & 0x1f)],
(int)((insn & 0x1000)?'-':'+'),
(insn & 0x1000)?((insn+1) & 0xfff):(insn & 0xfff));
@ -959,7 +959,7 @@ db_disasm(loc, altfmt)
db_printf("%%fsr");
break;
case '9':
db_printf("0x%lxl",
db_printf("0x%xl",
((insn & 0xf) | ((insn >> 4) & 0x7)));
break;
case '0':
@ -975,16 +975,16 @@ db_disasm(loc, altfmt)
db_printf("%%%s", state_regs[((insn >> 14) & 0x1f)]);
break;
case 'C':
db_printf("%%hi(0x%lx)", ((insn & 0x3fffff) << 10));
db_printf("%%hi(0x%x)", ((insn & 0x3fffff) << 10));
break;
case 'D':
db_printf("0x%lx", (insn & 0x1f));
db_printf("0x%x", (insn & 0x1f));
break;
case 'E':
db_printf("0x%lx", (insn & 0x3f));
db_printf("0x%x", (insn & 0x3f));
break;
case 'F':
db_printf("0x%lx", (insn & 0x3f));
db_printf("0x%x", (insn & 0x3f));
break;
case 'G':
db_printf("%%%s", priv_regs[((insn >> 25) & 0x1f)]);

43
sys/arch/sparc64/sparc64/db_interface.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_interface.c,v 1.6 1998/09/02 05:51:38 eeh Exp $ */
/* $NetBSD: db_interface.c,v 1.7 1998/09/05 23:57:27 eeh Exp $ */
/*
* Mach Operating System
@ -53,7 +53,6 @@
#include <machine/openfirm.h>
#include <machine/ctlreg.h>
#include <machine/pmap.h>
#include <sparc64/sparc64/asm.h>
extern void OF_enter __P((void));
@ -193,6 +192,8 @@ kdb_trap(type, tf)
/* We should do a proper copyin and xlate 64-bit stack frames, but... */
/* if (tf->tf_tstate & TSTATE_PRIV) { */
#if 0
/* make sure this is not causing ddb problems. */
if (tf->tf_out[6] & 1) {
if ((unsigned)(tf->tf_out[6] + BIAS) > (unsigned)KERNBASE)
ddb_regs.ddb_fr = *(struct frame64 *)(tf->tf_out[6] + BIAS);
@ -214,6 +215,7 @@ kdb_trap(type, tf)
ddb_regs.ddb_fr.fr_fp = (long)tfr.fr_fp;
ddb_regs.ddb_fr.fr_pc = tfr.fr_pc;
}
#endif
db_active++;
cnpollc(TRUE);
@ -221,8 +223,8 @@ kdb_trap(type, tf)
s = splhigh();
tl = savetstate(ts);
for (i=0; i<tl; i++) {
printf("%d tt=%x tstate=%lx tpc=%p tnpc=%p\n",
i+1, (int)ts[i].tt, (u_long)ts[i].tstate,
printf("%d tt=%lx tstate=%lx tpc=%p tnpc=%p\n",
i+1, (long)ts[i].tt, (u_long)ts[i].tstate,
(void*)ts[i].tpc, (void*)ts[i].tnpc);
}
db_trap(type, 0/*code*/);
@ -315,10 +317,10 @@ db_dump_dtlb(addr, have_addr, count, modif)
if (have_addr) {
int i;
int* p = (int*)addr;
long* p = (long*)addr;
for (i=0; i<64;) {
db_printf("%2d:%08x:%08x %08x:%08x ", i++, *p++, *p++, *p++, *p++);
db_printf("%2d:%08x:%08x %08x:%08x\n", i++, *p++, *p++, *p++, *p++);
db_printf("%2d:%016.16lx %016.16lx ", i++, *p++, *p++);
db_printf("%2d:%016.16lx %016.16lx\n", i++, *p++, *p++);
}
} else
print_dtlb();
@ -341,8 +343,8 @@ db_pload_cmd(addr, have_addr, count, modif)
db_printf("no address\n");
return;
}
db_printf("%08.8lx%08.8lx:\t%08.8lx\n", (long)(oldaddr>>32),
(long)oldaddr, (long)lda(oldaddr, ASI_PHYS_CACHED));
db_printf("%016.16lx:\t%08.8lx\n", (long)oldaddr,
(long)lda(oldaddr, ASI_PHYS_CACHED));
}
int64_t pseg_get __P((struct pmap *, vaddr_t));
@ -359,24 +361,22 @@ struct pmap* pm;
n = 0;
for (i=0; i<STSZ; i++) {
if((pdir = (paddr_t *)ldxa(&pm->pm_segs[i], ASI_PHYS_CACHED))) {
db_printf("pdir %d at %x:\n", i, (long)pdir);
db_printf("pdir %ld at %xl:\n", i, (long)pdir);
for (k=0; k<PDSZ; k++) {
if ((ptbl = (paddr_t *)ldxa(&pdir[k], ASI_PHYS_CACHED))) {
db_printf("ptable %d:%d at %x:\n", i, k, (long)ptbl);
db_printf("ptable %ld:%ld at %xl:\n", i, k, (long)ptbl);
for (j=0; j<PTSZ; j++) {
int64_t data0, data1;
data0 = ldxa(&ptbl[j], ASI_PHYS_CACHED);
j++;
data1 = ldxa(&ptbl[j], ASI_PHYS_CACHED);
if (data0 || data1) {
db_printf("%p: %x:%x\t",
db_printf("%p: %lx\t",
(i<<STSHIFT)|(k<<PDSHIFT)|((j-1)<<PTSHIFT),
(int)(data0>>32),
(int)(data0));
db_printf("%p: %x:%x\n",
(u_long)(data0));
db_printf("%p: %lx\n",
(i<<STSHIFT)|(k<<PDSHIFT)|(j<<PTSHIFT),
(int)(data1>>32),
(int)(data1));
(u_long)(data1));
}
}
}
@ -406,11 +406,10 @@ db_pmap_kernel(addr, have_addr, count, modif)
/* lookup an entry for this VA */
if ((data = pseg_get(&kernel_pmap_, (vaddr_t)addr))) {
db_printf("pmap_kernel(%p)->pm_segs[%x][%x][%x]=>%x:%x\n",
(void *)addr, (int)va_to_seg(addr),
(int)va_to_dir(addr), (int)va_to_pte(addr),
(int)(data>>32),
(int)(data));
db_printf("pmap_kernel(%p)->pm_segs[%lx][%lx][%lx]=>%lx\n",
(void *)addr, (u_long)va_to_seg(addr),
(u_long)va_to_dir(addr), (u_long)va_to_pte(addr),
(u_long)data);
} else {
db_printf("No mapping for %p\n", addr);
}

90
sys/arch/sparc64/sparc64/db_trace.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_trace.c,v 1.3 1998/08/30 15:32:18 eeh Exp $ */
/* $NetBSD: db_trace.c,v 1.4 1998/09/05 23:57:27 eeh Exp $ */
/*
* Mach Operating System
@ -165,13 +165,13 @@ u_int64_t frame;
db_printf("frame64 %x locals, ins:\n", f);
if (INKERNEL(f)) {
db_printf("%x:%x %x:%x %x:%x %x:%x\n",
db_printf("%llx %llx %llx %llx ",
f->fr_local[0], f->fr_local[1], f->fr_local[2], f->fr_local[3]);
db_printf("%x:%x %x:%x %x:%x %x:%x\n",
db_printf("%llx %llx %llx %llx\n",
f->fr_local[4], f->fr_local[5], f->fr_local[6], f->fr_local[7]);
db_printf("%x:%x %x:%x %x:%x %x:%x\n",
db_printf("%llx %llx %llx %llx ",
f->fr_arg[0], f->fr_arg[1], f->fr_arg[2], f->fr_arg[3]);
db_printf("%x:%x %x:%x %x:%xsp %x:%xpc=",
db_printf("%llx %llx %llxsp %llxpc=",
f->fr_arg[0], f->fr_arg[1], f->fr_fp, f->fr_pc);
db_printsym(f->fr_pc, DB_STGY_PROC);
db_printf("\n");
@ -292,59 +292,39 @@ db_dump_trap(addr, have_addr, count, modif)
db_printf("y: %x\tpil: %d\toldpil: %d\tfault: %p\tkstack: %p\ttt: %x\tGlobals:\n",
(int)tf->tf_y, (int)tf->tf_pil, (int)tf->tf_oldpil, (long)tf->tf_fault,
(long)tf->tf_kstack, (int)tf->tf_tt);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\n",
(long)(tf->tf_global[0]>>32), (long)tf->tf_global[0],
(long)(tf->tf_global[1]>>32), (long)tf->tf_global[1],
(long)(tf->tf_global[2]>>32), (long)tf->tf_global[2],
(long)(tf->tf_global[3]>>32), (long)tf->tf_global[3]);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\nouts:\n",
(long)(tf->tf_global[4]>>32), (long)tf->tf_global[4],
(long)(tf->tf_global[5]>>32), (long)tf->tf_global[5],
(long)(tf->tf_global[6]>>32), (long)tf->tf_global[6],
(long)(tf->tf_global[7]>>32), (long)tf->tf_global[7]);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\n",
(long)(tf->tf_out[0]>>32), (long)tf->tf_out[0],
(long)(tf->tf_out[1]>>32), (long)tf->tf_out[1],
(long)(tf->tf_out[2]>>32), (long)tf->tf_out[2],
(long)(tf->tf_out[3]>>32), (long)tf->tf_out[3]);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\nlocals:\n",
(long)(tf->tf_out[4]>>32), (long)tf->tf_out[4],
(long)(tf->tf_out[5]>>32), (long)tf->tf_out[5],
(long)(tf->tf_out[6]>>32), (long)tf->tf_out[6],
(long)(tf->tf_out[7]>>32), (long)tf->tf_out[7]);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\n",
(long)(tf->tf_local[0]>>32), (long)tf->tf_local[0],
(long)(tf->tf_local[1]>>32), (long)tf->tf_local[1],
(long)(tf->tf_local[2]>>32), (long)tf->tf_local[2],
(long)(tf->tf_local[3]>>32), (long)tf->tf_local[3]);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\nins:\n",
(long)(tf->tf_local[4]>>32), (long)tf->tf_local[4],
(long)(tf->tf_local[5]>>32), (long)tf->tf_local[5],
(long)(tf->tf_local[6]>>32), (long)tf->tf_local[6],
(long)(tf->tf_local[7]>>32), (long)tf->tf_local[7]);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\n",
(long)(tf->tf_in[0]>>32), (long)tf->tf_in[0],
(long)(tf->tf_in[1]>>32), (long)tf->tf_in[1],
(long)(tf->tf_in[2]>>32), (long)tf->tf_in[2],
(long)(tf->tf_in[3]>>32), (long)tf->tf_in[3]);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\n",
(long)(tf->tf_in[4]>>32), (long)tf->tf_in[4],
(long)(tf->tf_in[5]>>32), (long)tf->tf_in[5],
(long)(tf->tf_in[6]>>32), (long)tf->tf_in[6],
(long)(tf->tf_in[7]>>32), (long)tf->tf_in[7]);
db_printf("%016llx %016llx %016llx %016llx\n",
(int64_t)tf->tf_global[0], (int64_t)tf->tf_global[1],
(int64_t)tf->tf_global[2], (int64_t)tf->tf_global[3]);
db_printf("%016llx %016llx %016llx %016llx\nouts:\n",
(int64_t)tf->tf_global[4], (int64_t)tf->tf_global[5],
(int64_t)tf->tf_global[6], (int64_t)tf->tf_global[7]);
db_printf("%016llx %016llx %016llx %016llx\n",
(int64_t)tf->tf_out[0], (int64_t)tf->tf_out[1],
(int64_t)tf->tf_out[2], (int64_t)tf->tf_out[3]);
db_printf("%016llx %016llx %016llx %016llx\nlocals:\n",
(int64_t)tf->tf_out[4], (int64_t)tf->tf_out[5],
(int64_t)tf->tf_out[6], (int64_t)tf->tf_out[7]);
db_printf("%016llx %016llx %016llx %016llx\n",
(int64_t)tf->tf_local[0], (int64_t)tf->tf_local[1],
(int64_t)tf->tf_local[2], (int64_t)tf->tf_local[3]);
db_printf("%016llx %016llx %016llx %016llx\nins:\n",
(int64_t)tf->tf_local[4], (int64_t)tf->tf_local[5],
(int64_t)tf->tf_local[6], (int64_t)tf->tf_local[7]);
db_printf("%016llx %016llx %016llx %016llx\n",
(int64_t)tf->tf_in[0], (int64_t)tf->tf_in[1],
(int64_t)tf->tf_in[2], (int64_t)tf->tf_in[3]);
db_printf("%016llx %016llx %016llx %016llx\n",
(int64_t)tf->tf_in[4], (int64_t)tf->tf_in[5],
(int64_t)tf->tf_in[6], (int64_t)tf->tf_in[7]);
#if 0
if (tf == curproc->p_md.md_tf) {
struct rwindow32 *kstack = (struct rwindow32 *)(((caddr_t)tf)+CCFSZ);
db_printf("ins (from stack):\n%08x%08x %08x%08x %08x%08x %08x%08x\n",
(long)(kstack->rw_local[0]>>32), (long)kstack->rw_local[0],
(long)(kstack->rw_local[1]>>32), (long)kstack->rw_local[1],
(long)(kstack->rw_local[2]>>32), (long)kstack->rw_local[2],
(long)(kstack->rw_local[3]>>32), (long)kstack->rw_local[3]);
db_printf("%08x%08x %08x%08x %08x%08x %08x%08x\n",
(long)(kstack->rw_local[4]>>32), (long)kstack->rw_local[4],
(long)(kstack->rw_local[5]>>32), (long)kstack->rw_local[5],
(long)(kstack->rw_local[6]>>32), (long)kstack->rw_local[6],
(long)(kstack->rw_local[7]>>32), (long)kstack->rw_local[7]);
db_printf("ins (from stack):\n%016llx %016llx %016llx %016llx\n",
(int64_t)kstack->rw_local[0], (int64_t)kstack->rw_local[1],
(int64_t)kstack->rw_local[2], (int64_t)kstack->rw_local[3]);
db_printf("%016llx %016llx %016llx %016llx\n",
(int64_t)kstack->rw_local[4], (int64_t)kstack->rw_local[5],
(int64_t)kstack->rw_local[6], (int64_t)kstack->rw_local[7]);
}
#endif
}

6
sys/arch/sparc64/sparc64/emul.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: emul.c,v 1.2 1998/09/05 15:28:09 christos Exp $ */
/* $NetBSD: emul.c,v 1.3 1998/09/05 23:57:27 eeh Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
@ -264,7 +264,7 @@ fixalign(p, tf)
union instr code;
size_t size;
int32_t rs1, rs2;
int64_t rs1, rs2;
int error;
/* fetch and check the instruction that caused the fault */
@ -396,7 +396,7 @@ fixalign(p, tf)
*/
int
emulinstr(pc, tf)
int pc;
vaddr_t pc;
struct trapframe *tf;
{
union instr code;

4
sys/arch/sparc64/sparc64/genassym.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: genassym.c,v 1.3 1998/08/13 02:10:46 eeh Exp $ */
/* $NetBSD: genassym.c,v 1.4 1998/09/05 23:57:27 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@ -69,7 +69,7 @@
#include <sparc64/dev/zsvar.h>
#endif
#include <dev/ic/am7930reg.h>
#include <sparc64/dev/amd7930var.h>
#include <dev/ic/amd7930var.h>
#include <sparc64/dev/fdreg.h>
#include <sparc64/dev/fdvar.h>

4
sys/arch/sparc64/sparc64/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.4 1998/09/05 15:28:10 christos Exp $
# $NetBSD: genassym.cf,v 1.5 1998/09/05 23:57:27 eeh Exp $
#
# Copyright (c) 1997 The NetBSD Foundation, Inc.
@ -106,7 +106,7 @@ include <sparc64/dev/zsvar.h>
endif
include <dev/ic/am7930reg.h>
include <sparc64/dev/amd7930var.h>
include <dev/ic/am7930var.h>
include <sparc64/dev/fdreg.h>
include <sparc64/dev/fdvar.h>

22
sys/arch/sparc64/sparc64/intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.c,v 1.8 1998/08/30 15:32:18 eeh Exp $ */
/* $NetBSD: intr.c,v 1.9 1998/09/05 23:57:28 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@ -111,14 +111,14 @@ strayintr(fp)
{
static int straytime, nstray;
int timesince;
static int swallow_zsintrs;
extern int swallow_zsintrs;
/* If we're in polled mode ignore spurious interrupts */
if (swallow_zsintrs) return;
if ((fp->tf_pil == PIL_SER) /* && swallow_zsintrs */) return;
printf("stray interrupt ipl %x pc=%x npc=%x pstate=%b\n",
fp->tf_pil, (int)fp->tf_pc, (int)fp->tf_npc,
(unsigned int)(fp->tf_tstate>>TSTATE_PSTATE_SHIFT), PSTATE_BITS);
printf("stray interrupt ipl %u pc=%lx npc=%lx pstate=%b\n",
fp->tf_pil, fp->tf_pc, fp->tf_npc,
(unsigned long)(fp->tf_tstate>>TSTATE_PSTATE_SHIFT), PSTATE_BITS);
timesince = time.tv_sec - straytime;
if (timesince <= 10) {
if (++nstray > 500)
@ -251,9 +251,9 @@ intr_establish(level, ih)
/*
* Store in fast lookup table
*/
#ifdef NOTDEF_DEBUG
#ifdef NOT_DEBUG
if (!ih->ih_number) {
printf("intr_establish: NULL vector fun %p arg %p pil %p\n",
printf("\nintr_establish: NULL vector fun %p arg %p pil %p\n",
ih->ih_fun, ih->ih_arg, ih->ih_number, ih->ih_pil);
Debugger();
}
@ -262,9 +262,9 @@ intr_establish(level, ih)
if (intrlev[ih->ih_number])
panic("intr_establish: intr reused %d", ih->ih_number);
intrlev[ih->ih_number] = ih;
#ifdef NOTDEF_DEBUG
printf("intr_establish: vector %p ipl %d clrintr %p fun %p arg %p\n",
ih->ih_number, ih->ih_pil, ih->ih_clr, ih->ih_fun, ih->ih_arg);
#ifdef NOT_DEBUG
printf("\nintr_establish: vector %x ipl mask %x clrintr %p fun %p arg %p\n",
ih->ih_number, ih->ih_pil, (long)ih->ih_clr, ih->ih_fun, ih->ih_arg);
Debugger();
#endif
} else

3
sys/arch/sparc64/sparc64/kgdb_stub.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: kgdb_stub.c,v 1.2 1998/08/13 02:10:46 eeh Exp $ */
/* $NetBSD: kgdb_stub.c,v 1.3 1998/09/05 23:57:28 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@ -68,7 +68,6 @@
#include <machine/autoconf.h>
#include <machine/bsd_openprom.h>
#include <sparc64/sparc64/asm.h>
#include <sparc64/sparc64/kgdb_proto.h>
#ifndef KGDBDEV

147
sys/arch/sparc64/sparc64/locore.s
View File

@ -104,6 +104,7 @@
#ifdef _LP64
/* first constants for storage allocation */
#define PTRSZ 8
#define PTRSHFT 3
#define POINTER .xword
/* Now instructions to load/store pointers */
#define LDPTR ldx
@ -114,6 +115,7 @@
#define STKB BIAS
#else
#define PTRSZ 4
#define PTRSHFT 2
#define POINTER .word
#define LDPTR lduw
#define LDPTRA lduwa
@ -1573,14 +1575,14 @@ intr_setup_msg:
* We don't guarantee any registers are preserved during this operation.
*/
#define INTR_SETUP(stackspace) \
sethi %hi(_C_LABEL(eintstack)), %g6; \
sethi %hi(_C_LABEL(eintstack)-BIAS), %g6; \
sethi %hi((stackspace)), %g5; \
btst 1, %sp; \
bnz,pt %icc, 0f; \
mov %sp, %g1; \
add %sp, -BIAS, %g1; \
0: \
or %g6, %lo(_C_LABEL(eintstack)), %g6; \
or %g6, %lo(_C_LABEL(eintstack)-BIAS), %g6; \
set (_C_LABEL(eintstack)-_C_LABEL(intstack)), %g7; /* XXXXXXXXXX This assumes kernel addresses are unique from user addresses */ \
or %g5, %lo((stackspace)), %g5; \
sub %g6, %g1, %g2; /* Determine if we need to switch to intr stack or not */ \
@ -2643,8 +2645,8 @@ datafault:
mov %g2, %o1
mov %g3, %o2
ldxa [%g0] ASI_AFSR, %o3 ! get async fault status
ldxa [%g0] ASI_AFAR, %o4 ! get async fault address
ldxa [%g0] ASI_AFAR, %o3 ! get async fault address
ldxa [%g0] ASI_AFSR, %o4 ! get async fault status
mov -1, %g7
stxa %g7, [%g0] ASI_AFSR ! And clear this out, too
membar #Sync ! No real reason for this XXXX
@ -2728,6 +2730,7 @@ datafault:
wrpr %g0, PSTATE_INTR, %pstate ! reenable interrupts
mov %o5, %o1 ! (argument: trap address)
mov %g2, %o2 ! (argument: trap pc)
call _C_LABEL(data_access_fault) ! data_access_fault(type, addr, pc, &tf);
add %sp, CC64FSZ + STKB, %o3 ! (argument: &tf)
@ -3558,11 +3561,14 @@ return_from_syscall:
* code.
*
*/
#ifdef DEBUG
#define INTRDEBUG_VECTOR 0x1
#define INTRDEBUG_LEVEL 0x2
#define INTRDEBUG_FUNC 0x4
#define INTRDEBUG_SPUR 0x8
intrdebug: .word 0
.globl _C_LABEL(intrdebug)
_C_LABEL(intrdebug): .word 0
#endif
interrupt_vector:
#ifdef TRAPSTATS
set _C_LABEL(kiveccnt), %g1
@ -3581,14 +3587,21 @@ interrupt_vector:
set intrlev, %g3
bz,pn %icc, 3f ! spurious interrupt
cmp %g2, MAXINTNUM
bgeu iv_halt ! 3f
sllx %g2, 2, %g5 ! Calculate entry number -- 32-bit offset
#ifdef DEBUG
tgeu 55
#endif
bgeu 3f
sllx %g2, PTRSHFT, %g5 ! Calculate entry number
LDPTR [%g3+%g5], %g5 ! We have a pointer to the handler
brz,pn %g5, iv_halt /*3f*/ ! NULL means it isn't registered yet. Skip it.
#ifdef DEBUG
tst %g5
tz 56
#endif
brz,pn %g5, 3f ! NULL means it isn't registered yet. Skip it.
nop
lduh [%g5+IH_PIL], %g6 ! Read interrupt mask
#ifdef NOT_DEBUG
set intrdebug, %g7
#ifdef DEBUG
set _C_LABEL(intrdebug), %g7
ld [%g7], %g7
btst INTRDEBUG_VECTOR, %g7
bz,pt %icc, 1f
@ -3602,6 +3615,7 @@ interrupt_vector:
mov %g2, %o1
rdpr %pil, %o3
GLOBTOLOC
clr %g4
call prom_printf
mov %g6, %o2
LOCTOGLOB
@ -3619,7 +3633,7 @@ interrupt_vector:
3:
#ifdef DEBUG
set intrdebug, %g7
set _C_LABEL(intrdebug), %g7
ld [%g7], %g7
btst INTRDEBUG_SPUR, %g7
bz,pt %icc, 2b
@ -3632,6 +3646,7 @@ interrupt_vector:
set 5f, %o0
mov %g1, %o1
GLOBTOLOC
clr %g4
call prom_printf
rdpr %pil, %o2
LOCTOGLOB
@ -3659,8 +3674,8 @@ iv_halt:
restore
2:
.asciz "interrupt_vector: received %08x:%08x\r\n"
4: .asciz "interrupt_vector: number %x softint mask %x pil %d\r\n"
5: .asciz "interrupt_vector: spurious vector %x at pil %d\r\n"
4: .asciz "interrupt_vector: number %lx softint mask %lx pil %lu\r\n"
5: .asciz "interrupt_vector: spurious vector %lx at pil %d\r\n"
_ALIGN
3:
@ -3779,7 +3794,7 @@ _C_LABEL(sparc_interrupt):
set _C_LABEL(intrcnt), %l4 ! intrcnt[intlev]++;
stb %l5, [%sp + CC64FSZ + STKB + TF_PIL] ! set up intrframe/clockframe
rdpr %pil, %o1
sll %l5, 2, %l3
sll %l5, PTRSHFT, %l3
stb %o1, [%sp + CC64FSZ + STKB + TF_OLDPIL] ! old %pil
ld [%l4 + %l3], %o0
inc %o0
@ -3806,7 +3821,7 @@ _C_LABEL(sparc_interrupt):
mov %sp, %o1
ta 1; nop
0:
set intrdebug, %o0 ! Check intrdebug
set _C_LABEL(intrdebug), %o0 ! Check intrdebug
ld [%o0], %o0
btst INTRDEBUG_LEVEL, %o0
bz,a,pt %icc, 3f
@ -3819,15 +3834,15 @@ _C_LABEL(sparc_interrupt):
clr %l5
#ifdef DEBUG
7: .asciz "sparc_interrupt: stack %p eintstack %p\r\n"
8: .asciz "sparc_interrupt: got lev %d\r\n"
9: .asciz "sparc_interrupt: calling %x:%x(%x:%x) sp = %p\r\n"
8: .asciz "sparc_interrupt: got lev %ld\r\n"
9: .asciz "sparc_interrupt: calling %llx(%llx) sp = %p\r\n"
_ALIGN
#endif
1: LDPTR [%l4 + IH_FUN], %o1 ! do {
LDPTR [%l4 + IH_ARG], %o0
#ifdef DEBUG
set intrdebug, %o2
set _C_LABEL(intrdebug), %o2
ld [%o2], %o2
btst INTRDEBUG_FUNC, %o2
bz,a,pt %icc, 7f
@ -3835,13 +3850,11 @@ _C_LABEL(sparc_interrupt):
save %sp, -CC64FSZ, %sp
set 9b, %o0
srax %i0, 32, %o1
sra %i0, 0, %o2
srax %i1, 32, %o3
mov %i6, %o5
mov %i0, %o2 ! arg
mov %i6, %o3 ! sp
GLOBTOLOC
call prom_printf
srax %i1, 0, %o4
mov %i1, %o1 ! fun
LOCTOGLOB
restore
7:
@ -4645,6 +4658,43 @@ dump_dtlb:
nop
.globl print_dtlb
print_dtlb:
#ifdef _LP64
save %sp, -CC64FSZ, %sp
clr %l1
add %l1, (64*8), %l3
clr %l2
1:
ldxa [%l1] ASI_DMMU_TLB_TAG, %o2
membar #Sync
mov %l2, %o1
ldxa [%l1] ASI_DMMU_TLB_DATA, %o3
membar #Sync
inc %l2
set 2f, %o0
call _C_LABEL(printf)
inc 8, %l1
ldxa [%l1] ASI_DMMU_TLB_TAG, %o2
membar #Sync
mov %l2, %o1
ldxa [%l1] ASI_DMMU_TLB_DATA, %o3
membar #Sync
inc %l2
set 3f, %o0
call _C_LABEL(printf)
inc 8, %l1
cmp %l1, %l3
bl 1b
inc 8, %l0
ret
restore
2:
.asciz "%2d:%016lx %016lx "
3:
.asciz "%2d:%016lx %016lx\r\n"
#else
save %sp, -CC64FSZ, %sp
clr %l1
add %l1, (64*8), %l3
@ -4688,6 +4738,7 @@ print_dtlb:
.asciz "%2d:%08x:%08x %08x:%08x "
3:
.asciz "%2d:%08x:%08x %08x:%08x\r\n"
#endif
.align 8
dostart:
/*
@ -5193,7 +5244,11 @@ _C_LABEL(openfirmware):
mov %g7, %l7
rdpr %pstate, %l0
jmpl %i4, %o7
#ifndef _LP64
wrpr %g0, PSTATE_PROM|PSTATE_IE, %pstate
#else
wrpr %g0, PSTATE_PROM, %pstate
#endif
wrpr %l0, %g0, %pstate
mov %l1, %g1
mov %l2, %g2
@ -5244,7 +5299,11 @@ _C_LABEL(openfirmware):
mov %g6, %l6
mov %g7, %l7
jmpl %o1, %o7
#ifdef _LP64
wrpr %g0, PSTATE_PROM, %pstate ! Enable 64-bit addresses for the prom
#else
wrpr %g0, PSTATE_PROM|PSTATE_IE, %pstate ! Enable 64-bit addresses for the prom
#endif
wrpr %l0, 0, %pstate
wrpr %i2, 0, %pil
#if 0
@ -6719,7 +6778,7 @@ swdebug: .word 0
2:
#endif
#ifdef NOTDEF_DEBUG
set intrdebug, %g1
set _C_LABEL(intrdebug), %g1
mov INTRDEBUG_FUNC, %o1
st %o1, [%g1]
#endif
@ -6818,15 +6877,15 @@ Lsw_scan:
* We found a nonempty run queue. Take its first process.
*/
set _C_LABEL(qs), %o5 ! q = &qs[which];
sll %o4, 3, %o0
sll %o4, PTRSHFT+1, %o0
add %o0, %o5, %o5
ld [%o5], %g3 ! p = q->ph_link;
LDPTR [%o5], %g3 ! p = q->ph_link;
cmp %g3, %o5 ! if (p == q)
be,pn %icc, Lsw_panic_rq ! panic("switch rq");
EMPTY
ld [%g3], %o0 ! tmp0 = p->p_forw;
st %o0, [%o5] ! q->ph_link = tmp0;
st %o5, [%o0 + 4] ! tmp0->p_back = q;
LDPTR [%g3], %o0 ! tmp0 = p->p_forw;
STPTR %o0, [%o5] ! q->ph_link = tmp0;
STPTR %o5, [%o0 + PTRSZ] ! tmp0->p_back = q;
cmp %o0, %o5 ! if (tmp0 == q)
bne 1f
EMPTY
@ -6868,7 +6927,7 @@ Lsw_scan:
sethi %hi(_C_LABEL(want_resched)), %o0
st %g0, [%o0 + %lo(_C_LABEL(want_resched))] ! want_resched = 0;
LDPTR [%g3 + P_ADDR], %g1 ! newpcb = p->p_addr;
STPTR %g0, [%g3 + 4] ! p->p_back = NULL;
STPTR %g0, [%g3 + PTRSZ] ! p->p_back = NULL;
ldub [%g1 + PCB_PIL], %g2 ! newpil = newpcb->pcb_pil;
STPTR %g4, [%g7 + %lo(_C_LABEL(curproc))] ! restore old proc so we can save it
@ -7469,12 +7528,12 @@ ENTRY(probeset)
ENTRY(insque)
ENTRY(_insque)
! %o0 = e = what to insert; %o1 = after = entry to insert after
STPTR %o1, [%o0 + 4] ! e->prev = after;
STPTR %o1, [%o0 + PTRSZ] ! e->prev = after;
LDPTR [%o1], %o2 ! tmp = after->next;
STPTR %o2, [%o0] ! e->next = tmp;
STPTR %o0, [%o1] ! after->next = e;
retl
STPTR %o0, [%o2 + 4] ! tmp->prev = e;
STPTR %o0, [%o2 + PTRSZ] ! tmp->prev = e;
/*
@ -7484,8 +7543,8 @@ ENTRY(remque)
ENTRY(_remque)
! %o0 = e = what to remove
LDPTR [%o0], %o1 ! n = e->next;
LDPTR [%o0 + 4], %o2 ! p = e->prev;
STPTR %o2, [%o1 + 4] ! n->prev = p;
LDPTR [%o0 + PTRSZ], %o2 ! p = e->prev;
STPTR %o2, [%o1 + PTRSZ] ! n->prev = p;
retl
STPTR %o1, [%o2] ! p->next = n;
@ -9026,6 +9085,11 @@ ENTRY(delay) ! %o0 = n
retl ! return
nop ! [delay slot]
#else
#ifdef NOT_DEBUG
set 100*MICROPERSEC, %o1
cmp %o0, %o1
tge %xcc, 1
#endif
rdpr %tick, %g1 ! Take timer snapshot
sethi %hi(_C_LABEL(cpu_clockrate)), %g2
sethi %hi(MICROPERSEC), %o2
@ -9045,7 +9109,20 @@ ENTRY(delay) ! %o0 = n
retl
nop
/*
* If something's wrong with the standard setup do this stupid loop
* calibrated for a 143MHz processor.
*/
Lstupid_delay:
set 142857143/MICROPERSEC, %o1
Lstupid_loop:
brnz,pt %o1, Lstupid_loop
dec %o1
brnz,pt %o0, Lstupid_delay
dec %o0
retl
nop
#endif
ENTRY(setjmp)

193
sys/arch/sparc64/sparc64/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.8 1998/09/02 05:51:39 eeh Exp $ */
/* $NetBSD: machdep.c,v 1.9 1998/09/05 23:57:28 eeh Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -133,7 +133,6 @@
#include <machine/openfirm.h>
#include <machine/sparc64.h>
#include <sparc64/sparc64/asm.h>
#include <sparc64/sparc64/cache.h>
#include <sparc64/sparc64/vaddrs.h>
@ -574,6 +573,15 @@ cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p)
/* NOTREACHED */
}
#ifdef _LP64
#define rwindow rwindow64
#define STACK_OFFSET BIAS
#define CPOUTREG(l,v) copyout(&(v), (l), sizeof(v))
#else
#define rwindow rwindow32
#define STACK_OFFSET 0
#define CPOUTREG(l,v) suword((l), (v))
#endif
/*
* Send an interrupt to process.
*/
@ -588,7 +596,7 @@ sendsig(catcher, sig, mask, code)
register struct sigframe *fp;
register struct trapframe *tf;
vaddr_t addr, oonstack;
struct rwindow32 *kwin, *oldsp, *newsp, /* DEBUG */tmpwin;
struct rwindow *oldsp, *newsp, /* DEBUG */tmpwin;
struct sigframe sf;
extern char sigcode[], esigcode[];
#define szsigcode (esigcode - sigcode)
@ -599,7 +607,7 @@ sendsig(catcher, sig, mask, code)
#endif
tf = p->p_md.md_tf;
oldsp = (struct rwindow32 *)tf->tf_out[6];
oldsp = (struct rwindow *)(tf->tf_out[6] + STACK_OFFSET);
oonstack = psp->ps_sigstk.ss_flags & SS_ONSTACK;
/*
* Compute new user stack addresses, subtract off
@ -612,7 +620,7 @@ sendsig(catcher, sig, mask, code)
psp->ps_sigstk.ss_flags |= SS_ONSTACK;
} else
fp = (struct sigframe *)oldsp;
fp = (struct sigframe *)((long)(fp - 1) & ~7);
fp = (struct sigframe *)((long)(fp - 1) & ~0x0f);
#ifdef DEBUG
sigpid = p->p_pid;
@ -629,17 +637,19 @@ sendsig(catcher, sig, mask, code)
*/
sf.sf_signo = sig;
sf.sf_code = code;
#ifndef __LP64
#ifdef COMPAT_SUNOS
sf.sf_scp = &fp->sf_sc;
#endif
sf.sf_addr = 0; /* XXX */
#endif
/*
* Build the signal context to be used by sigreturn.
*/
sf.sf_sc.sc_onstack = oonstack;
sf.sf_sc.sc_mask = mask;
sf.sf_sc.sc_sp = (long)oldsp;
sf.sf_sc.sc_sp = (long)tf->tf_out[6];
sf.sf_sc.sc_pc = tf->tf_pc;
sf.sf_sc.sc_npc = tf->tf_npc;
sf.sf_sc.sc_psr = TSTATECCR_TO_PSR(tf->tf_tstate); /* XXX */
@ -655,30 +665,18 @@ sendsig(catcher, sig, mask, code)
* joins seamlessly with the frame it was in when the signal occurred,
* so that the debugger and _longjmp code can back up through it.
*/
newsp = (struct rwindow32 *)((vaddr_t)fp - sizeof(struct rwindow32));
newsp = (struct rwindow *)((vaddr_t)fp - sizeof(struct rwindow));
write_user_windows();
#ifdef DEBUG
if ((sigdebug & SDB_KSTACK))
printf("sendsig: saving sf to %p, setting stack pointer %p to %p\n",
fp, &(((union rwindow *)newsp)->v8.rw_in[6]), oldsp);
fp, &(((struct rwindow *)newsp)->rw_in[6]), (vaddr_t)tf->tf_out[6]);
#endif
kwin = (struct rwindow32 *)(((caddr_t)tf)-CCFSZ);
if (rwindow_save(p) || /* copyout(((caddr_t)tf)+CCFSZ, (caddr_t)oldsp, sizeof(struct rwindow32)) || */
#ifndef TRAPWIN
suword(&oldsp->rw_in[0], tf->tf_in[0]) || suword(&oldsp->rw_in[1], tf->tf_in[1]) ||
suword(&oldsp->rw_in[2], tf->tf_in[2]) || suword(&oldsp->rw_in[3], tf->tf_in[3]) ||
suword(&oldsp->rw_in[4], tf->tf_in[4]) || suword(&oldsp->rw_in[5], tf->tf_in[5]) ||
suword(&oldsp->rw_in[6], tf->tf_in[6]) || suword(&oldsp->rw_in[7], tf->tf_in[7]) ||
suword(&oldsp->rw_local[0], (int)tf->tf_local[0]) || suword(&oldsp->rw_local[1], (int)tf->tf_local[1]) ||
suword(&oldsp->rw_local[2], (int)tf->tf_local[2]) || suword(&oldsp->rw_local[3], (int)tf->tf_local[3]) ||
suword(&oldsp->rw_local[4], (int)tf->tf_local[4]) || suword(&oldsp->rw_local[5], (int)tf->tf_local[5]) ||
suword(&oldsp->rw_local[6], (int)tf->tf_local[6]) || suword(&oldsp->rw_local[7], (int)tf->tf_local[7]) ||
#endif
copyout((caddr_t)&sf, (caddr_t)fp, sizeof sf) ||
if (rwindow_save(p) || copyout((caddr_t)&sf, (caddr_t)fp, sizeof sf) ||
#ifdef DEBUG
copyin(oldsp, &tmpwin, sizeof(tmpwin)) || copyout(&tmpwin, newsp, sizeof(tmpwin)) ||
#endif
suword(&(((union rwindow *)newsp)->v8.rw_in[6]), (vaddr_t)oldsp)) {
CPOUTREG(&(((struct rwindow *)newsp)->rw_in[6]), tf->tf_out[6])) {
/*
* Process has trashed its stack; give it an illegal
* instruction to halt it in its tracks.
@ -693,11 +691,6 @@ sendsig(catcher, sig, mask, code)
/* NOTREACHED */
}
#if 0
/* Now we need to update %i6 in the trap frame -- this was saved to kernel space */
(((union rwindow *)(((caddr_t)tf)-CCFSZ))->v8.rw_in[6]) = oldsp;
#endif
#ifdef DEBUG
if (sigdebug & SDB_FOLLOW) {
printf("sendsig: %s[%d] sig %d scp %p\n",
@ -719,7 +712,7 @@ sendsig(catcher, sig, mask, code)
}
tf->tf_pc = addr;
tf->tf_npc = addr + 4;
tf->tf_out[6] = (register64_t)newsp;
tf->tf_out[6] = (vaddr_t)newsp - STACK_OFFSET;
#ifdef DEBUG
if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid) {
printf("sendsig: about to return to catcher %p thru %p\n",
@ -751,7 +744,7 @@ sys_sigreturn(p, v, retval)
struct sigcontext *scp;
struct sigcontext sc;
register struct trapframe *tf;
struct rwindow32 *rwstack, *kstack;
struct rwindow *rwstack, *kstack;
#ifndef TRAPWIN
int i;
#endif
@ -811,46 +804,10 @@ sys_sigreturn(p, v, retval)
tf->tf_out[0] = (int64_t)sc.sc_o0;
tf->tf_out[6] = (int64_t)sc.sc_sp;
rwstack = (struct rwindow32 *)tf->tf_out[6];
#ifndef TRAPWIN
#if 0
kstack = (struct rwindow32 *)(((caddr_t)tf)-CCFSZ);
for (i=0; i<8; i++) {
tf->tf_local[i] = (int64_t)fuword(&rwstack->rw_local[i]);
kstack->rw_in[i] = (int)fuword(&rwstack->rw_in[i]);
}
#else
kstack = (struct rwindow32 *)(((caddr_t)tf)-CCFSZ);
for (i=0; i<8; i++) {
int tmp;
if (copyin((caddr_t)&rwstack->rw_local[i], &tmp, sizeof tmp)) {
printf("sigreturn: cannot load \%l%d from %p\n", i, &rwstack->rw_local[i]);
Debugger();
}
tf->tf_local[i] = (int64_t)tmp;
if (copyin((caddr_t)&rwstack->rw_in[i], &tmp, sizeof tmp)) {
printf("sigreturn: cannot load \%i%d from %p\n", i, &rwstack->rw_in[i]);
Debugger();
}
tf->tf_in[i] = (int)tmp;
}
#endif
#endif
#ifdef DEBUG
/* Need to sync tf locals and ins with stack to prevent panic */
{
int i;
kstack = (struct rwindow32 *)tf->tf_out[6];
for (i=0; i<8; i++) {
tf->tf_local[i] = fuword(&kstack->rw_local[i]);
tf->tf_in[i] = fuword(&kstack->rw_in[i]);
}
}
#endif
#ifdef DEBUG
if (sigdebug & SDB_FOLLOW) {
printf("sys_sigreturn: return trapframe pc=%p sp=%p tstate=%x\n",
(int)tf->tf_pc, (int)tf->tf_out[6], (int)tf->tf_tstate);
printf("sys_sigreturn: return trapframe pc=%p sp=%p tstate=%llx\n",
(vaddr_t)tf->tf_pc, (vaddr_t)tf->tf_out[6], tf->tf_tstate);
if (sigdebug & SDB_DDB) Debugger();
}
#endif
@ -1137,10 +1094,10 @@ stackdump()
if( ((long)fp) & 1 ) {
fp64 = (struct frame64*)(((char*)fp)+BIAS);
/* 64-bit frame */
printf("%x(%x:%x,%x:%x,%x:%x,%x:%x,%x:%x,%x:%x,%x:%x)sp=%p",
(long)fp64->fr_pc, fp64->fr_arg[0], fp64->fr_arg[1], fp64->fr_arg[2],
printf("%x(%llx,%llx,%llx,%llx,%llx,%llx,%llx)sp=%p",
fp64->fr_pc, fp64->fr_arg[0], fp64->fr_arg[1], fp64->fr_arg[2],
fp64->fr_arg[3], fp64->fr_arg[4], fp64->fr_arg[5], fp64->fr_arg[6],
(long)fp64->fr_fp);
fp64->fr_fp);
fp = (struct frame32*)fp64->fr_fp;
} else {
/* 32-bit frame */
@ -1153,67 +1110,6 @@ stackdump()
}
}
#if 0 /* Obsolete? */
/*
* Map an I/O device given physical address and size in bytes, e.g.,
*
* mydev = (struct mydev *)mapdev(myioaddr, 0,
* 0, sizeof(struct mydev));
*
* See also machine/autoconf.h.
*/
void *
mapdev(phys, virt, offset, size)
register struct rom_reg *phys;
register int offset, virt, size;
{
register vaddr_t v;
register u_int64_t pa;
register void *ret;
static vaddr_t iobase;
if (iobase == NULL)
iobase = IODEV_BASE;
size = round_page(size);
if (size == 0) panic("mapdev: zero size");
if (virt)
v = trunc_page(virt);
else {
v = iobase;
iobase += size;
if (iobase > IODEV_END) /* unlikely */
panic("mapiodev");
}
ret = (void *)(v | (((u_long)phys->rr_paddr + offset) & PGOFSET));
/* note: preserve page offset */
pa = ((u_int64_t)phys->rr_iospace<<32) | trunc_page(phys->rr_paddr + offset);
#ifdef NOTDEF_DEBUG
printf("mapdev: io=%x pa=%x va=%x pa=%x:%x\n", phys->rr_iospace, phys->rr_paddr,
v, (int)(pa>>32), (int)pa);
#endif
do {
int i;
for (i=0; page_size_map[i].mask; i++) {
if (((pa | v) & page_size_map[i].mask) == 0
&& page_size_map[i].mask < size)
break;
}
do {
pmap_enter_phys(pmap_kernel(), v, pa | PMAP_NC,
page_size_map[i].code,
VM_PROT_READ | VM_PROT_WRITE, 1);
v += PAGE_SIZE;
pa += PAGE_SIZE;
} while (pa & page_size_map[i].mask);
} while ((size -= PAGE_SIZE) > 0);
return (ret);
}
#endif
int
cpu_exec_aout_makecmds(p, epp)
@ -1293,9 +1189,9 @@ wcopy(vb1, vb2, l)
*b2 = *b1e;
}
static bus_addr_t dvmamap_alloc __P((int, int));
bus_addr_t dvmamap_alloc __P((int, int));
static __inline__ bus_addr_t
bus_addr_t
dvmamap_alloc(size, flags)
int size;
int flags;
@ -1321,9 +1217,9 @@ dvmamap_alloc(size, flags)
return ((bus_addr_t)rctov(pn));
}
static void dvmamap_free __P((bus_addr_t, bus_size_t));
void dvmamap_free __P((bus_addr_t, bus_size_t));
static __inline__ void
void
dvmamap_free (addr, size)
bus_addr_t addr;
bus_size_t size;
@ -1630,15 +1526,11 @@ _bus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags)
if (error)
return (error);
dvmaddr = dvmamap_alloc(size, flags);
if (dvmaddr == (bus_addr_t)-1)
return (ENOMEM);
/*
* Compute the location, size, and number of segments actually
* returned by the VM code.
*/
segs[0].ds_addr = dvmaddr;
segs[0].ds_addr= NULL; /* UPA does not map things */
segs[0].ds_len = size;
*rsegs = 1;
@ -1671,13 +1563,6 @@ _bus_dmamem_free(t, segs, nsegs)
if (nsegs != 1)
panic("bus_dmamem_free: nsegs = %d", nsegs);
addr = segs[0].ds_addr;
len = segs[0].ds_len;
dvmamap_free(addr, len);
/* The bus driver should do the actual unmapping */
/*
* Return the list of pages back to the VM system.
*/
@ -1873,7 +1758,7 @@ sparc_bus_map(t, iospace, addr, size, flags, vaddr, hp)
{
vaddr_t v;
u_int64_t pa;
static vaddr_t iobase;
static vaddr_t iobase = IODEV_BASE;
if (iobase == NULL)
@ -1900,13 +1785,13 @@ static vaddr_t iobase;
pa = addr & ~PAGE_MASK; /* = trunc_page(addr); Will drop high bits */
#ifdef NOTDEF_DEBUG
printf("\nsparc_bus_map: type %x addr %x:%x virt %x paddr %x:%x\n",
iospace, (int)(addr>>32), (int)addr, (int)*hp, (int)(pa>>32), (int)pa);
printf("\nsparc_bus_map: type %x addr %p virt %p paddr %llx\n",
iospace, addr, *hp, (paddr_t)pa);
#endif
do {
#ifdef NOTDEF_DEBUG
printf("sparc_bus_map: phys %x:%x virt %p hp %x:%x\n",
printf("sparc_bus_map: phys %llx virt %p hp %llx\n",
(int)(pa>>32), (int)pa, v, (int)((*hp)>>32), (int)*hp);
#endif
pmap_enter_phys(pmap_kernel(), v, pa | PMAP_NC, NBPG,
@ -1941,9 +1826,9 @@ sparc_bus_mmap(t, iospace, paddr, flags, hp)
{
*hp = (bus_space_handle_t)(paddr>>PGSHIFT);
#if 0
printf("sparc_bus_mmap: encoding pa %x:%x as %x:%x becomes %x:%x\n",
(int)(paddr>>32), (int)(paddr), (int)((*hp)>>32), (int)*hp,
(int)(pmap_phys_address(*hp)>>32), (int)(pmap_phys_address(*hp)));
printf("sparc_bus_mmap: encoding pa %llx as %llx becomes %llx\n",
(bus_addr_t)(paddr), (bus_space_handle_t)*hp,
(paddr_t)(pmap_phys_address(*hp)));
#endif
return (0);
}

3
sys/arch/sparc64/sparc64/mem.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mem.c,v 1.3 1998/08/13 02:10:47 eeh Exp $ */
/* $NetBSD: mem.c,v 1.4 1998/09/05 23:57:28 eeh Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -55,7 +55,6 @@
#include <sys/conf.h>
#include <sparc64/sparc64/vaddrs.h>
#include <sparc64/sparc64/asm.h>
#include <machine/eeprom.h>
#include <machine/conf.h>
#include <machine/ctlreg.h>

13
sys/arch/sparc64/sparc64/memreg.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: memreg.c,v 1.1.1.1 1998/06/20 04:58:52 eeh Exp $ */
/* $NetBSD: memreg.c,v 1.2 1998/09/05 23:57:28 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@ -55,7 +55,6 @@
#include <sparc64/sparc64/memreg.h>
#include <sparc64/sparc64/vaddrs.h>
#include <sparc64/sparc64/asm.h>
#include <machine/reg.h> /* for trapframe */
#include <machine/trap.h> /* for trap types */
@ -195,7 +194,7 @@ hardmemerr4m(issync, fsr, faddr)
case 1:
if ((fsr & SFSR_FT) == SFSR_FT_NONE)
return;
panic("mem err: sfsr=%b sfaddr=%x", fsr, SFSR_BITS, faddr);
panic("mem err: sfsr=%qb sfaddr=%x", fsr, SFSR_BITS, faddr);
break;
case 0:
if (!(fsr & AFSR_AFO))
@ -206,7 +205,7 @@ hardmemerr4m(issync, fsr, faddr)
break;
default: /* unknown; print both decodings*/
panic("Unknown mem err: if sync, fsr=%b fva=%x; if async, fsr"
"=%b fa=%x pa=%x%x", fsr, SFSR_BITS, faddr, fsr,
"=%qb fa=%x pa=%x%x", fsr, SFSR_BITS, faddr, fsr,
AFSR_BITS, faddr, (fsr & AFSR_AFA) >> AFSR_AFA_RSHIFT,
faddr);
break;
@ -275,7 +274,7 @@ memerr4m(type, sfsr, sfva, afsr, afva, tf)
oldtype = T_DATAFAULT;
} else if (type == 0) { /* NMI */
printf("ERROR: got NMI with sfsr=0x%b, sfva=0x%x, afsr=0x%b, "
printf("ERROR: got NMI with sfsr=0x%qb, sfva=0x%x, afsr=0x%b, "
"afaddr=0x%x. Retrying...\n",
sfsr,SFSR_BITS,sfva,afsr, AFSR_BITS,afva);
if (oldtype == 0 || addrold == sfva)
@ -285,8 +284,8 @@ memerr4m(type, sfsr, sfva, afsr, afva, tf)
oldtype = 0;
addrold = sfva;
} else /* something we don't know about?!? */ {
panic("memerr4m: unknown fatal memory error. type=%d, sfsr=%b,"
" sfva=%x, afsr=%b, afaddr=%x",
panic("memerr4m: unknown fatal memory error. type=%d, sfsr=%qb,"
" sfva=%x, afsr=%qb, afaddr=%x",
type, sfsr, SFSR_BITS, sfva, afsr, AFSR_BITS, afva);
}

9
sys/arch/sparc64/sparc64/openfirm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: openfirm.c,v 1.5 1998/09/02 05:51:39 eeh Exp $ */
/* $NetBSD: openfirm.c,v 1.6 1998/09/05 23:57:29 eeh Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@ -499,6 +499,7 @@ OF_write(handle, addr, len)
args.nreturns = 1;
args.ihandle = HDL2CELL(handle);
args.addr = ADR2CELL(addr);
if (len>1024) { prom_printf("OF_write() > 1024\n"); Debugger(); }
for (; len > 0; len -= l, addr += l) {
l = min(NBPG, len);
args.len = l;
@ -669,6 +670,9 @@ void OF_sym2val(cells)
db_sym_t symbol;
db_expr_t value;
/* Set data segment pointer */
__asm __volatile("clr %%g4" : :);
/* No args? Nothing to do. */
if (!args->nargs ||
!args->nreturns) return;
@ -701,6 +705,9 @@ void OF_val2sym(cells)
db_expr_t value;
db_expr_t offset;
/* Set data segment pointer */
__asm __volatile("clr %%g4" : :);
/* No args? Nothing to do. */
if (!args->nargs ||
!args->nreturns) return;

14
sys/arch/sparc64/sparc64/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.10 1998/09/02 05:51:39 eeh Exp $ */
/* $NetBSD: pmap.c,v 1.11 1998/09/05 23:57:29 eeh Exp $ */
/* #define NO_VCACHE /* Don't forget the locked TLB in dostart */
#define HWREF
/* #define BOOT_DEBUG */
@ -1348,7 +1348,7 @@ void
pmap_collect(pm)
struct pmap *pm;
{
#if 0
#if 1
int i, j, k, n, m;
paddr_t *pdir, *ptbl;
/* This is a good place to scan the pmaps for page tables with
@ -1358,7 +1358,7 @@ pmap_collect(pm)
if ((pdir = (paddr_t *)ldxa(&pm->pm_segs[i], ASI_PHYS_CACHED))) {
m = 0;
for (k=0; k<PDSZ; k++) {
if (ptbl = (paddr_t)ldxa(&pdir[k], ASI_PHYS_CACHED)) {
if ((ptbl = (paddr_t)ldxa(&pdir[k], ASI_PHYS_CACHED))) {
m++;
n = 0;
for (j=0; j<PTSZ; j++) {
@ -2188,15 +2188,15 @@ pmap_extract(pm, va)
if (pmapdebug & PDB_EXTRACT) {
paddr_t pa;
pa = ldxa(&pm->pm_segs[va_to_seg(va)], ASI_PHYS_CACHED);
printf("pmap_extract: va=%p segs[%d]=%lx", va, (int)va_to_seg(va), (long)pa);
printf("pmap_extract: va=%p segs[%ld]=%lx", va, (long)va_to_seg(va), (long)pa);
if (pa) {
pa = ldxa(&((paddr_t*)pa)[va_to_dir(va)], ASI_PHYS_CACHED);
printf(" segs[%d][%d]=%lx", va_to_seg(va), (int)va_to_dir(va), (long)pa);
printf(" segs[%ld][%ld]=%lx", va_to_seg(va), (long)va_to_dir(va), (long)pa);
}
if (pa) {
pa = ldxa(&((paddr_t*)pa)[va_to_pte(va)], ASI_PHYS_CACHED);
printf(" segs[%d][%d][%d]=%lx", (int)va_to_seg(va),
(int)va_to_dir(va), (int)va_to_pte(va), (long)pa);
printf(" segs[%ld][%ld][%ld]=%lx", (long)va_to_seg(va),
(long)va_to_dir(va), (long)va_to_pte(va), (long)pa);
}
db_printf(" pseg_get: %lx\n", (long)pa);
}

63
sys/arch/sparc64/sparc64/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.10 1998/09/02 05:51:40 eeh Exp $ */
/* $NetBSD: trap.c,v 1.11 1998/09/05 23:57:29 eeh Exp $ */
/*
* Copyright (c) 1996
@ -71,7 +71,6 @@
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <sparc64/sparc64/asm.h>
#include <machine/cpu.h>
#include <machine/ctlreg.h>
#include <machine/trap.h>
@ -155,7 +154,7 @@ int rwindow_debug = RW_64|RW_ERR;
#define TDB_STOPCALL 0x200
#define TDB_STOPCPIO 0x400
#define TDB_SYSTOP 0x800
int trapdebug = 0|TDB_FOLLOW|TDB_STOPSIG|TDB_STOPCPIO;
int trapdebug = 0|TDB_STOPSIG|TDB_STOPCPIO/*|TDB_FOLLOW*/;
/* #define __inline */
#endif
@ -997,8 +996,8 @@ data_access_fault(type, addr, pc, tf)
/* if (cpcb->pcb_nsaved > 6) trapdebug |= TDB_NSAVED; */
if ((trapdebug&TDB_NSAVED && cpcb->pcb_nsaved) || trapdebug&(TDB_ADDFLT|TDB_FOLLOW)) {
printf("%ld: data_access_fault(%lx, %p, %p, %p) nsaved=%d\n",
(long)(curproc?curproc->p_pid:-1), (long)type, (void*)addr, (void*)pc, (void*)tf,
(int)cpcb->pcb_nsaved);
(long)(curproc?curproc->p_pid:-1), (long)type, (void*)addr,
(void*)pc, (void*)tf, (int)cpcb->pcb_nsaved);
if ((trapdebug&TDB_NSAVED && cpcb->pcb_nsaved)) Debugger();
}
if (trapdebug & TDB_FRAME) {
@ -1137,7 +1136,7 @@ kfault:
(long)p->p_addr->u_pcb.pcb_onfault : 0;
if (!onfault) {
(void) splhigh();
printf("data fault: pc=%x addr=%x\n",
printf("data fault: pc=%lx addr=%x\n",
pc, addr);
DEBUGGER(type, tf);
panic("kernel fault");
@ -1145,7 +1144,7 @@ kfault:
}
#ifdef DEBUG
if (trapdebug&(TDB_ADDFLT|TDB_FOLLOW|TDB_STOPCPIO)) {
printf("data_access_fault: copyin/out fault -- recover\n");
printf("data_access_fault: copyin/out of %p fault -- recover\n", addr);
Debugger();
}
#endif
@ -1191,7 +1190,7 @@ data_access_error(type, sfva, sfsr, afva, afsr, tf)
register u_long afsr;
register struct trapframe *tf;
{
register int pc;
register u_long pc;
register u_int64_t tstate;
register struct proc *p;
register struct vmspace *vm;
@ -1208,25 +1207,25 @@ data_access_error(type, sfva, sfsr, afva, afsr, tf)
if (protmmu || missmmu) {
extern int trap_trace_dis;
trap_trace_dis = 1;
printf("%d: data_access_error(%x, %x, %x, %x) %s=%d\n",
printf("%d: data_access_error(%x, %lx, %lx, %lx) %s=%d\n",
curproc?curproc->p_pid:-1, type, sfva, afva, tf,
(protmmu)?"protmmu":"missmmu", (protmmu)?protmmu:missmmu);
Debugger();
}
write_user_windows();
if ((trapdebug&TDB_NSAVED && cpcb->pcb_nsaved) || trapdebug&(TDB_ADDFLT|TDB_FOLLOW))
printf("%d data_access_error(%x, %x, %x, %x)=%x:%x @ %x %b\n",
curproc?curproc->p_pid:-1,
type, sfva, afva, tf, (long)(tf->tf_tstate>>32),
(long)tf->tf_tstate, (long)tf->tf_pc, sfsr, SFSR_BITS);
printf("%ld data_access_error(%lx, %lx, %lx, %p)=%lx @ %p %lx %%qb\n",
(long)curproc?curproc->p_pid:-1,
(long)type, (long)sfva, (long)afva, tf, (long)tf->tf_tstate,
(long)tf->tf_pc, (long)sfsr, SFSR_BITS);
if (trapdebug & TDB_FRAME) {
print_trapframe(tf);
}
if ((trapdebug & TDB_TL) && tl()) {
printf("%d tl %d data_access_error(%x, %x, %x, %x)=%x:%x @ %x %b\n",
curproc?curproc->p_pid:-1, tl(),
type, sfva, afva, tf, (long)(tf->tf_tstate>>32),
(long)tf->tf_tstate, (long)tf->tf_pc, sfsr, SFSR_BITS);
printf("%ld tl %ld data_access_error(%lx, %lx, %lx, %p)=%lx @ %lx %%qb\n",
(long)curproc?curproc->p_pid:-1, (long)tl(),
(long)type, (long)sfva, (long)afva, tf, (long)tf->tf_tstate,
(long)tf->tf_pc, (long)sfsr, SFSR_BITS);
Debugger();
}
if (trapdebug&TDB_STOPCALL) {
@ -1266,6 +1265,7 @@ data_access_error(type, sfva, sfsr, afva, afsr, tf)
printf("data memory error type %x sfsr=%p sfva=%p afsr=%p afva=%p tf=%p\n",
type, sfsr, sfva, afsr, afva, tf);
if (tstate & (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT)) {
DEBUGGER(type, tf);
/* User fault -- Berr */
trapsignal(p, SIGBUS, (u_long)sfva);
} else {
@ -1395,8 +1395,8 @@ kfault:
(long)p->p_addr->u_pcb.pcb_onfault : 0;
if (!onfault) {
(void) splhigh();
printf("data fault: pc=%x addr=%x sfsr=%b\n",
pc, sfva, sfsr, SFSR_BITS);
printf("data fault: pc=%lx addr=%lx sfsr=%%qb\n",
(u_long)pc, (long)sfva, (long)sfsr, SFSR_BITS);
DEBUGGER(type, tf);
panic("kernel fault");
/* NOTREACHED */
@ -1585,25 +1585,25 @@ text_access_error(type, pc, sfsr, afva, afsr, tf)
if (protmmu || missmmu) {
extern int trap_trace_dis;
trap_trace_dis = 1;
printf("%d: text_access_error(%x, %x, %x, %x) %s=%d\n",
curproc?curproc->p_pid:-1, type, sfsr, afsr, tf,
printf("%ld: text_access_error(%lx, %lx, %lx, %lx) %s=%d\n",
(long)curproc?curproc->p_pid:-1, (long)type, (long)sfsr, (long)afsr, tf,
(protmmu)?"protmmu":"missmmu", (protmmu)?protmmu:missmmu);
Debugger();
}
write_user_windows();
if ((trapdebug&TDB_NSAVED && cpcb->pcb_nsaved) || trapdebug&(TDB_TXTFLT|TDB_FOLLOW))
printf("%d text_access_error(%x, %x, %x, %x)=%x:%x @ %x %b\n",
curproc?curproc->p_pid:-1,
type, pc, afva, tf, (long)(tf->tf_tstate>>32),
(long)tf->tf_tstate, (long)tf->tf_pc, sfsr, SFSR_BITS);
printf("%ld text_access_error(%lx, %lx, %lx, %p)=%lx @ %lx %%qb\n",
(long)curproc?curproc->p_pid:-1,
(long)type, pc, (long)afva, tf, (long)tf->tf_tstate,
(long)tf->tf_pc, (long)sfsr, SFSR_BITS);
if (trapdebug & TDB_FRAME) {
print_trapframe(tf);
}
if ((trapdebug & TDB_TL) && tl()) {
printf("%d tl %d text_access_error(%x, %x, %x, %x)=%x:%x @ %x %b\n",
curproc?curproc->p_pid:-1, tl(),
type, pc, afva, tf, (long)(tf->tf_tstate>>32),
(long)tf->tf_tstate, (long)tf->tf_pc, sfsr, SFSR_BITS);
printf("%ld tl %ld text_access_error(%lx, %lx, %lx, %p)=%lx @ %lx %%qb\n",
(long)curproc?curproc->p_pid:-1, (long)tl(),
(long)type, (long)pc, (long)afva, tf,
(long)tf->tf_tstate, (long)tf->tf_pc, (long)sfsr, SFSR_BITS);
Debugger();
}
if (trapdebug&TDB_STOPCALL) {
@ -1661,8 +1661,7 @@ text_access_error(type, pc, sfsr, afva, afsr, tf)
ftype = VM_PROT_READ;
if (tstate & (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT)) {
(void) splhigh();
printf("text error: pc=%x sfsr=%b\n", pc,
sfsr, SFSR_BITS, pc);
printf("text error: pc=%lx sfsr=%%qb\n", pc, (long)sfsr, SFSR_BITS);
DEBUGGER(type, tf);
panic("kernel fault");
/* NOTREACHED */
@ -1696,7 +1695,7 @@ text_access_error(type, pc, sfsr, afva, afsr, tf)
*/
if (tstate & TSTATE_PRIV) {
(void) splhigh();
printf("text error: pc=%x sfsr=%b\n",
printf("text error: pc=%lx sfsr=%%qb\n",
pc, sfsr, SFSR_BITS);
DEBUGGER(type, tf);
panic("kernel fault");

14
sys/arch/sparc64/sparc64/vaddrs.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: vaddrs.h,v 1.2 1998/07/07 03:05:05 eeh Exp $ */
/* $NetBSD: vaddrs.h,v 1.3 1998/09/05 23:57:29 eeh Exp $ */
/*
* Copyright (c) 1996
@ -69,7 +69,7 @@
*/
#ifndef IODEV_0
#define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */
#define IODEV_0 0x0fe000000L /* must match VM_MAX_KERNEL_ADDRESS */
#define _MAXNBPG 8192 /* fixed VAs, independent of actual NBPG */
#define _MAXNCPU 4 /* fixed VA allocation allows 4 CPUs */
@ -86,7 +86,7 @@
#define PI_INTR_VA ( MSGBUF_VA + _MAXNBPG) /* [4m] */
#define SI_INTR_VA ( PI_INTR_VA + _MAXNBPG*_MAXNCPU) /* [4m] */
#define IODEV_BASE ( SI_INTR_VA + _MAXNBPG)
#define IODEV_END 0xff000000 /* 16 MB of iospace */
#define IODEV_END 0x0ff000000L /* 16 MB of iospace */
/*
* The next constant defines the amount of reserved DVMA space on the
@ -126,9 +126,9 @@
* We will use the 8MB size for now.
*/
#define DVMA_BASE 0xff800000 /* can change subject to above rule */
#define DVMA_TOP 0xffffffff /* do not modify */
#define DVMA_START 0xff800000 /* 8M of DVMA */
#define DVMA_END 0xfff00000 /* XXX is this enough? */
#define DVMA_BASE 0x0ff800000L /* can change subject to above rule */
#define DVMA_TOP 0x0ffffffffL /* do not modify */
#define DVMA_START 0x0ff800000L /* 8M of DVMA */
#define DVMA_END 0x0fff00000L /* XXX is this enough? */
#endif /* IODEV_0 */

32
sys/arch/sparc64/sparc64/vm_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vm_machdep.c,v 1.6 1998/08/30 15:32:19 eeh Exp $ */
/* $NetBSD: vm_machdep.c,v 1.7 1998/09/05 23:57:29 eeh Exp $ */
/*
* Copyright (c) 1996
@ -203,8 +203,12 @@ vunmapbuf(bp, len)
*/
#ifdef _LP64
#define TOPFRAMEOFF (USPACE-sizeof(struct trapframe)-sizeof(struct frame64))
#define rwindow rwindow64
#define STACK_OFFSET BIAS
#else
#define TOPFRAMEOFF (USPACE-sizeof(struct trapframe)-sizeof(struct frame32))
#define rwindow rwindow32
#define STACK_OFFSET 0
#endif
#ifdef DEBUG
@ -226,7 +230,7 @@ cpu_fork(p1, p2)
register struct pcb *opcb = &p1->p_addr->u_pcb;
register struct pcb *npcb = &p2->p_addr->u_pcb;
register struct trapframe *tf2;
register struct rwindow32 *rp;
register struct rwindow *rp;
/*
* Save all user registers to p1's stack or, in the case of
@ -301,26 +305,14 @@ cpu_fork(p1, p2)
tf2->tf_out[0] = 0;
tf2->tf_out[1] = 1;
#ifdef DEBUG
/* Need to sync tf locals and ins with stack to prevent panic */
{
int i;
rp = (struct rwindow32 *)tf2->tf_out[6];
for (i=0; i<8; i++) {
tf2->tf_local[i] = fuword(&rp->rw_local[i]);
tf2->tf_in[i] = fuword(&rp->rw_in[i]);
}
}
#endif
/* Construct kernel frame to return to in cpu_switch() */
rp = (struct rwindow32 *)((u_long)npcb + TOPFRAMEOFF);
*rp = *(struct rwindow32 *)((u_long)opcb + TOPFRAMEOFF);
rp = (struct rwindow *)((u_long)npcb + TOPFRAMEOFF);
*rp = *(struct rwindow *)((u_long)opcb + TOPFRAMEOFF);
rp->rw_local[0] = (long)child_return; /* Function to call */
rp->rw_local[1] = (long)p2; /* and its argument */
npcb->pcb_pc = (long)proc_trampoline - 8;
npcb->pcb_sp = (long)rp;
npcb->pcb_sp = (long)rp - STACK_OFFSET;
#ifdef NOTDEF_DEBUG
printf("cpu_fork: Copying over trapframe: otf=%p ntf=%p sp=%p opcb=%p npcb=%p\n",
@ -352,7 +344,7 @@ cpu_set_kpc(p, pc)
void (*pc) __P((struct proc *));
{
struct pcb *pcb;
struct rwindow32 *rp;
struct rwindow *rp;
#if 0
/* Make sure our D$ is not polluted w/bad data */
@ -361,7 +353,7 @@ cpu_set_kpc(p, pc)
pcb = &p->p_addr->u_pcb;
rp = (struct rwindow32 *)((u_long)pcb + TOPFRAMEOFF);
rp = (struct rwindow *)((u_long)pcb + TOPFRAMEOFF);
rp->rw_local[0] = (long)pc; /* Function to call */
rp->rw_local[1] = (long)p; /* and its argument */
@ -382,7 +374,7 @@ cpu_set_kpc(p, pc)
* - make it run in a clear set of register windows
*/
pcb->pcb_pc = (long)proc_trampoline - 8 ;
pcb->pcb_sp = (long)rp;
pcb->pcb_sp = (long)rp - STACK_OFFSET;
}
/*