Add debugger single-stepping and fix interrupt dispatch bugs.
This commit is contained in:
eeh
parent
ede7778a1c
commit
082d2d0074
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@ -1,4 +1,4 @@
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/* $NetBSD: db_machdep.h,v 1.8 1999/11/06 20:13:50 eeh Exp $ */
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/* $NetBSD: db_machdep.h,v 1.9 2000/01/10 03:53:20 eeh Exp $ */
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/*
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* Mach Operating System
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@ -96,18 +96,39 @@ db_regs_t ddb_regs; /* register state */
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#define BKPT_SIZE (4) /* size of breakpoint inst */
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#define BKPT_SET(inst) (BKPT_INST)
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#define db_clear_single_step(regs) (void) (0)
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#define db_set_single_step(regs) (void) (0)
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#define IS_BREAKPOINT_TRAP(type, code) \
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((type) == T_BREAKPOINT || (type) == T_KGDB_EXEC)
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#define IS_WATCHPOINT_TRAP(type, code) (0)
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#define IS_WATCHPOINT_TRAP(type, code) \
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((type) ==T_PA_WATCHPT || (type) == T_VA_WATCHPT)
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#define inst_trap_return(ins) ((ins)&0)
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#define inst_return(ins) ((ins)&0)
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#define inst_call(ins) ((ins)&0)
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#define inst_load(ins) 0
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#define inst_store(ins) 0
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/*
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* Sparc cpus have no hardware single-step.
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*/
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#define SOFTWARE_SSTEP
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boolean_t db_inst_trap_return __P((int inst));
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boolean_t db_inst_return __P((int inst));
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boolean_t db_inst_call __P((int inst));
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boolean_t db_inst_branch __P((int inst));
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int db_inst_load __P((int inst));
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int db_inst_store __P((int inst));
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boolean_t db_inst_unconditional_flow_transfer __P((int inst));
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db_addr_t db_branch_taken __P((int inst, db_addr_t pc, db_regs_t *regs));
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#define inst_trap_return(ins) db_inst_trap_return(ins)
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#define inst_return(ins) db_inst_return(ins)
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#define inst_call(ins) db_inst_call(ins)
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#define inst_branch(ins) db_inst_branch(ins)
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#define inst_load(ins) db_inst_load(ins)
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#define inst_store(ins) db_inst_store(ins)
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#define inst_unconditional_flow_transfer(ins) \
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db_inst_unconditional_flow_transfer(ins)
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#define branch_taken(ins, pc, regs) \
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db_branch_taken((ins), (pc), (regs))
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/* see note in db_interface.c about reversed breakpoint addrs */
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#define next_instr_address(pc, bd) \
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((bd) ? (pc) : ddb_regs.ddb_tf.tf_npc)
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#define DB_MACHINE_COMMANDS
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@ -1,4 +1,4 @@
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/* $NetBSD: instr.h,v 1.2 1998/09/22 02:48:43 eeh Exp $ */
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/* $NetBSD: instr.h,v 1.3 2000/01/10 03:53:20 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -46,8 +46,8 @@
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/* see also Appendix F of the SPARC version 8 document */
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enum IOP { IOP_OP2, IOP_CALL, IOP_reg, IOP_mem };
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enum IOP2 { IOP2_UNIMP, IOP2_err1, IOP2_Bicc, IOP2_err3,
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IOP2_SETHI, IOP2_err5, IOP2_FBfcc, IOP2_CBccc };
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enum IOP2 { IOP2_UNIMP, IOP2_BPcc, IOP2_Bicc, IOP2_BPr,
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IOP2_SETHI, IOP2_FBPfcc, IOP2_FBfcc, IOP2_CBccc };
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enum IOP3_reg {
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IOP3_ADD, IOP3_AND, IOP3_OR, IOP3_XOR,
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IOP3_SUB, IOP3_ANDN, IOP3_ORN, IOP3_XNOR,
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@ -193,6 +193,31 @@ union instr {
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int i_disp:22; /* branch displacement */
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} i_branch;
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/* more branches: BPcc, FBPfcc */
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struct {
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u_int :2; /* 00 */
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u_int i_annul:1; /* annul bit */
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u_int i_cond:4; /* condition codes */
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u_int i_op2:3; /* opcode: {BP,FBPf}cc */
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u_int i_cc:2; /* condition code selector */
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u_int i_pred:1; /* branch prediction bit */
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int i_disp:19; /* branch displacement */
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} i_branch_p;
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/* one last branch: BPr */
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struct {
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u_int :2; /* 00 */
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u_int i_annul:1; /* annul bit */
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u_int :1; /* 0 */
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u_int i_rcond:4; /* register condition */
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u_int :3; /* 011 */
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int i_disphi:2; /* branch displacement, hi bits */
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u_int i_pred:1; /* branch prediction bit */
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u_int i_rs1:1; /* source register 1 */
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u_int i_displo:16; /* branch displacement, lo bits */
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} i_branch_pr;
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/*
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* Format 3 instructions (memory reference; arithmetic, logical,
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* shift, and other miscellaneous operations). The second-level
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@ -1,4 +1,4 @@
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/* $NetBSD: reg.h,v 1.5 1999/12/30 16:20:43 eeh Exp $ */
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/* $NetBSD: reg.h,v 1.6 2000/01/10 03:53:20 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -142,6 +142,8 @@ struct reg64 {
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* ``I'd suggest allowing 16 ... allowing an indeterminate variable
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* size would be even better''. Of course, we cannot do that; we
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* need to malloc these.
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*
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* XXXX UltraSPARC processors don't implement a floating point queue.
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*/
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#define FP_QSIZE 16
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#define ALIGNFPSTATE(f) ((struct fpstate64 *)(((long)(f))&(~BLOCK_ALIGN)))
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@ -170,14 +172,14 @@ struct fpstate32 {
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};
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/*
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* Clone fpstate into an fpreg structure to satisfy <kern/sys_process.c>
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* The actual FP registers are made accessable (c.f. ptrace(2)) through
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* a `struct fpreg'; <arch/sparc64/sparc64/process_machdep.c> relies on the
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* fact that `fpreg' is a prefix of `fpstate'.
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*/
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struct fpreg64 {
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u_int fr_regs[64]; /* our view is 64 32-bit registers */
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int64_t fr_fsr; /* %fsr */
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int fr_gsr; /* graphics state reg */
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int fr_qsize; /* actual queue depth */
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struct fp_qentry fr_queue[FP_QSIZE]; /* queue contents */
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};
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/*
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@ -186,8 +188,6 @@ struct fpreg64 {
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struct fpreg32 {
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u_int fr_regs[32]; /* our view is 32 32-bit registers */
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int fr_fsr; /* %fsr */
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int fr_qsize; /* actual queue depth */
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struct fp_qentry fr_queue[FP_QSIZE]; /* queue contents */
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};
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#if defined(__arch64__)
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@ -1,4 +1,4 @@
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/* $NetBSD: db_interface.c,v 1.25 1999/12/30 16:34:02 eeh Exp $ */
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/* $NetBSD: db_interface.c,v 1.26 2000/01/10 03:53:22 eeh Exp $ */
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/*
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* Mach Operating System
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@ -52,6 +52,7 @@
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#include <ddb/db_output.h>
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#include <ddb/db_interface.h>
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#include <machine/instr.h>
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#include <machine/cpu.h>
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#include <machine/openfirm.h>
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#include <machine/ctlreg.h>
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@ -179,13 +180,6 @@ kdb_trap(type, tf)
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default:
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printf("kernel trap %x: %s\n", type, trap_type[type & 0x1ff]);
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if (db_recover != 0) {
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#if 0
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#ifdef __arch64__
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/* For now, don't get into infinite DDB trap loop */
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printf("Faulted in DDB; going to OBP...\n");
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OF_enter();
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#endif
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#endif
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db_error("Faulted in DDB; continuing...\n");
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OF_enter();
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/*NOTREACHED*/
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@ -224,10 +218,10 @@ kdb_trap(type, tf)
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}
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#endif
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s = splhigh();
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db_active++;
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cnpollc(TRUE);
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/* Need to do spl stuff till cnpollc works */
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s = splhigh();
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tl = savetstate(ts);
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for (i=0; i<tl; i++) {
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printf("%d tt=%lx tstate=%lx tpc=%p tnpc=%p\n",
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@ -236,15 +230,15 @@ kdb_trap(type, tf)
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}
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db_trap(type, 0/*code*/);
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restoretstate(tl,ts);
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splx(s);
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cnpollc(FALSE);
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db_active--;
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splx(s);
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#if 0
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/* We will not alter the machine's running state until we get everything else working */
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*(struct frame *)tf->tf_out[6] = ddb_regs.ddb_fr;
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*tf = ddb_regs.ddb_tf;
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#endif
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*tf = ddb_regs.ddb_tf;
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trap_trace_dis = traptrace_enabled;
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return (1);
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@ -865,3 +859,235 @@ db_machine_init()
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{
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db_machine_commands_install(sparc_db_command_table);
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}
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/*
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* support for SOFTWARE_SSTEP:
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* return the next pc if the given branch is taken.
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*
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* note: in the case of conditional branches with annul,
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* this actually returns the next pc in the "not taken" path,
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* but in that case next_instr_address() will return the
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* next pc in the "taken" path. so even tho the breakpoints
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* are backwards, everything will still work, and the logic is
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* much simpler this way.
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*/
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db_addr_t
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db_branch_taken(inst, pc, regs)
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int inst;
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db_addr_t pc;
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db_regs_t *regs;
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{
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union instr insn;
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db_addr_t npc = ddb_regs.ddb_tf.tf_npc;
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insn.i_int = inst;
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/*
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* if this is not an annulled conditional branch, the next pc is "npc".
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*/
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if (insn.i_any.i_op != IOP_OP2 || insn.i_branch.i_annul != 1)
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return npc;
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switch (insn.i_op2.i_op2) {
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case IOP2_Bicc:
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case IOP2_FBfcc:
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case IOP2_BPcc:
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case IOP2_FBPfcc:
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case IOP2_CBccc:
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/* branch on some condition-code */
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switch (insn.i_branch.i_cond)
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{
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case Icc_A: /* always */
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return pc + ((inst << 10) >> 8);
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default: /* all other conditions */
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return npc + 4;
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}
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case IOP2_BPr:
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/* branch on register, always conditional */
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return npc + 4;
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default:
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/* not a branch */
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panic("branch_taken() on non-branch");
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}
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}
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boolean_t
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db_inst_branch(inst)
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int inst;
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{
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union instr insn;
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insn.i_int = inst;
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if (insn.i_any.i_op != IOP_OP2)
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return FALSE;
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switch (insn.i_op2.i_op2) {
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case IOP2_BPcc:
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case IOP2_Bicc:
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case IOP2_BPr:
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case IOP2_FBPfcc:
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case IOP2_FBfcc:
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case IOP2_CBccc:
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return TRUE;
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default:
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return FALSE;
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}
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}
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boolean_t
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db_inst_call(inst)
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int inst;
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{
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union instr insn;
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insn.i_int = inst;
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switch (insn.i_any.i_op) {
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case IOP_CALL:
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return TRUE;
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case IOP_reg:
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return (insn.i_op3.i_op3 == IOP3_JMPL) && !db_inst_return(inst);
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default:
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return FALSE;
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}
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}
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boolean_t
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db_inst_unconditional_flow_transfer(inst)
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int inst;
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{
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union instr insn;
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insn.i_int = inst;
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if (db_inst_call(inst))
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return TRUE;
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if (insn.i_any.i_op != IOP_OP2)
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return FALSE;
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switch (insn.i_op2.i_op2)
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{
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case IOP2_BPcc:
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case IOP2_Bicc:
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case IOP2_FBPfcc:
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case IOP2_FBfcc:
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case IOP2_CBccc:
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return insn.i_branch.i_cond == Icc_A;
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default:
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return FALSE;
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}
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}
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boolean_t
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db_inst_return(inst)
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int inst;
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{
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return (inst == I_JMPLri(I_G0, I_O7, 8) || /* ret */
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inst == I_JMPLri(I_G0, I_I7, 8)); /* retl */
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}
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boolean_t
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db_inst_trap_return(inst)
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int inst;
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{
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union instr insn;
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insn.i_int = inst;
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return (insn.i_any.i_op == IOP_reg &&
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insn.i_op3.i_op3 == IOP3_RETT);
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}
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int
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db_inst_load(inst)
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int inst;
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{
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union instr insn;
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insn.i_int = inst;
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if (insn.i_any.i_op != IOP_mem)
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return 0;
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switch (insn.i_op3.i_op3) {
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case IOP3_LD:
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case IOP3_LDUB:
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case IOP3_LDUH:
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case IOP3_LDD:
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case IOP3_LDSB:
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case IOP3_LDSH:
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case IOP3_LDSTUB:
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case IOP3_SWAP:
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case IOP3_LDA:
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case IOP3_LDUBA:
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case IOP3_LDUHA:
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case IOP3_LDDA:
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case IOP3_LDSBA:
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case IOP3_LDSHA:
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case IOP3_LDSTUBA:
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case IOP3_SWAPA:
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case IOP3_LDF:
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case IOP3_LDFSR:
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case IOP3_LDDF:
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case IOP3_LFC:
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case IOP3_LDCSR:
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case IOP3_LDDC:
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return 1;
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default:
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return 0;
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}
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}
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int
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db_inst_store(inst)
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int inst;
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{
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union instr insn;
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insn.i_int = inst;
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if (insn.i_any.i_op != IOP_mem)
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return 0;
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switch (insn.i_op3.i_op3) {
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case IOP3_ST:
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case IOP3_STB:
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case IOP3_STH:
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case IOP3_STD:
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case IOP3_LDSTUB:
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case IOP3_SWAP:
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case IOP3_STA:
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case IOP3_STBA:
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case IOP3_STHA:
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case IOP3_STDA:
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case IOP3_LDSTUBA:
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case IOP3_SWAPA:
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case IOP3_STF:
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case IOP3_STFSR:
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case IOP3_STDFQ:
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case IOP3_STDF:
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case IOP3_STC:
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case IOP3_STCSR:
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case IOP3_STDCQ:
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case IOP3_STDC:
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return 1;
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default:
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return 0;
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}
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.c,v 1.17 1999/11/06 20:18:50 eeh Exp $ */
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/* $NetBSD: intr.c,v 1.18 2000/01/10 03:53:21 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -105,16 +105,20 @@
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*/
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struct intrhand *intrlev[MAXINTNUM];
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void strayintr __P((const struct trapframe64 *));
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void strayintr __P((const struct trapframe64 *, int));
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int soft01intr __P((void *));
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/*
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* Stray interrupt handler. Clear it if possible.
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* If not, and if we get 10 interrupts in 10 seconds, panic.
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*/
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int ignore_stray = 1;
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int straycnt[16];
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void
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strayintr(fp)
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strayintr(fp, vectored)
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const struct trapframe64 *fp;
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int vectored;
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{
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static int straytime, nstray;
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int timesince;
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@ -122,14 +126,18 @@ strayintr(fp)
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extern int swallow_zsintrs;
|
||||
#endif
|
||||
|
||||
return;
|
||||
if (fp->tf_pil < 16)
|
||||
straycnt[(int)fp->tf_pil]++;
|
||||
|
||||
if (ignore_stray)
|
||||
return;
|
||||
|
||||
/* If we're in polled mode ignore spurious interrupts */
|
||||
if ((fp->tf_pil == PIL_SER) /* && swallow_zsintrs */) return;
|
||||
|
||||
printf("stray interrupt ipl %u pc=%lx npc=%lx pstate=%lb\n",
|
||||
printf("stray interrupt ipl %u pc=%lx npc=%lx pstate=%lb vecttored=%d\n",
|
||||
fp->tf_pil, fp->tf_pc, fp->tf_npc,
|
||||
(unsigned long)(fp->tf_tstate>>TSTATE_PSTATE_SHIFT), PSTATE_BITS);
|
||||
(unsigned long)(fp->tf_tstate>>TSTATE_PSTATE_SHIFT), PSTATE_BITS, vectored);
|
||||
timesince = time.tv_sec - straytime;
|
||||
if (timesince <= 10) {
|
||||
if (++nstray > 500)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: locore.s,v 1.48 1999/12/30 16:39:53 eeh Exp $ */
|
||||
/* $NetBSD: locore.s,v 1.49 2000/01/10 03:53:21 eeh Exp $ */
|
||||
/*
|
||||
* Copyright (c) 1996-1999 Eduardo Horvath
|
||||
* Copyright (c) 1996 Paul Kranenburg
|
||||
|
|
@ -130,6 +130,7 @@
|
|||
#define LDPTRA ldxa
|
||||
#define STPTR stx
|
||||
#define STPTRA stxa
|
||||
#define CASPTR casxa
|
||||
/* Now something to calculate the stack bias */
|
||||
#define STKB BIAS
|
||||
#else
|
||||
|
|
@ -141,6 +142,7 @@
|
|||
#define LDPTRA lduwa
|
||||
#define STPTR stw
|
||||
#define STPTRA stwa
|
||||
#define CASPTR casa
|
||||
#define STKB 0
|
||||
#endif
|
||||
|
||||
|
|
@ -3768,11 +3770,18 @@ setup_sparcintr:
|
|||
mov 8, %g7 ! Number of slots to search
|
||||
sll %g6, PTRSHFT+3, %g2 ! Find start of table for this IPL
|
||||
add %g1, %g2, %g1
|
||||
LDPTR [%g1], %g2 ! Get slot
|
||||
dec %g7
|
||||
brz,a,pt %g2, 4f ! Available?
|
||||
STPTR %g5, [%g1] ! Put intrhand in slot
|
||||
brgz,pt %g7, 1b
|
||||
2:
|
||||
#if 1
|
||||
mov %g5, %g2
|
||||
CASPTR [%g1] ASI_N, %g0, %g2 ! Try a slot -- MPU safe
|
||||
brz,pt %g2, 4f ! Available?
|
||||
#else
|
||||
LDPTR [%g1], %g2 ! Try a slog
|
||||
brz,a %g2, 4f ! Available?
|
||||
STPTR %g5, [%g1] ! Grab it
|
||||
#endif
|
||||
dec %g7
|
||||
brgz,pt %g7, 2b
|
||||
inc PTRSZ, %g1 ! Next slot
|
||||
|
||||
!! If we get here we have a problem.
|
||||
|
|
@ -3995,10 +4004,17 @@ _C_LABEL(sparc_interrupt):
|
|||
movrz %o0, %o2, %o0 ! arg = (arg == 0) ? arg : tf
|
||||
brz,pt %o0, intrcmplt ! Done?
|
||||
nop
|
||||
call _C_LABEL(strayintr) ! strayintr(&intrframe)
|
||||
mov 1, %o1
|
||||
call _C_LABEL(strayintr) ! strayintr(&intrframe, 1)
|
||||
add %sp, CC64FSZ + STKB, %o0
|
||||
ba,a,pt %icc, intrcmplt ! done
|
||||
2:
|
||||
#endif
|
||||
#ifdef TRAPSTATS
|
||||
set _C_LABEL(intrpoll), %l4
|
||||
ld [%l4], %o0
|
||||
inc %o0 ! Increment non-vectored interrupts.
|
||||
st %o0, [%l4]
|
||||
#endif
|
||||
set _C_LABEL(intrhand), %l4 ! %l4 = intrhand[intlev];
|
||||
LDPTR [%l4 + %l3], %l4
|
||||
|
|
@ -4073,21 +4089,23 @@ _C_LABEL(sparc_interrupt):
|
|||
clr %l3 ! Make sure we don't have a valid pointer
|
||||
brnz,pn %l5, intrcmplt ! if (handled) break
|
||||
nop
|
||||
! call _C_LABEL(strayintr) ! strayintr(&intrframe)
|
||||
clr %o1
|
||||
! call _C_LABEL(strayintr) ! strayintr(&intrframe, 0)
|
||||
add %sp, CC64FSZ + STKB, %o0
|
||||
/* all done: restore registers and go return */
|
||||
#else
|
||||
brz,a,pn %o0, 2f
|
||||
add %sp, CC64FSZ + STKB, %o0
|
||||
2: jmpl %o1, %o7 ! handled = (*ih->ih_fun)(...)
|
||||
LDPTR [%l4 + IH_CLR], %l3
|
||||
add %sp, CC64FSZ + STKB, %o2
|
||||
jmpl %o1, %o7 ! handled = (*ih->ih_fun)(...)
|
||||
movrz %o0, %o2, %o0
|
||||
LDPTR [%l4 + IH_CLR], %l3
|
||||
brnz,a,pt %l3, 5f ! Clear intr?
|
||||
stx %g0, [%l3] ! Yes
|
||||
5: brnz,pn %o0, intrcmplt ! if (handled) break
|
||||
LDPTR [%l4 + IH_NEXT], %l4 ! and ih = ih->ih_next
|
||||
3: brnz,pt %l4, 1b ! while (ih)
|
||||
clr %l3 ! Make sure we don't have a valid pointer
|
||||
call _C_LABEL(strayintr) ! strayintr(&intrframe)
|
||||
clr %o1
|
||||
call _C_LABEL(strayintr) ! strayintr(&intrframe, 0)
|
||||
add %sp, CC64FSZ + STKB, %o0
|
||||
/* all done: restore registers and go return */
|
||||
#endif
|
||||
|
|
@ -9202,7 +9220,7 @@ Lbzero_block:
|
|||
#ifdef DEBUG
|
||||
LDPTR [%l1 + %lo(_C_LABEL(fpproc))], %l7
|
||||
cmp %l7, %l5
|
||||
tnz 1 ! fpproc has changed!
|
||||
! tnz 1 ! fpproc has changed!
|
||||
LDPTR [%l5 + P_FPSTATE], %l7
|
||||
cmp %l7, %l0
|
||||
tnz 1 ! fpstate has changed!
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: process_machdep.c,v 1.8 1999/12/30 16:42:10 eeh Exp $ */
|
||||
/* $NetBSD: process_machdep.c,v 1.9 2000/01/10 03:53:22 eeh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1993 The Regents of the University of California.
|
||||
|
|
@ -192,10 +192,6 @@ struct fpreg *regs;
|
|||
statep = p->p_md.md_fpstate;
|
||||
for (i=0; i<32; i++)
|
||||
regp->fr_regs[i] = statep->fs_regs[i];
|
||||
regp->fr_fsr = statep->fs_fsr;
|
||||
regp->fr_qsize = statep->fs_qsize;
|
||||
for (i=0; i<statep->fs_qsize; i++)
|
||||
regp->fr_queue[i] = statep->fs_queue[i];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -226,9 +222,6 @@ struct fpreg *regs;
|
|||
for (i=0; i<32; i++)
|
||||
statep->fs_regs[i] = regp->fr_regs[i];
|
||||
statep->fs_fsr = regp->fr_fsr;
|
||||
statep->fs_qsize = regp->fr_qsize;
|
||||
for (i=0; i<regp->fr_qsize; i++)
|
||||
statep->fs_queue[i] = regp->fr_queue[i];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: trap.c,v 1.34 1999/12/30 16:57:27 eeh Exp $ */
|
||||
/* $NetBSD: trap.c,v 1.35 2000/01/10 03:53:22 eeh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996
|
||||
|
|
@ -124,6 +124,7 @@ int uintrcnt = 0;
|
|||
int kiveccnt = 0;
|
||||
int kintrcnt = 0;
|
||||
int intristk = 0; /* interrupts when already on intrstack */
|
||||
int intrpoll = 0; /* interrupts not using vector lists */
|
||||
int wfill = 0;
|
||||
int kwfill = 0;
|
||||
int wspill = 0;
|
||||
|
|
@ -502,6 +503,7 @@ trap(type, tstate, pc, tf)
|
|||
printf("trap: tpc %p == tnpc %p\n", tf->tf_pc, tf->tf_npc);
|
||||
Debugger();
|
||||
}
|
||||
#if 0
|
||||
{
|
||||
/* Check to make sure we're on the normal stack */
|
||||
int* sp;
|
||||
|
|
@ -515,6 +517,7 @@ trap(type, tstate, pc, tf)
|
|||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef DEBUG
|
||||
|
|
@ -558,7 +561,7 @@ trap(type, tstate, pc, tf)
|
|||
if (type == T_BREAKPOINT) {
|
||||
write_all_windows();
|
||||
if (kdb_trap(type, tf)) {
|
||||
ADVANCE;
|
||||
/* ADVANCE; */
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -1981,7 +1984,7 @@ syscall(code, tf, pc)
|
|||
for (j=0; j<i; j++)
|
||||
temp[j] = args.i[j];
|
||||
ktrsyscall(p->p_tracep, code,
|
||||
callp->sy_argsize, (register_t *)temp);
|
||||
i * sizeof(register_t), (register_t *)temp);
|
||||
#else
|
||||
ktrsyscall(p->p_tracep, code,
|
||||
callp->sy_argsize, (register_t *)args.i);
|
||||
|
|
|
|||
Loading…
Reference in New Issue