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1385 Commits

Author SHA1 Message Date
lukem
0635de35a3 Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more. 2002-11-26 23:30:07 +00:00
simonb
12c35ee2d2 New generic way-aware MIPS32/64 range-index cache functions with proper 
handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.

Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.
 2002-11-24 07:41:29 +00:00
simonb
3a72aadc2b Add the VI bit in config 0. 2002-11-24 07:28:42 +00:00
simonb
3682edd3d4 Move the curpcb and segbase extern decls to cpu.h to better group together 
what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.
 2002-11-24 07:26:04 +00:00
cgd
8935916d0a initial support for mac features in new chip revs 2002-11-19 01:44:04 +00:00
simonb
5e3d4a224c Add cache_r4k_op_8lines_{16,32} macros to perform cache ops on 8 
consecutive lines.
 2002-11-17 06:40:43 +00:00
simonb
aa5595f691 Fix typo in the address of the Au1500 MAC1 enable register; 2nd MAC works 
on the Au1500 cpu now.
 2002-11-17 04:57:34 +00:00
simonb
ba1c8ffa9d Remove reference to mips_int5_evcnt from here; that is port-specific, 
not arch-specific.
 2002-11-17 04:56:57 +00:00
manu
d584ed9598 Add a realcode argument to trace_enter and ktrsyscall. realcode is the 
original system call number, which can be negative for a Mach trap.
We cannot just replace code by realcode, because ktrsyscall uses it as
an index in the system call table, thus crashing the kernel when the
value is negative.
 2002-11-15 20:06:00 +00:00
simonb
5bdb1a36ce Add a hack to mipsNN_pdcache_wbinv_range_index_32_4way() so that we 
use the index ops at a offset of the page size as well, controlled by
an MIPS64_SB1 check.  The SB1 D-cache way size is physically indexed
and twice as big as the page size (4k), so we weren't flushing all the
addresses we needed too.

XXX: This is kinda gross; will be cleaned up and made more generic soon.
There are still other SB1-specific issues to be cleaned up too...
 2002-11-15 01:23:17 +00:00
simonb
181d7f08c9 Use COP0_HAZARD_FPUENABLE instead of a hard-coded 4 NOPs when enabling 
the FPU.
 2002-11-15 01:16:18 +00:00
simonb
2aabe4d4e2 Define COP0_HAZARD_FPUENABLE as four nops. 
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.
 2002-11-15 01:15:11 +00:00
simonb
383afcb5b6 Declare some CP0 hazards for the SB1 core. 2002-11-15 01:09:20 +00:00
simonb
28a1083dd2 Put the MIPS64_SB1 option in opt_cputype.h. 2002-11-15 01:02:49 +00:00
simonb
3d416825dc White space nits. 2002-11-15 00:58:32 +00:00
nisimura
abad61e77f Remove o32 stack layout exposure form cpu_fork(). 
Tested on R4000 and R3000.
 2002-11-12 14:00:41 +00:00
simonb
96c9d84cda Add support for the ST M41T81 RTC found on pass 2 swarm boards. 
XXX: Much of this should live in arch/sbmips instead of arch/mips/sibyte.
XXX: These should be replaced with MI SMBus drivers one day.
 2002-11-12 01:22:25 +00:00
he
aba5de5e41 Remove a PARANOIADIAG check which is a bit too paranoid. This one 
would now trigger whenever a previously used "cached" uarea was reused.

Reviewed by thorpej and chs.
 2002-11-11 22:30:15 +00:00
simonb
396f36cc12 Fix a typo in the on-board device selection machinery (which I thought 
I'd committed long ago).
 2002-11-11 16:39:18 +00:00
simonb
2e98091daf Make sure we use index ops (instead of hit ops) in the range index 
functions.
Fix typos in the cache_r4k_op_32_4way_load_off macro.

Both problems reported by Chris Demetriou.
 2002-11-10 11:11:39 +00:00
simonb
b8eff8f9aa Adapt for the ioctl ERESTART/EPASSTHROUGH changes. 
Make sure we don't tsleep() at splhigh/splserial.
 2002-11-10 11:06:11 +00:00
simonb
6fb837941b Remove some copyright notices that don't apply to this code. 2002-11-10 11:01:15 +00:00
nisimura
983202f1ed Change pmap_kenter_pa/pmap_kremove pair back to pmap_enter/pmap_remove 
in fear of the case choosen kva results in occupying inconsistent
distinctive cache lines of uva.
 2002-11-10 05:29:18 +00:00
nisimura
2a312dd17f Use pmap_enter_pa and pmap_kremove for vmapbuf/vunmapbuf, respectively. 
Have variable names renamed for the logic clarity.
 2002-11-10 02:27:50 +00:00
thorpej
84ccc9c46e Build with kernel with -msoft-float. 2002-11-09 20:34:26 +00:00
thorpej
ff114c4a59 Fix signed/unsigned comparison warnings. 2002-11-09 20:06:07 +00:00
thorpej
21ca5cbcc7 Make md_ss_addr a vaddr_t. 2002-11-09 20:05:57 +00:00
thorpej
800f626770 Fix signed/unsigned comparison warnings. 2002-11-09 20:00:20 +00:00
thorpej
0c2979d1c8 Fix signed/unsigned comparison warnings. 2002-11-09 19:35:52 +00:00
thorpej
4d7f6969a5 Make cache size/mask variables unsigned. 2002-11-09 19:34:39 +00:00
thorpej
73f78d5e61 Fix signed/unsigned comparison warnings. 2002-11-09 18:52:20 +00:00
thorpej
3689b18f89 * Add -mno-abicalls to AFLAGS. 
* GCC 3.3's traditional preprocessor functions properly now, so we
  no longer need to special-case it.
 2002-11-09 18:18:22 +00:00
thorpej
a99bec6b60 Nuke the CROSSDIR stuff. 2002-11-09 18:12:09 +00:00
nisimura
94df053502 Nuke "mips_reg_t" exposures from here. "mips_reg_t" will be 
corrected-back with "register_t" by completing the implementations
of N32 and LP64 environment.
 2002-11-09 10:59:52 +00:00
thorpej
e935239e3c No need to pass -mno-half-pic; NetBSD's compiler does not generate 
half-pic references.
 2002-11-09 07:31:08 +00:00
simonb
31fcce3c41 Include <sys/device.h> so this compiles again. 2002-11-09 04:13:03 +00:00
nisimura
8d6e18f90d - Make monolistic files into smaller manageable pieces, resulting 
three new files;
    sig_machdep.c (from mips_machdep.c)
    copy.S and sigcode.S (from locore.S)
- Nuke the local use of struct sigframe, which is now identical to
struct sigcontext, from sendsig() as the consequence of new signal
trampoline.
 2002-11-09 02:02:31 +00:00
cgd
48164df6b2 handle different SOC types and features a little better 2002-11-08 19:53:29 +00:00
cgd
f4a3e5f997 fix long-standing pasto in DMA config1 register address setting 2002-11-08 19:40:05 +00:00
cgd
49c87f0804 update to latest CFE API code 2002-11-08 19:35:38 +00:00
cgd
99a582aab5 Calculate end virtual address for cache ops before chopping low bits 
(line mask) off of starting address.  Otherwise, could miss the final
line that the ops should have been operating on.  Reviewed by simonb.
 2002-11-08 07:35:20 +00:00
cgd
1f2efd0d77 update SiByte includes from their master versions. (main differences: 
bug fixes, conditionalization of different chip support, new features.)
(Reviewed and tested by simonb.)
 2002-11-08 07:32:40 +00:00
simonb
0b3b87b6c8 Whitespace nit. 2002-11-08 04:13:13 +00:00
simonb
28cb103184 Note a new MIPS64_SB1 option that should be included in opt_cputype.h 
one day.
 2002-11-08 00:50:49 +00:00
simonb
220b08b128 Sprinkle a little more COP0_SYNC (in an unused function...). 2002-11-08 00:49:32 +00:00
cgd
a13b227af2 fix errors in calculating the ending VA to use in r4k_icache_sync_range_16 
and r5k_icache_sync_range_32.  (reviewed by thorpej.)
 2002-11-07 23:03:21 +00:00
cgd
d6cd994028 don't under COP0_SYNC. (approved by simonb.) 2002-11-07 05:39:48 +00:00
thorpej
0bc2a57e26 Use named indices for RA, SR, MULLO, MULHI, and EPC in the 
trapframe.
 2002-11-04 20:02:09 +00:00
thorpej
fab408c3af Use named indices for trapframe slots, and use the TA0-TA3 names 
where appropriate.
 2002-11-04 19:51:05 +00:00
thorpej
c8fbf16072 Define named constants for the trapframe register idices (they 
are different from the normal register numbers).  Use these names
in genassym.cf.  (Wow, how ever did that test kernel boot before...)
 2002-11-04 19:40:04 +00:00