Fix regress/lib/libc/ieeefp/except for MIPS. Newer FPE handling code
did not generate SIGFPE, but always SIGILL. Add this back to the
assembly code. The QED 5231 requests the kernel emulates some of
the conditions that generate an SIGFPE, but when the emulation code
did a ctc1 to fsr with an exception the kernel got a FPE in kernel mode.
Fix this by saving the fp regs earlier, then saving the new FSR in
the context. This allows the FSR value to be seen by the SIGFPE
handler.
Add fp emulation for 8 mips2 fpu instructions to handle exceptions
(round.w.fmt, trunc.w.fmt, ceil.w.fmt, floor.w.fmt). This lets
perl5 run when compiled -mips2.
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID. MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump. Change for MIPS3 is
to be done.
uvm_page_init() has completed, add a boolean uvm.page_init_done,
and test against that. Use this same boolean (rather than
pmap_initialized) in pmap_growkernel() to determine if we are
being called via uvm_page_init() to grow the kernel address space.
This fixes a problem on some i386 configurations where pmap_init()
itself was needing to have the kernel page table grown, and since
pmap_initialized was not yet set to TRUE, pmap_growkernel() was
choosing the wrong code path.
Fix tested by Havard Eidnes.
half-baked and resulted in one superfluous ASID bump if new pmaps
are created when pmap_asid_generation > 0. Need to initialize pmap
fields correctly.
Yet, this possibly might not be the perfect solution. If one
process bumped pmap_asid_generation _after_ a new pmap was created
and initialized with then-current pmap_asid_generation value. In
that case, the new pmap would have another (superfluous) ASID bump
when 2nd (not 1st) CPU tick is assigned. I'm not sure if this case
would happen.
Have pmap_max_asid variable to hold the maximum number of ASID
(TLBpid) supported by processor anticipating the possible runtime
cost of ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS).
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.
- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.
was used for debugg'n purposes which only make senses on particular
hardware configurations and has never been intended to extend pagesize
of NetBSD/mips.
* Remove the casts to vaddr_t from the round_page() and trunc_page() macros to
make them type-generic, which is necessary i.e. to operate on file offsets
without truncating them.
* In due course, cast pointer arguments to these macros to an appropriate
integral type (paddr_t, vaddr_t).
Originally done by Chuck Silvers, updated by myself.
nisimura