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cc2c493bc4
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571 Commits

Author SHA1 Message Date
thorpej
cc2c493bc4 Use PAGE_SIZE rather than NBPG. 2003-04-02 07:35:54 +00:00
rafal
33fcc94c6f Add support for R5k secondary caches, from code Chris Sekiya sent me a long 
time ago, with small tweaks by me.  Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.
 2003-03-08 04:43:24 +00:00
tshiozak
31e2cbf0b5 add some ISO C 1995 I18N functions and types: 
btowc, wctrans, towctrans, wcscoll, wcsxfrm, wctype_t and wctrans_t.
 2003-03-02 22:18:11 +00:00
simonb
8883b06039 No need to protect headers with #ifdef _KERNEL if they're never installed 
in /usr/include.
 2003-02-17 11:35:01 +00:00
cgd
8a6b8c3b72 Update to consistently use Broadcom GPL-compatible license on all SiByte code. 2003-02-07 17:38:48 +00:00
nakayama
e3e4805068 Replace machine/rnd.h with more appropriate name to share it 
with cycle counter based microtime in kern/kern_microtime.c.
 2003-02-05 13:57:50 +00:00
kent
cd7d9faeaf Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it. 2003-01-28 01:07:51 +00:00
rafal
c406903ac2 LWP'ify the svr4_mcontext stuff. 2003-01-22 04:32:17 +00:00
thorpej
706b88727b Fix typo in sigcontext conversion macros. From Christopher SEKIYA. 2003-01-20 16:28:13 +00:00
tsutsui
aa4186745b Add '#define' for _MCONTEXT_TO_SIGCONTEXT(). 2003-01-18 13:03:17 +00:00
thorpej
a50e3bc1cb Merge the nathanw_sa branch. 2003-01-17 22:58:53 +00:00
rafal
0cc0813590 Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the 
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k.  If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.
 2003-01-10 03:22:48 +00:00
simonb
2c1a832f25 Add support for caches where the data cache is fully coherent, and 
either requires flushing either only when the I cache ops are used
or not at all.  Currently only used by MIPS32/MIPS64 cache code.
 2002-12-17 12:04:29 +00:00
thorpej
e8cc3884de Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is. 2002-12-10 17:14:02 +00:00
thorpej
78ea2dd367 Use __LDPGSZ (which must be == USRTEXT) as the text address for a.out 
executables, and eliminate the USRTEXT constant, which was only used
by the a.out exec code.
 2002-12-10 05:14:24 +00:00
simonb
699bf96665 Drop the _KERNEL test; these functions are needed for SMP and other ports 
don't bother with a _KERNEL check.
 2002-12-05 02:56:51 +00:00
tsutsui
d03ac2a783 Fix botch in previous. This is pcb.h, not reg.h. 2002-11-30 22:50:01 +00:00
simonb
fdd1e3b715 Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests. 2002-11-30 01:52:31 +00:00
simonb
d644dd9c43 Add multiple-inclusion protection. 2002-11-30 01:49:18 +00:00
lukem
0635de35a3 Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more. 2002-11-26 23:30:07 +00:00
simonb
12c35ee2d2 New generic way-aware MIPS32/64 range-index cache functions with proper 
handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.

Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.
 2002-11-24 07:41:29 +00:00
simonb
3a72aadc2b Add the VI bit in config 0. 2002-11-24 07:28:42 +00:00
simonb
3682edd3d4 Move the curpcb and segbase extern decls to cpu.h to better group together 
what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.
 2002-11-24 07:26:04 +00:00
simonb
5e3d4a224c Add cache_r4k_op_8lines_{16,32} macros to perform cache ops on 8 
consecutive lines.
 2002-11-17 06:40:43 +00:00
simonb
2aabe4d4e2 Define COP0_HAZARD_FPUENABLE as four nops. 
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.
 2002-11-15 01:15:11 +00:00
simonb
383afcb5b6 Declare some CP0 hazards for the SB1 core. 2002-11-15 01:09:20 +00:00
simonb
3d416825dc White space nits. 2002-11-15 00:58:32 +00:00
thorpej
21ca5cbcc7 Make md_ss_addr a vaddr_t. 2002-11-09 20:05:57 +00:00
thorpej
4d7f6969a5 Make cache size/mask variables unsigned. 2002-11-09 19:34:39 +00:00
thorpej
0bc2a57e26 Use named indices for RA, SR, MULLO, MULHI, and EPC in the 
trapframe.
 2002-11-04 20:02:09 +00:00
thorpej
c8fbf16072 Define named constants for the trapframe register idices (they 
are different from the normal register numbers).  Use these names
in genassym.cf.  (Wow, how ever did that test kernel boot before...)
 2002-11-04 19:40:04 +00:00
thorpej
65fdfe7d64 Add TA0-TA3 register indices. 2002-11-04 04:24:48 +00:00
thorpej
aa2b9a65fc Add SGI-compatible ta0-ta3 register names. These allow one to write 
asm code which can be built easily in old-ABI and new-ABI environemnts.

In old-ABI, they map to t4-t7, and in new-ABI, they map to a4-a7.  This
means that t0-t3,ta0-ta3,t8,t9 are available in both ABIs.

Because ta0-ta3 overlap with arg regs (albeit arg slots which are usually
unused), they should be used only if t0-t3,t8,t9 isn't enough.
 2002-11-04 03:38:32 +00:00
thorpej
15d3b348c9 Add LP64 limits. 2002-11-03 20:02:39 +00:00
thorpej
9f9d6d33f4 Add LP64 types, limits, formats. 2002-11-03 19:55:23 +00:00
thorpej
f8dceffac5 Add LP64 macros. 2002-11-03 19:24:55 +00:00
thorpej
c88320f8d7 Add LP64 types. 2002-11-03 19:22:00 +00:00
thorpej
16084f1873 Add _LP64 types. 2002-11-03 17:43:07 +00:00
thorpej
c5adb2880e In the _MIPS_PADDR_T_64BIT case, only use "unsigned long long" if _LP64 
is not defined.
 2002-11-03 17:35:32 +00:00
nisimura
ad5b782866 Retire __HAVE_MD_RUNQUEUE from MD types.h and remove 
setrunqueue/remrunqueue from locore.S.  C codes are
compiled a bit shorter and provide better DIAGNOSTICs.
 2002-11-03 13:47:34 +00:00
nisimura
5a63303fc1 Add two PRiD values. 
- 0x55 for NEC Vr5500.  ISA might be MIPS64.
- 0x38 for Toshiba TX79.  This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space.  Any of pointer related
registers have 32bit.
 2002-11-03 13:16:11 +00:00
thorpej
3d93c95dc8 Make register_t == long long for N32, and == long for everthing else. 
Use register_t in label_t.
 2002-11-02 02:45:22 +00:00
thorpej
3517ae5f6a Define N32/N64 register usage. 2002-11-02 02:00:17 +00:00
chs
b79663cf62 eliminate PT_ENTRY_NULL in favor of plain old NULL. 2002-10-14 05:11:21 +00:00
simonb
63096043b3 Use "#define\t" instead of "#define ". 2002-09-22 08:30:56 +00:00
chs
c081614ea2 it really helps to get the stub right before cutting + pasting it 27 times. 
alas, I did not.  doh.
 2002-09-22 07:53:39 +00:00
chs
55e1f79335 add pmap_remove_all() hook (empty on most platforms so far). 2002-09-22 07:17:08 +00:00
gmcgarry
dca80f08fd Add __HAVE_MD_RUNQUEUE flag for MD code to override MI run queue primitives. 2002-09-22 04:11:32 +00:00
gmcgarry
a2e5c0f036 Bring down from nathanw_sa branch. 2002-09-16 07:00:43 +00:00
gmcgarry
1a8058823b RAS support for MIPS. Tested on R3000. 2002-08-28 08:34:06 +00:00