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33434 Commits

Author SHA1 Message Date
thorpej
950670fa77 Fix a typo. 2002-10-08 17:39:17 +00:00
scw
16c5b1b5a8 - g/c an accidentally committed debug hack 
- use sh5_trunc_page() instead of masking with SH5_PTEH_EPN mask
  where appropriate. The latter is not safe in 64-bit mode.
 2002-10-08 16:01:07 +00:00
scw
ae8f4bf362 Fix tyop. 2002-10-08 15:59:32 +00:00
scw
71de7dd5e6 - Tweak the kernel's start address for 64-bit kernels. 
- Use a local hacked-up-for-sh64 dbsym(8).
 2002-10-08 15:59:11 +00:00
scw
f30b5f8e54 Cast to caddr_t via intptr_t. 2002-10-08 15:56:13 +00:00
scw
2729bcfb69 - Use intrnames[] instead of rolling our own. 
- Update intrcnt[level] in sh5_intr_dispatch().
 2002-10-08 15:55:07 +00:00
scw
e0248b775a intrnames has moved to board-specific code. 2002-10-08 15:53:04 +00:00
scw
f07358cb66 - Make sure not to sign-extend the PA of KSEG0, particulary in 64-bit mode, 
- Moved intrnames/eintrnames here, since they're pretty much board-specific.
 2002-10-08 15:52:02 +00:00
scw
a5719508fe Get DB_ELFSIZE for 64-bit kernels. 2002-10-08 15:49:26 +00:00
augustss
b45db92e85 Add ubsa attachment. 2002-10-08 13:09:05 +00:00
jdolecek
e72c35e47e tag the cdevsw as tty with D_TTY 2002-10-08 08:57:52 +00:00
bjh21
8bd749851d Special locking primitives for use in Hydra kernels. These include a cache 
invalidation after every lock to ensure that changes made by other CPUs are
visible.  This has nasty performance implications, but it does allow my
Hydrated Risc PC to run printf() on all its CPUs at once without corrupting
the message buffer.
 2002-10-07 23:23:53 +00:00
bjh21
5a9767e3de Minor tidy-up, mostly to improve readability. The SWP instruction is now 
in its own little inline function, and this allows us to get rid of all the
automatic variables elsewhere.  This subtly changes the semantics of
__cpu_simple_lock() such that the loop ends up one instruction longer, but
I'm not sure that's a particularly bad thing.
 2002-10-07 23:19:49 +00:00
jdolecek
4140408d7e g/c empty apmpoll(), use nopoll() instead 2002-10-07 21:32:10 +00:00
martin
e91fcc8060 Remove obsolete and unused file (there still is ../include/asm.h, which is 
shared with sparc)
 2002-10-07 20:01:46 +00:00
scw
2657f0ac37 Ensure the temporary mapping for /dev/mem is flagged as unmanaged. 2002-10-07 15:05:58 +00:00
scw
88e1242876 Lots of small changes, some functional, some cosmetic. 
The main bug fixes are:
 - pmap_pvo_remove() must calculate the kipt index if the idx param is -1.

 - Don't assume that if a pmap's ASID generation is out of date that we
   can skip purging/invalidating the cache for any of its constituent
   mappings. At this time, the ASID generation just indicates that none
   of its mappings are in the TLB. However, there may still be some valid
   cache entries for them.

Finally, the subtle NFS and buffer cache corruption problems disappear.
 2002-10-07 15:02:07 +00:00
martin
bbdf4c9e6d Remove unused file, superseeded by syssrc/dev/sun/fb.c. 2002-10-07 14:57:53 +00:00
scw
199e165526 Add a cacheop for purging/invalidating the whole operand/insn caches. 
This is currently not used (actually, it was used locally for a short time
while tracking down a pmap bug), but is here in case it's needed later.
 2002-10-07 14:48:14 +00:00
scw
9bbc15e3a1 Add a SH5_PTEL_CACHEABLE() macro which evaulates TRUE if the specified 
PTEL describes a cacheable mapping.
 2002-10-07 14:42:31 +00:00
martin
44a2c6cb31 All sparc64 CPUs do __HAVE_CPU_COUNTER (aka %tick). 2002-10-07 13:26:56 +00:00
scw
c3ed42912c Simplify the scsibus attatchment as pointed out by Simon Burge. 2002-10-07 08:20:07 +00:00
fvdl
570d69db6e Remove ifdef LOCKDEBUG, this file is only compiled when it is defined. 2002-10-07 07:58:26 +00:00
fvdl
288a0ddc5d lock_machdep.c only depends on LOCKDEBUG, in which case it's also 
needed in the non-MP case (since pmap.c now calls __cpu_simple_lock
directly)
 2002-10-07 07:54:31 +00:00
fvdl
fb2f78f8b5 Put DDB stubs inside ifdef DDB, PR 18563. 2002-10-07 07:11:59 +00:00
thorpej
7bbf61fd89 Add support for restartable atomic sequences on 26-bit ARM. Compile 
tested only.

Now that all ARM systems have RAS, move __HAVE_RAS from arm/arm32/types.h
to arm/types.h.
 2002-10-07 02:48:38 +00:00
fvdl
d1cbc91464 Remove ci_lapic_ints from struct cpu_info again, it isn't needed anymore. 2002-10-06 20:40:27 +00:00
fvdl
3319c2f2dc Add cpu_id field to mp_intr_map structure. Declare mp_nintr. 2002-10-06 20:39:33 +00:00
fvdl
f493e906e6 Handle per-CPU local apic redir entries a little better. My previous 
solution relied on CPU entries coming first in the table, which
isn't guaranteed. Instead, export mp_intrs to lapic.c, and scan
it for entries that match the current CPU in lapic_set_lvt().

Also, do not try to up intr_cnt by the number of IO APICs or CPUs in
the case of MPS_ALL_APICS; it isn't needed, and it also relies on
CPU and IO APIC entries being earlier in the table.
 2002-10-06 20:38:37 +00:00
fvdl
be146319cd Keep size of struct cpu_info independent of DIAGNOSTIC/LOCKDEBUG 
(was done in rev. 1.81, got lost in the MP merge).
 2002-10-06 18:31:21 +00:00
bjh21
c62984115f Turn curcpu() into a macro. 
Rename cpu_info_array to cpu_info and make it public.
Add CPU_FOREACH() and friends.
 2002-10-06 18:28:48 +00:00
thorpej
70cc64f942 Make this compile with strict prototypes. 2002-10-06 17:13:58 +00:00
fvdl
f8a5d4e00c Handle per-CPU local APIC redir tables in the MP BIOS. 2002-10-06 14:28:55 +00:00
fvdl
85eaacd06e Add per-CPU local apic redir table (2 pointers). 2002-10-06 14:28:17 +00:00
bjh21
1f17ac8831 Remove footbridge and isadma glue -- these no longer seem to be necessary. 2002-10-06 13:05:39 +00:00
bjh21
682415134d Call cpu_setup() and cpu_attach() from cpu_hydra_hatch(). 
Also simplify cpu_hydra_attach() somewhat.
 2002-10-06 12:37:59 +00:00
fvdl
a2e301721c cpu_swapin now exists, so remove the empty define. 2002-10-06 12:37:35 +00:00
fvdl
2560973204 If NOREDZONE is defined, keep UPAGES at 2 as before. 2002-10-06 12:37:12 +00:00
fvdl
5e33ec48d8 Define NOREDZONE and use it in the *_TINY config files to save a page 
per process.
 2002-10-06 12:36:16 +00:00
fvdl
14c70e4627 Put an unmapped page below the kernel stack (and above struct user) to 
catch kernel stack overflows. This bumps UPAGES from 2 to 4 (one unmapped),
because struct user take 1 page then there's the unmapped page, and
then the 2 pages for the kernel stack. If the NOREDZONE option is
set, UPAGES is 2 as before, and no unmapped page is used.
 2002-10-06 12:35:16 +00:00
bjh21
c775c3e73c Give each CPU a struct cpu_info, and have curcpu() return the right one. 
Also have cpu_boot_secondary_processors() un-halt all the slave CPUs, and
have them do something visible when that happens.
 2002-10-06 11:34:12 +00:00
bjh21
8e25492f64 Make cpu_number() work. 2002-10-06 10:21:50 +00:00
bjh21
f68de9a752 Use HYDRA_ID_SLAVE_MASK rather than 3. 
No need for an infinite loop after we jump out of hydra_hatchcode.
 2002-10-06 10:21:10 +00:00
provos
d1c3210192 regen from GENERIC.in 2002-10-06 03:00:02 +00:00
provos
fbc128def8 add SYSTRACE here; pointed out by lukem 2002-10-06 02:58:21 +00:00
tsutsui
a7933969a6 Sync with GENERIC. (systrace and other misc options) 2002-10-06 02:50:28 +00:00
tsutsui
a9ca52263a Sync with GENERIC: 
- Add options SYSTRACE
- Add (commented out) options for semaphores
 2002-10-06 02:31:38 +00:00
provos
2f7a0aaac8 add SYSTRACE; approved perry. 2002-10-06 02:11:54 +00:00
bjh21
bb6b27b143 Second phase of Hydra attachment: All CPUs are now set up sufficiently that 
they can call printf(), which they do before halting.
 2002-10-05 23:30:03 +00:00
bjh21
389f612a10 Remove spurious comment. 2002-10-05 23:26:48 +00:00
chs
993948e989 count executable image pages as executable for vm-usage purposes. 
also, always do the VTEXT vs. v_writecount mutual exclusion
(which we previously skipped if the text or data segment was empty).
 2002-10-05 22:34:02 +00:00
fvdl
9110a093d8 Do rendezvous for TLB shootdown IPI. The sender sets a bitmask 
of all CPUs it wants entries shot down on, and waits until it
clears. pmap_tlb_doshootdown clears the bit of the current CPU
in this mask.

Also, change simple_lock -> __cpu_simple_lock in IPI path.
 2002-10-05 21:30:42 +00:00
fvdl
c55b2f6fa9 Define XINTR_TSS 2002-10-05 21:29:01 +00:00
fvdl
2153e9d81a Adjust callers to setgate() to match new extra parameter. 2002-10-05 21:28:34 +00:00
fvdl
1176155ea2 Protect against multiple inclusion. 2002-10-05 21:27:52 +00:00
fvdl
724f151d44 Define some masks to be able to pass information about a trap 
being a TSS trap down to things like DDB.

XXX a bit of a hack.
 2002-10-05 21:27:35 +00:00
fvdl
3230052ed9 Change setgate() prototype. 
Define GDT entries for DDB and double fault TSS.
 2002-10-05 21:26:24 +00:00
fvdl
8cea44a52a Adapt i386_send_ipi prototype. Make spllock < splipi (IPI paths 
changed to use __cpu_simple_lock because of LOCKDEBUG conflict).
 2002-10-05 21:25:24 +00:00
fvdl
df3dd8684d Add mask for TLB IPI rendezvous, and stackpointers + TSS structures 
for TSS gates per CPU.

XXX struct cpu_info is getting to be a bit large
 2002-10-05 21:22:31 +00:00
fvdl
75b1ec0ed0 Add wrapper for trap() to be used for traps that come in via a TSS. 2002-10-05 21:21:05 +00:00
fvdl
23349480e8 To be able to set up TSS gates, setgate needs another argument for the 
selector.
 2002-10-05 21:20:27 +00:00
fvdl
b70873cac2 Add double fault TSS stub code. 2002-10-05 21:20:00 +00:00
fvdl
4c9f03d9e5 Make i386_send_ipi return an error when it fails to send. 2002-10-05 21:19:39 +00:00
fvdl
736c720259 Deal with coming in via a TSS. 2002-10-05 21:19:16 +00:00
fvdl
d24101a133 Set up TSS gates per CPU for DDB IPI and double fault handlers. 2002-10-05 21:18:44 +00:00
fvdl
220edb92fa Add stub for DDB IPI via a TSS. 2002-10-05 21:17:35 +00:00
chs
ecdf1b4084 add missing protos, clean up includes. 2002-10-05 17:16:33 +00:00
chs
89fab1629e cats has full protos. 2002-10-05 17:12:51 +00:00
chs
038d3a7684 add missing protos. 2002-10-05 17:12:09 +00:00
chs
65c08c58b4 copy over some stuff from the shark version of this file. 
(how did this compile before?)
add missing protos.
 2002-10-05 17:04:44 +00:00
chs
cdd13585e9 add missing protos. 2002-10-05 17:01:51 +00:00
chs
0b379cf8d7 add missing protos. 2002-10-05 17:01:49 +00:00
chs
50697f04c0 remove leftover acorn32 headers. 2002-10-05 17:01:10 +00:00
chs
c0950517f1 fix void * math, turn on -Wpointer-arith. 2002-10-05 16:25:34 +00:00
elric
19ac738a39 add [commented out] cgd's to generic kernel configs. 2002-10-05 16:02:38 +00:00
bjh21
96f1e7a472 Correct some gratuitously-wrong indentation. 2002-10-05 13:57:11 +00:00
bjh21
3832819227 Minimal changes to allow a kernel with "options MULTIPROCESSOR" to compile 
and boot multi-user on a single-processor machine.  Many of these changes
are wildly inappropriate for actual multi-processor operation, and correcting
this will be my next task.
 2002-10-05 13:46:57 +00:00
chris
dfcb3e3552 Add random jitter to stat clock, the random jitter is +- 511 usec's, so 
we should average the nominal clock rate.

stathz now runs at hz (the hard clock hz), without getting high amounts of
time in interrupt handling.
 2002-10-05 12:22:55 +00:00
scw
c784454024 Use a more aesthetically pleasing 10% duty-cycle for the heartbeat LED. 2002-10-05 12:18:58 +00:00
scw
a7330033a9 Add ex(4), ahc(4), scsibus(4), and sd(4). 2002-10-05 11:43:23 +00:00
scw
1b3c8f3be0 Flesh out cpu_reboot(). 2002-10-05 11:01:13 +00:00
scw
fa307a78a6 A couple of additions: 
- sysfpga_sreset()
   Hit the soft-reset register to reset the board.

 - sysfpga_twinkle_led()
   Might as well put the blinkenlight on the Cayman to good use as
   a "heartbeat" indicator.
 2002-10-05 10:59:10 +00:00
chris
50e43712d9 Add commented out WSDISPLAY_CHARFUNCS. Using it enables wsmoused support. 2002-10-05 10:42:23 +00:00
scw
0bd5c145b4 Pick up sh3's disksubr.c instead of maintaining an identical copy locally. 
This allows the two architectures to share disklabels.
 2002-10-05 09:51:17 +00:00
scw
cf68c75f4a Simplify the test for KSEG0 addresses in pmap_extract() so that it 
works for _all_ KSEG0 addresses, not just managed VAs.
 2002-10-05 08:23:32 +00:00
gmcgarry
8a6f05a3ec At least make it compile even though it doesn't make sense. 2002-10-05 05:55:46 +00:00
bjh21
7e6e75483b Don't define DEBUG if it's already defined. 2002-10-04 22:46:29 +00:00
martin
76b8216ed6 Disable tagged queuing for the esp driver, with a comment describing 
why and how to re-enable it. The driver is broken, and can currently
cause data corruption.

Since this file is included by the INSTALL config, enabling tagged queueing
could prevent first time installation (and creation of a custom kernel
with these settings changed)
 2002-10-04 21:11:27 +00:00
joda
337993c988 use the same mnemonics as linux for cpu features (this is -o linux 
after all)
 2002-10-04 19:39:54 +00:00
junyoung
8c56af5cb9 Don't init IDT twice. 2002-10-04 19:27:05 +00:00
junyoung
857da21d88 Correctly identify model 6, 7, and 8 of AMD Athlon and Duron processors. 
Before:
cpu0: AMD Athlon Model 6 (Palomino) (686-class), 1532.11 MHz

After:
cpu0: AMD Athlon XP 1800+ (686-class), 1532.11 MHz
 2002-10-04 18:42:34 +00:00
elric
d19d268a95 assign majors for raw and cooked cgd's. 2002-10-04 18:28:24 +00:00
rearnsha
16930e9cb8 Hmm, fix some bogosity in my previous attempt to fix some bogosity:-) 
Keep SYMTAB_SPACE (but clean it up).
Restore iophy PHYs.
 2002-10-04 17:14:48 +00:00
matt
2f1192b327 CFATTACH mem_sbi, not sbi 2002-10-04 17:09:51 +00:00
tsutsui
714e6adf24 Add le* at isapnp? 2002-10-04 16:24:47 +00:00
scw
4c6f867793 s/COPTS/DEFCOPTS/ 2002-10-04 10:24:05 +00:00
scw
26ebb442bf - Hook the PCI arbiter and error interrupts, and print something 
useful should one occur.
- Manually poke some config values into the sh5pci host bridge's
  config registers since it doesn't appear in config. space.
- Reserve the first 256 bytes of i/o space to avoid assigning i/o
  address 0 to any cards.
- Slight tweak to the initialisation code after consultation with
  SuperH and the linux driver.
 2002-10-04 10:22:24 +00:00
chris
5dded94793 Fixup IPL_LEVELS to be correct. This matches the change I did to footbridge 
based systems.  Untested on shark, but is the right thing to do.  I suspect
the original arm32 intr.h had the bug, and when the ports split we just took
the bug.
 2002-10-04 10:21:33 +00:00
scw
a520b3b2c8 Convert to new devsw world order. 2002-10-04 10:16:56 +00:00
scw
db80ebe781 Add needs-flag to sysfpga, and check it before calling sysfpga_nmi_clear(). 2002-10-04 09:24:52 +00:00
scw
d4c3160197 pmap_bootstrap() needs to know the physical address of KSEG0. 2002-10-04 09:23:27 +00:00
scw
f7f3db86ff When loading a DMA map, make sure the BUS_DMA_COHERENT flag in the 
map accurately tracks the same flag in the segments belonging to it.
The map's copy can be set only if all the segments are coherent.

This finally gets NFS writes fully working on my PCI ex(4) card.
 2002-10-04 09:20:20 +00:00
scw
99fec1b346 Minor pmap rototil: 
- Track unmanaged mappings of RAM more closely by allocating a pvo
   for them. This allows us to check more accurately for multiple
   cache-mode-incompatible mappings.

 - As part of the above, implement pmap_steal_memory(). This has the
   beneficial side-effect of moving a fair chunk of kernel data
   structures into KSEG0.
 2002-10-04 09:17:57 +00:00
simonb
a66f0d74ef This file hasn't been used in a long time. 2002-10-04 08:48:35 +00:00
simonb
dcd65411b2 Only declare and set the "step" variable in identifycpu() ifdef CPUDEBUG. 2002-10-04 08:44:08 +00:00
junyoung
acd50bf487 Back out pushl/popl -> movl change. copy_fault is also used by kcopy(9). 2002-10-04 06:43:40 +00:00
explorer
3a856ad198 use config_match() 2002-10-04 06:02:38 +00:00
junyoung
f9939562a1 Fix a mistake in previous commit. 2002-10-04 04:40:12 +00:00
junyoung
8ab9e2ef57 Use single movl instruction rather than pushl/popl pair. 2002-10-04 03:20:59 +00:00
itojun
8f0eabf697 whitespace 2002-10-04 03:17:00 +00:00
thorpej
d90d300b7b Overhaul the way cfattach structures are looked up. The cfdata entry 
now carries the name of the attachment (e.g. "tlp_pci" or "audio"),
and cfattach structures are registered at boot time on a per-driver
basis.  The cfdriver and cfattach pointers are cached in the device
structure when attached.
 2002-10-04 01:50:53 +00:00
thorpej
1a5a7fe7b7 Use indirect configuration for on-board devices (i.e. those things 
attached to "obio") on the IQ80310 and IQ80321.  It makes more sense
to do it this way for this type of system (the goal being to encapsulate
as much information about the board as possible into one file).
 2002-10-03 20:14:58 +00:00
thorpej
cea0a147b4 Add macros to convert an "IRQ" number to its respective XINT3/XINT0 bit. 2002-10-03 20:11:42 +00:00
thorpej
072eedb728 Add a symbolic constant for where external interrupts start. 2002-10-03 20:10:40 +00:00
fvdl
547337a4ce FIx off by one error for brand id array index. 2002-10-03 19:39:51 +00:00
elric
70bf1b763b prepend syscall_fancy and syscall_plain with mach_ to get this to compile 
again.
 2002-10-03 19:17:01 +00:00
uwe
fbcf88f171 Add wscons. Misc catch-up with GENERIC. 2002-10-03 17:45:20 +00:00
uwe
fa76f154c6 Add majors for wscons devices. 
And, no!  This does not mean that sparc switches to wscons.
Only Krups has experimental wscons support so far.
 2002-10-03 17:06:18 +00:00
uwe
7235b5d479 First cut at PS/2 keyboard and mouse drivers that talk Sun firm events. 
Console and Xsun for Mr.Coffee.
 2002-10-03 16:27:04 +00:00
uwe
fb2195ae8f Search children of the "8042" node to check if keyboard is the stdin. 2002-10-03 16:22:46 +00:00
uwe
191626f788 Refactor kbd and mouse drivers so that they can use different middle 
layers.  Common middle layer shared by kbd_zs and sunkbd is moved into
the new file.  Move shared config directives to files.sun and adjust
ports' files.* accordingly.

Need this to support console/Xsun on Mr.Coffee JavaStation.

Tested on sparc, sparc64 (by martin) and sun3 (by jdc).
 2002-10-03 16:13:24 +00:00
fvdl
4eb09bb2aa Make shared IRQs for the normal PIC case work again as they did before 
the MP merge (i.e. treat them as having the lowest level of all registered
handlers in the chain for the IRQ).
 2002-10-03 15:58:56 +00:00
uwe
50de7c9595 If we don't get record drq from pnpbios, set it to play drq. 
Otherwise attaching half-duplex device will trigger panic.
NB: ad1848_isa_get_props should probably check for recdrq == -1 as well.
 2002-10-03 03:02:11 +00:00
thorpej
0c1efadb23 Include <sys/param.h> so that we get the defn of NULL. 2002-10-03 01:57:24 +00:00
thorpej
dd14964387 Fix script-o. 2002-10-03 01:29:30 +00:00
jdolecek
47ae4d5c59 remove local declaration of iwm_cd and fd_cd for LKM case; it's superfluous 
and doesn't even compile after latest autoconf changes
 2002-10-02 20:35:28 +00:00
rearnsha
16c4b46282 Revert previous change. GENERIC already has an sb* at isapnp? 2002-10-02 20:33:44 +00:00
jdolecek
2bbadb1fa6 make ha_name const 2002-10-02 20:21:32 +00:00
jdolecek
c802e99987 make ka_name const 2002-10-02 20:21:01 +00:00
jdolecek
a38b5eed0e adapt to latest dev/ic/wi* changes 2002-10-02 20:13:48 +00:00
scw
c859106ab8 Gee, this file is showing its origins... cpu_swapout() may invoke 
panic() on MIPS, but really shouldn't do the same on SH5.
 2002-10-02 16:19:59 +00:00
thorpej
4bf871a755 Add trailing ; to CFATTACH_DECL. 2002-10-02 16:02:08 +00:00
thorpej
89bf5a8f8e Add trailing ; to CFATTACH_DECL. 2002-10-02 15:52:22 +00:00
thorpej
bd5bb4652b Add trailing ; to CFATTACH_DECL 2002-10-02 15:45:10 +00:00
drochner
59ec26b0d3 _C_LABEL(curproc) disappeared - have cpu_info now 
(still uniprocessor only)
 2002-10-02 15:23:31 +00:00
drochner
5a62e785ca add kvm86_incall again which got lost in the SMP merge 2002-10-02 14:54:43 +00:00
scw
b13817324e Fix the initial cacheline alignment case. This gets my PCI ex(4) card 
pretty much working, at least for non-NFS use.

With NFS, it fails under pressure probably due to operand cache aliases
between KSEG0 and regular 4KB mappings elsewhere. Sigh.
 2002-10-02 14:40:27 +00:00
scw
9e1133a710 In pmap_page_is_cacheable(), add an explicit check for KSEG0 addresses. 
They don't show up in the page tables, so the default "not cacheable"
status is wrong.

This finally gets my ex(4) working on the Cayman's PCIbus.
 2002-10-02 12:19:38 +00:00
itohy
d64dac0bb7 ../../../../arch/dreamcast/dev/g2/gapspci.c:62: macro `CFATTACH_DECL' used with only 5 args 2002-10-02 09:49:38 +00:00
scw
4c12ca2bdc Don't clear the original contents of r0 in sigreturn(). We're returning 
to the interrupted context, not the sigreturn syscall stub.
 2002-10-02 08:13:09 +00:00
scw
240029a2aa NetBSD/sh5 post-dates the old "signal trampoline" delivery mechanism, 
so don't bother even pretending it exists.
 2002-10-02 08:10:34 +00:00
thorpej
10e0a941aa Use ELF-safe local labels. 2002-10-02 06:18:32 +00:00
thorpej
666aa24c58 Use CFATTACH_DECL(). 2002-10-02 05:51:28 +00:00
thorpej
1ad8e0ff42 Tidy up CFATTACH_DECL() formatting. 2002-10-02 05:47:08 +00:00
thorpej
c5e91d447d Use CFATTACH_DECL(). 2002-10-02 04:55:47 +00:00
thorpej
021b694d77 Use CFATTACH_DECL(). 2002-10-02 04:40:08 +00:00
thorpej
d52d005f78 Use CFATTACH_DECL(). 2002-10-02 04:27:51 +00:00
thorpej
adb90ad2ae Use CFATTACH_DECL(). 2002-10-02 04:17:21 +00:00
thorpej
b96bc0d7bc Use CFATTACH_DECL(). 2002-10-02 04:06:36 +00:00
thorpej
47c14a34bc Fix script-o's in last. 2002-10-02 03:36:20 +00:00
thorpej
7c0e5bcc4b Fix script-o's in previous. 2002-10-02 03:31:58 +00:00
thorpej
4cac257e08 More script-o fixes. 2002-10-02 03:25:46 +00:00
thorpej
9b3343e917 Fix script-o in last. 2002-10-02 03:18:07 +00:00
thorpej
5a9ddc1422 Use CFATTACH_DECL(). 2002-10-02 02:21:20 +00:00
thorpej
0dac35b547 Use CFATTACH_DECL(). 2002-10-02 02:00:07 +00:00
thorpej
354bc052d9 Use the register prefix in the ELF case in _PROF_PROLOGUE. 2002-10-02 00:23:29 +00:00
bjh21
92c36acca6 Report the hardware version in case anyone's interested (I was). 2002-10-01 22:52:22 +00:00
bjh21
cef90c2dc7 Constify ide_versions. 2002-10-01 22:38:56 +00:00
bjh21
b828507087 constify various string tables. 2002-10-01 22:33:10 +00:00
bjh21
7e08b73e47 Use CFATTACH_DECL(). 2002-10-01 22:23:52 +00:00
bjh21
8b39ec99a9 Add a shutdown hook which puts the Hydra back into its post-reset state, 
largely to ensure that we don't leave the slave CPUs running when we go
back to RISC OS.
 2002-10-01 22:18:00 +00:00
bjh21
b585e1d57a Remove a spurious ']' from the CFATTACH_DECL invokation. 2002-10-01 22:11:14 +00:00
thorpej
a942508291 Use CFATTACH_DECL(). 2002-10-01 21:36:00 +00:00
thorpej
217c799fe7 Use CFATTACH_DECL(). 2002-10-01 21:24:43 +00:00
reinoud
4d64d47a1f Remove old unused cruft 2002-10-01 21:16:15 +00:00
scw
c4efa0ddba Change IPL_SOFTNET to 3. 2002-10-01 21:07:31 +00:00
scw
0e3aa70138 Count all soft interrupt events per level, rather than just 
the first one per call to softintr_dispatch().
 2002-10-01 21:04:59 +00:00
scw
92c80efadc Fix a soft interrupt botch which prevented softints being dispatched 
on exit from regular h/w interrupts.
 2002-10-01 20:41:52 +00:00
provos
d94186ee91 more trailing \r cleanup; pointed out by wiz 2002-10-01 20:41:22 +00:00
fvdl
6b7332c86b The local APIC registers are defined for 32bit access only, so don't 
use movzbl on them.
 2002-10-01 19:36:51 +00:00
fvdl
bb7657559b Don't use pool(9) for TLB shootdown queue elements. Recent pool 
changes made the usage here clash with the pool code, and the
pool code is overkill for this case (fixed number of elements,
always NOWAIT).

Use a simple static freelist allocator instead (pv_list-like).
 2002-10-01 19:36:06 +00:00
thorpej
3b6eef8108 Use CFATTACH_DECL(). 2002-10-01 19:24:47 +00:00
thorpej
ad2758f375 Use CFATTACH_DECL(). 2002-10-01 19:18:57 +00:00
matt
be5fafec51 ANSI'fy the inline functions. 2002-10-01 19:08:51 +00:00
thorpej
c1077f220d Use CFATTACH_DECL(). 2002-10-01 18:57:48 +00:00
thorpej
34c3944c08 Use CFATTACH_DECL(). 2002-10-01 18:40:06 +00:00
scw
2ce95435ad One of the last pieces of the SH5 pmap jigsaw; detect and deal with 
operand cache synonyms and paradoxes for shared mappings:

 - Writable mappings are cache-inhibited if the underlying physical
   page is mapped at two or more *different* VAs.

   This means that read-only mappings at different VAs are still
   cacheable. While this could lead to operand cache synonyms, it
   won't cause data loss. At worst, we'd have the same read-only
   data in several cache-lines.

 - If a new cache-inhibited mapping is added for a page which has
   existing cacheable mappings, all the existing mappings must be
   made cache-inhibited.

 - Conversely, if a new cacheable mapping is added for a page which
   has existing cache-inhibited mappings, the new mapping must also
   be made cache-ibhibited.

 - When a mapping is removed, see if we can upgrade any of the
   underlying physical page's remaining mappings to cacheable.

TODO: Deal with operand cache aliases (if necessary).
 2002-10-01 15:01:48 +00:00
fvdl
1aca7be70a Add cpu0 at mainbus0 2002-10-01 13:29:03 +00:00
fvdl
26ab868e68 Merge Bill Sommerfeld's i386 MP branch. This code has some known 
caveats, but works quite well in a lot of MP cases, and all
UP cases that I have tested. Parts of this will hopefully be
reworked in the not-too-distant future.
 2002-10-01 12:56:36 +00:00
aymeric
f835a6ae04 . treat a stream of framing errors as a single break 
. trigger ddb upon receiving a break if we are the console
 2002-10-01 12:17:09 +00:00
reinoud
7ba11c51fd Fix some small range checks and why weren't we writing the palette in when 
we're asked to set the VIDC in a given state! :-D ahum... these are fixed
now. The top palette entry wasn't set.
 2002-10-01 12:09:49 +00:00
bsh
10bb2aff03 add board type for Intel PXA2[15]0 and Samsung S3C2800 based boards. 2002-10-01 11:02:27 +00:00
abs
ef14d0e624 Enable PPP_* options for ppp 2002-10-01 09:52:10 +00:00
abs
cd05e3d894 Enable ppp 2002-10-01 09:37:11 +00:00
scw
9d94c9899c Check if an interrupt is already claimed _after_ locating the 
right interrupt handle.
 2002-10-01 07:58:54 +00:00
scw
1e4acb4d20 Another temporary fix until I write a bootloader: run the kernel 
through dbsym(8).
 2002-10-01 07:56:45 +00:00
scw
5a512e6285 Flesh out bus_dmamap_sync(). 2002-10-01 07:55:17 +00:00
scw
02301c13c5 Add a #define for the SH5's cacheline size. 2002-10-01 07:50:36 +00:00
scw
a5ea619bef In pmap_extract() deal with KVAs in KSEG0 (which can be passed by the 
bus_dma(9) code) instead of panicing.
 2002-10-01 07:49:46 +00:00
thorpej
82af7d52d4 Use CFATTACH_DECL(). 2002-10-01 05:32:42 +00:00
thorpej
fa165ee3fd Use CFATTACH_DECL(). 2002-10-01 05:18:59 +00:00
thorpej
b7e3052e30 Use CFATTACH_DECL(). 2002-10-01 05:01:37 +00:00
thorpej
6bc733245c Missed one use of CFATTACH_DECL(). 2002-10-01 04:59:10 +00:00
thorpej
a84e1f7f8f Use CFATTACH_DECL(). 2002-10-01 04:43:01 +00:00
thorpej
f59e5352f2 Use CFATTACH_DECL(). 2002-10-01 04:21:32 +00:00
thorpej
d1c37db940 Use CFATTACH_DECL(). 2002-10-01 03:10:12 +00:00
thorpej
c4cbfcf060 Use CFATTACH_DECL(). 2002-10-01 02:54:11 +00:00
thorpej
d652bdcafe Use CFATTACH_DECL(). 2002-10-01 02:49:56 +00:00
thorpej
4ed249cc6f Remove unecessary extern decl of ade_ca. 2002-10-01 01:40:32 +00:00
bjh21
b59e2e1320 Beginnings of support for the Simtec Hydra multiprocessor board. 
So far, the Hydra is detected and initialised, and each slave CPU is
spun up briefly to check that it works.
 2002-09-30 23:22:05 +00:00