I had assumed for ages this would increase the amount of caching and
thereby increase the chance of stale caches leading to rendering
glitches. But apparently I was wrong, and failing to pass these
through was causing all sorts of problems!
- Make struct agp_i810_softc::gatt specific to i810 chipsets; use other
members of struct agp_i810_softc for non-i810 chipsets.
- agp_i810_init detects and sets isc->gtt_size.
- Map GTT based on the GTT size detected by agp_i810_init.
- Sprinkle some comments particularly about questionable calculations.
- Fix up error branches in agp_i810_attach.
- Use a separate bus space handle for the GTT, whether it is in a
separate BAR or a subregion of the MMIO device registers, so that
(a) agp_i810_write_gtt_entry and agp_i810_post_gtt_entry are easier to
follow, and
(b) we can map the GTT prefetchable eventually.
While here, fix the use of the I915 PCI MSAC register: it lies on the
bridge device (bus 0 dev 0 func 0), not the graphics device (bus 0
dev 2 func 0). I'm not sure we ever need to consult this register,
really -- the PCI BARs should be sized. But I'll leave a rototill of
this mess for another day.
