Rework agp_i810 attachment code a little.
- Fix up error branches in agp_i810_attach. - Use a separate bus space handle for the GTT, whether it is in a separate BAR or a subregion of the MMIO device registers, so that (a) agp_i810_write_gtt_entry and agp_i810_post_gtt_entry are easier to follow, and (b) we can map the GTT prefetchable eventually.
This commit is contained in:
riastradh
parent
9ba7c7ea46
commit
7d41993c06
@ -1,4 +1,4 @@
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/* $NetBSD: agp_i810.c,v 1.78 2014/05/26 19:15:39 riastradh Exp $ */
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/* $NetBSD: agp_i810.c,v 1.79 2014/05/27 03:17:33 riastradh Exp $ */
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/*-
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* Copyright (c) 2000 Doug Rabson
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.78 2014/05/26 19:15:39 riastradh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.79 2014/05/27 03:17:33 riastradh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -88,6 +88,7 @@ static bool agp_i810_resume(device_t, const pmf_qual_t *);
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static int agp_i810_init(struct agp_softc *);
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static int agp_i810_setup_chipset_flush_page(struct agp_softc *);
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static void agp_i810_teardown_chipset_flush_page(struct agp_softc *);
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static int agp_i810_init(struct agp_softc *);
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static struct agp_methods agp_i810_methods = {
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@ -107,7 +108,6 @@ int
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agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v)
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{
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u_int32_t pte;
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bus_size_t base_off, wroff;
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/* Bits 11:4 (physical start address extension) should be zero. */
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if ((v & 0xff0) != 0)
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@ -132,58 +132,18 @@ agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v)
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}
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}
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base_off = 0;
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wroff = (off >> AGP_PAGE_SHIFT) * 4;
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bus_space_write_4(isc->gtt_bst, isc->gtt_bsh,
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4*(off >> AGP_PAGE_SHIFT), pte);
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switch (isc->chiptype) {
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case CHIP_I810:
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case CHIP_I830:
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case CHIP_I855:
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base_off = AGP_I810_GTT;
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break;
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case CHIP_I965:
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base_off = AGP_I965_GTT;
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break;
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case CHIP_G4X:
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base_off = AGP_G4X_GTT;
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break;
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case CHIP_I915:
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case CHIP_G33:
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bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, wroff, pte);
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return 0;
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}
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WRITE4(base_off + wroff, pte);
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return 0;
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}
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void
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agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off)
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{
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bus_size_t base_off, wroff;
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base_off = 0;
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wroff = (off >> AGP_PAGE_SHIFT) * 4;
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switch (isc->chiptype) {
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case CHIP_I810:
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case CHIP_I830:
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case CHIP_I855:
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base_off = AGP_I810_GTT;
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break;
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case CHIP_I965:
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base_off = AGP_I965_GTT;
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break;
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case CHIP_G4X:
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base_off = AGP_G4X_GTT;
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break;
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case CHIP_I915:
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case CHIP_G33:
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(void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, wroff);
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return;
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}
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(void)READ4(base_off + wroff);
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(void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh,
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4*(off >> AGP_PAGE_SHIFT));
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}
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static void
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@ -313,14 +273,17 @@ agp_i810_attach(device_t parent, device_t self, void *aux)
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struct agp_softc *sc = device_private(self);
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struct agp_i810_softc *isc;
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struct agp_gatt *gatt;
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int error, apbase;
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bus_addr_t mmadr;
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bus_size_t mmadrsize;
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int apbase, mmadr_bar, gtt_bar;
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int mmadr_type, mmadr_flags;
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bus_addr_t mmadr, gtt_off;
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bus_size_t mmadr_size;
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int error;
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isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO);
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if (isc == NULL) {
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aprint_error(": can't allocate chipset-specific softc\n");
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return ENOMEM;
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error = ENOMEM;
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goto fail0;
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}
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sc->as_chipc = isc;
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sc->as_methods = &agp_i810_methods;
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@ -335,12 +298,13 @@ agp_i810_attach(device_t parent, device_t self, void *aux)
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case PCI_PRODUCT_INTEL_82845G_DRAM:
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case PCI_PRODUCT_INTEL_82815_FULL_HUB:
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case PCI_PRODUCT_INTEL_82855GM_MCH:
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free(isc, M_AGP);
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return agp_intel_attach(parent, self, aux);
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}
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#endif
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aprint_error(": can't find internal VGA device config space\n");
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free(isc, M_AGP);
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return ENOENT;
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error = ENOENT;
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goto fail1;
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}
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/* XXXfvdl */
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@ -405,90 +369,102 @@ agp_i810_attach(device_t parent, device_t self, void *aux)
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break;
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}
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mmadr_type = PCI_MAPREG_TYPE_MEM;
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switch (isc->chiptype) {
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case CHIP_I915:
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case CHIP_G33:
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apbase = AGP_I915_GMADR;
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mmadr_bar = AGP_I915_MMADR;
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gtt_bar = AGP_I915_GTTADR;
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break;
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case CHIP_I965:
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apbase = AGP_I965_GMADR;
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mmadr_bar = AGP_I965_MMADR;
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mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT;
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gtt_bar = 0;
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gtt_off = AGP_I965_GTT;
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break;
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case CHIP_G4X:
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apbase = AGP_I965_GMADR;
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mmadr_bar = AGP_I965_MMADR;
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mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT;
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gtt_bar = 0;
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gtt_off = AGP_G4X_GTT;
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break;
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default:
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apbase = AGP_I810_GMADR;
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mmadr_bar = AGP_I810_MMADR;
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gtt_bar = 0;
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gtt_off = AGP_I810_GTT;
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break;
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}
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if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) {
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/* Map (or, rather, find the address and size of) the aperture. */
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if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X)
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error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase);
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} else {
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else
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error = agp_map_aperture(&isc->vga_pa, sc, apbase);
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}
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if (error != 0) {
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if (error) {
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aprint_error(": can't map aperture\n");
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free(isc, M_AGP);
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return error;
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goto fail1;
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}
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if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) {
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error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR,
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PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
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&mmadr, &mmadrsize);
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if (error != 0) {
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aprint_error(": can't map mmadr registers\n");
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agp_generic_detach(sc);
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return error;
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/* Map the memory-mapped I/O registers, or the non-GTT part. */
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if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar,
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mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) {
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aprint_error_dev(self, "can't find MMIO registers\n");
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error = ENXIO;
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goto fail1;
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}
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if (gtt_bar == 0) {
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if (mmadr_size < gtt_off) {
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aprint_error_dev(self, "MMIO registers too small"
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": %"PRIuMAX" < %"PRIuMAX"\n",
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(uintmax_t)mmadr_size, (uintmax_t)gtt_off);
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error = ENXIO;
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goto fail1;
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}
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error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR,
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PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh,
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NULL, NULL);
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if (error != 0) {
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aprint_error(": can't map gttadr registers\n");
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/* XXX we should release mmadr here */
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agp_generic_detach(sc);
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return error;
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}
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} else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) {
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error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR,
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PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
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&mmadr, &mmadrsize);
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if (error != 0) {
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aprint_error(": can't map mmadr registers\n");
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agp_generic_detach(sc);
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return error;
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isc->size = gtt_off;
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} else {
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isc->size = mmadr_size;
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}
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isc->bst = isc->vga_pa.pa_memt;
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error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags,
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&isc->bsh);
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if (error) {
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aprint_error_dev(self, "can't map MMIO registers: %d\n",
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error);
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error = ENXIO;
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goto fail1;
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}
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/* Map the GTT, from either part of the MMIO region or its own BAR. */
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if (gtt_bar == 0) {
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isc->gtt_bst = isc->bst;
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isc->gtt_size = (mmadr_size - gtt_off);
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error = bus_space_map(isc->gtt_bst, gtt_off, isc->gtt_size,
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mmadr_flags, &isc->gtt_bsh);
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if (error) {
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aprint_error_dev(self, "can't map GTT: %d\n", error);
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error = ENXIO;
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goto fail2;
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}
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} else {
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error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR,
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PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
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&mmadr, &mmadrsize);
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if (error != 0) {
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aprint_error(": can't map mmadr registers\n");
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agp_generic_detach(sc);
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return error;
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/*
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* All chipsets with a separate BAR for the GTT, namely
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* the i915 and G33 families, have 32-bit GTT BARs.
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*
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* XXX [citation needed]
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*/
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if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM,
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0,
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&isc->gtt_bst, &isc->gtt_bsh, NULL, &isc->gtt_size)) {
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aprint_error_dev(self, "can't map GTT\n");
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error = ENXIO;
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goto fail2;
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}
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}
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isc->initial_aperture = AGP_GET_APERTURE(sc);
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gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
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if (!gatt) {
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agp_generic_detach(sc);
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return ENOMEM;
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}
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isc->gatt = gatt;
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gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT;
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if (!pmf_device_register(self, NULL, agp_i810_resume))
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aprint_error_dev(self, "couldn't establish power handler\n");
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/*
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* XXX horrible hack to allow drm code to use our mapping
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* of VGA chip registers
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*/
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agp_i810_vga_regbase = mmadr;
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agp_i810_vga_bsh = isc->bsh;
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/* Set up a chipset flush page if necessary. */
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switch (isc->chiptype) {
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case CHIP_I915:
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@ -500,13 +476,64 @@ agp_i810_attach(device_t parent, device_t self, void *aux)
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aprint_error_dev(self,
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"failed to set up chipset flush page: %d\n",
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error);
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agp_generic_detach(sc);
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return error;
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goto fail3;
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}
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break;
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}
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return agp_i810_init(sc);
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/* Set up the generic AGP GATT record. */
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isc->initial_aperture = AGP_GET_APERTURE(sc);
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gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
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if (!gatt) {
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error = ENOMEM;
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goto fail4;
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}
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isc->gatt = gatt;
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gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT;
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/* Power management. (XXX Nothing to save on suspend? Fishy...) */
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if (!pmf_device_register(self, NULL, agp_i810_resume))
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aprint_error_dev(self, "couldn't establish power handler\n");
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/*
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* XXX horrible hack to allow drm code to use our mapping
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* of VGA chip registers
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*/
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agp_i810_vga_regbase = mmadr;
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agp_i810_vga_bsh = isc->bsh;
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/* Initialize the chipset. */
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error = agp_i810_init(sc);
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if (error)
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goto fail5;
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/* Success! */
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return 0;
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#if notyet
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fail6: __unused
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agp_i810_fini(sc);
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#endif
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fail5: pmf_device_deregister(self);
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free(gatt, M_AGP);
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isc->gatt = NULL;
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fail4: switch (isc->chiptype) {
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case CHIP_I915:
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case CHIP_I965:
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case CHIP_G33:
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case CHIP_G4X:
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agp_i810_teardown_chipset_flush_page(sc);
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break;
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}
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fail3: bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size);
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isc->gtt_size = 0;
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fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size);
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isc->size = 0;
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fail1: free(isc, M_AGP);
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sc->as_chipc = NULL;
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fail0: agp_generic_detach(sc);
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KASSERT(error);
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return error;
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}
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static int
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@ -587,6 +614,31 @@ agp_i810_setup_chipset_flush_page(struct agp_softc *sc)
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return 0;
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}
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static void
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agp_i810_teardown_chipset_flush_page(struct agp_softc *sc)
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{
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struct agp_i810_softc *const isc = sc->as_chipc;
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if (isc->flush_addr) {
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/* If we allocated a page, clear it. */
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if (isc->chiptype == CHIP_I915) {
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR,
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0);
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} else {
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_I965_IFPADDR, 0);
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_I965_IFPADDR + 4, 0);
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}
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isc->flush_addr = 0;
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bus_space_free(isc->flush_bst, isc->flush_bsh,
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PAGE_SIZE);
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} else {
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/* Otherwise, just unmap the pre-allocated page. */
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bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE);
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}
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}
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/*
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* XXX horrible hack to allow drm code to use our mapping
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* of VGA chip registers
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@ -861,25 +913,7 @@ agp_i810_detach(struct agp_softc *sc)
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case CHIP_I965:
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case CHIP_G33:
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case CHIP_G4X:
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if (isc->flush_addr) {
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/* If we allocated a page, clear it. */
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if (isc->chiptype == CHIP_I915) {
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_I915_IFPADDR, 0);
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} else {
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_I965_IFPADDR, 0);
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_I965_IFPADDR + 4, 0);
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}
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isc->flush_addr = 0;
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bus_space_free(isc->flush_bst, isc->flush_bsh,
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PAGE_SIZE);
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} else {
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/* Otherwise, just unmap the pre-allocated page. */
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bus_space_unmap(isc->flush_bst, isc->flush_bsh,
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PAGE_SIZE);
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}
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agp_i810_teardown_chipset_flush_page(sc);
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break;
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}
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|
||||
@ -1262,6 +1296,10 @@ agp_i810_resume(device_t dv, const pmf_qual_t *qual)
|
||||
struct agp_softc *sc = device_private(dv);
|
||||
struct agp_i810_softc *isc = sc->as_chipc;
|
||||
|
||||
/*
|
||||
* XXX Nothing uses isc->pgtblctl! Save on suspend, restore on
|
||||
* resume?
|
||||
*/
|
||||
isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL);
|
||||
agp_flush_cache();
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: agp_i810var.h,v 1.3 2014/05/23 22:58:56 riastradh Exp $ */
|
||||
/* $NetBSD: agp_i810var.h,v 1.4 2014/05/27 03:17:33 riastradh Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000 Doug Rabson
|
||||
@ -35,23 +35,30 @@
|
||||
#include <dev/pci/agpvar.h>
|
||||
|
||||
struct agp_i810_softc {
|
||||
u_int32_t initial_aperture; /* aperture size at startup */
|
||||
struct agp_gatt *gatt;
|
||||
int chiptype; /* i810-like or i830 */
|
||||
u_int32_t dcache_size; /* i810 only */
|
||||
u_int32_t stolen; /* number of i830/845 gtt entries
|
||||
for stolen memory */
|
||||
bus_space_tag_t bst; /* register bus_space tag */
|
||||
bus_space_handle_t bsh; /* register bus_space handle */
|
||||
bus_space_tag_t gtt_bst; /* GTT bus_space tag */
|
||||
bus_space_handle_t gtt_bsh; /* GTT bus_space handle */
|
||||
struct pci_attach_args vga_pa;
|
||||
struct pci_attach_args vga_pa; /* integrated graphics device args */
|
||||
int chiptype; /* chipset family: i810, i830, &c. */
|
||||
|
||||
u_int32_t pgtblctl;
|
||||
/* Memory-mapped I/O for device registers. */
|
||||
bus_space_tag_t bst;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
|
||||
bus_space_tag_t flush_bst; /* flush page bus_space tag */
|
||||
bus_space_handle_t flush_bsh; /* flush page bus_space handle */
|
||||
bus_addr_t flush_addr; /* flush page bus address */
|
||||
/* Graphics translation table. */
|
||||
bus_space_tag_t gtt_bst;
|
||||
bus_space_handle_t gtt_bsh;
|
||||
bus_size_t gtt_size;
|
||||
|
||||
/* Chipset flush page. */
|
||||
bus_space_tag_t flush_bst;
|
||||
bus_space_handle_t flush_bsh;
|
||||
bus_addr_t flush_addr;
|
||||
|
||||
uint32_t initial_aperture; /* aperture size at startup */
|
||||
struct agp_gatt *gatt; /* AGP graphics addr. trans. tbl. */
|
||||
uint32_t dcache_size; /* i810-only on-chip memory size */
|
||||
uint32_t stolen; /* num. GTT entries for stolen mem. */
|
||||
|
||||
uint32_t pgtblctl; /* saved PGTBL_CTL? XXX unused */
|
||||
};
|
||||
|
||||
extern struct agp_softc *agp_i810_sc;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user