Pass cache-related flags through to the GTT on pre-SNB devices.
I had assumed for ages this would increase the amount of caching and thereby increase the chance of stale caches leading to rendering glitches. But apparently I was wrong, and failing to pass these through was causing all sorts of problems!
This commit is contained in:
riastradh
parent
8bf6e1b17b
commit
1a0c0250a7
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@ -1,4 +1,4 @@
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/* $NetBSD: agp_i810.c,v 1.116 2015/02/26 00:58:17 riastradh Exp $ */
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/* $NetBSD: agp_i810.c,v 1.117 2015/03/06 22:03:06 riastradh Exp $ */
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/*-
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* Copyright (c) 2000 Doug Rabson
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.116 2015/02/26 00:58:17 riastradh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.117 2015/03/06 22:03:06 riastradh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -120,15 +120,23 @@ static struct agp_methods agp_i810_methods = {
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};
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int
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agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v)
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agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off,
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bus_addr_t addr, int flags)
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{
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u_int32_t pte;
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/* Bits 11:4 (physical start address extension) should be zero. */
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if ((v & 0xff0) != 0)
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/*
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* Bits 11:4 (physical start address extension) should be zero.
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* Flag bits 3:0 should be zero too.
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*
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* XXX This should be a kassert -- no reason for this routine
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* to allow failure.
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*/
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if ((addr & 0xfff) != 0)
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return EINVAL;
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KASSERT(flags == (flags & 0x7));
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pte = (u_int32_t)v;
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pte = (u_int32_t)addr;
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/*
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* We need to massage the pte if bus_addr_t is wider than 32 bits.
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* The compiler isn't smart enough, hence the casts to uintmax_t.
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@ -138,17 +146,17 @@ agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v)
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if (isc->chiptype == CHIP_I965 ||
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isc->chiptype == CHIP_G33 ||
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isc->chiptype == CHIP_G4X) {
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if (((uintmax_t)v >> 36) != 0)
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if (((uintmax_t)addr >> 36) != 0)
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return EINVAL;
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pte |= (v >> 28) & 0xf0;
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pte |= (addr >> 28) & 0xf0;
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} else {
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if (((uintmax_t)v >> 32) != 0)
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if (((uintmax_t)addr >> 32) != 0)
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return EINVAL;
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}
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}
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bus_space_write_4(isc->gtt_bst, isc->gtt_bsh,
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4*(off >> AGP_PAGE_SHIFT), pte);
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4*(off >> AGP_PAGE_SHIFT), pte | flags);
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return 0;
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}
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@ -1128,7 +1136,8 @@ agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
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}
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}
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return agp_i810_write_gtt_entry(isc, offset, physical | 1);
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return agp_i810_write_gtt_entry(isc, offset, physical,
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AGP_I810_GTT_VALID);
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}
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static int
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@ -1146,7 +1155,7 @@ agp_i810_unbind_page(struct agp_softc *sc, off_t offset)
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}
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}
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return agp_i810_write_gtt_entry(isc, offset, 0);
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return agp_i810_write_gtt_entry(isc, offset, 0, 0);
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}
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/*
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@ -1322,9 +1331,6 @@ agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem,
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return 0;
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}
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#define I810_GTT_PTE_VALID 0x01
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#define I810_GTT_PTE_DCACHE 0x02
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static int
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agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem,
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off_t offset)
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@ -1338,7 +1344,7 @@ agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem,
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KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0);
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for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
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error = agp_i810_write_gtt_entry(isc, offset + i,
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i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE);
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i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE);
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if (error)
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goto fail0;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: agp_i810var.h,v 1.5 2014/06/10 14:00:56 riastradh Exp $ */
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/* $NetBSD: agp_i810var.h,v 1.6 2015/03/06 22:03:06 riastradh Exp $ */
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/*-
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* Copyright (c) 2000 Doug Rabson
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@ -67,6 +67,11 @@ struct agp_i810_softc {
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extern struct agp_softc *agp_i810_sc;
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int agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, bus_addr_t);
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#define AGP_I810_GTT_VALID 0x01
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#define AGP_I810_GTT_I810_DCACHE 0x02 /* i810-only */
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#define AGP_I810_GTT_CACHED 0x06 /* >=i830 */
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int agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, bus_addr_t,
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int);
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void agp_i810_post_gtt_entry(struct agp_i810_softc *, off_t);
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void agp_i810_chipset_flush(struct agp_i810_softc *);
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@ -1,4 +1,4 @@
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/* $NetBSD: intel_gtt.c,v 1.4 2014/07/16 20:56:25 riastradh Exp $ */
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/* $NetBSD: intel_gtt.c,v 1.5 2015/03/06 22:03:06 riastradh Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -32,7 +32,7 @@
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/* Intel GTT stubs */
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: intel_gtt.c,v 1.4 2014/07/16 20:56:25 riastradh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: intel_gtt.c,v 1.5 2015/03/06 22:03:06 riastradh Exp $");
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#include <sys/types.h>
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#include <sys/bus.h>
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@ -143,19 +143,31 @@ intel_gtt_insert_entries(bus_dmamap_t dmamap, unsigned va_page, unsigned flags)
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struct agp_i810_softc *const isc = agp_i810_sc->as_chipc;
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off_t va = (va_page << PAGE_SHIFT);
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unsigned seg;
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int gtt_flags = 0;
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int error;
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KASSERT(0 <= va);
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KASSERT((va >> PAGE_SHIFT) == va_page);
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KASSERT(0 < dmamap->dm_nsegs);
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gtt_flags |= AGP_I810_GTT_VALID;
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switch (flags) {
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case AGP_USER_MEMORY:
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break;
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case AGP_USER_CACHED_MEMORY:
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gtt_flags |= AGP_I810_GTT_CACHED;
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break;
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default:
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panic("invalid intel gtt flags: %x", flags);
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}
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for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
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const bus_addr_t addr = dmamap->dm_segs[seg].ds_addr;
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KASSERT(dmamap->dm_segs[seg].ds_len == PAGE_SIZE);
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/* XXX Respect flags. */
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error = agp_i810_write_gtt_entry(isc, va, (addr | 1));
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error = agp_i810_write_gtt_entry(isc, va, addr, gtt_flags);
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if (error)
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device_printf(agp_i810_sc->as_dev,
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"write gtt entry"
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@ -171,6 +183,7 @@ intel_gtt_clear_range(unsigned va_page, unsigned npages)
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{
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struct agp_i810_softc *const isc = agp_i810_sc->as_chipc;
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const bus_addr_t addr = intel_gtt.scratch_map->dm_segs[0].ds_addr;
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const int gtt_flags = AGP_I810_GTT_VALID;
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off_t va = (va_page << PAGE_SHIFT);
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KASSERT(0 <= va);
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@ -178,7 +191,7 @@ intel_gtt_clear_range(unsigned va_page, unsigned npages)
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KASSERT(0 < npages);
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while (npages--) {
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agp_i810_write_gtt_entry(isc, va, (addr | 1));
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agp_i810_write_gtt_entry(isc, va, addr, gtt_flags);
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va += PAGE_SIZE;
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}
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agp_i810_post_gtt_entry(isc, va - PAGE_SIZE);
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@ -1,4 +1,4 @@
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/* $NetBSD: intel-gtt.h,v 1.4 2014/07/16 20:56:25 riastradh Exp $ */
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/* $NetBSD: intel-gtt.h,v 1.5 2015/03/06 22:03:06 riastradh Exp $ */
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/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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@ -50,14 +50,8 @@ void intel_gtt_chipset_flush(void);
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void intel_gtt_insert_entries(bus_dmamap_t, unsigned, unsigned);
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void intel_gtt_clear_range(unsigned, unsigned);
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#define AGP_DCACHE_MEMORY 1
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#define AGP_PHYS_MEMORY 2
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/* XXX Dummy stubs -- should make these mean something and respect them. */
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#define AGP_USER_MEMORY 0
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#define AGP_USER_CACHED_MEMORY 0
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#define AGP_USER_CACHED_MEMORY_GFDT __BIT(3)
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#define AGP_USER_MEMORY 1
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#define AGP_USER_CACHED_MEMORY 2
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extern int intel_iommu_gfx_mapped;
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