Commit Graph

243 Commits

Author SHA1 Message Date
martin
3b9bf49423 Move to standard TNF 2 clause license 2008-05-04 00:01:08 +00:00
cube
607ead0ef4 Split device_t and softc for all com(4) devices (well, everything that
uses a com_softc backend).  Use proper types and ansify where appropriate.
2008-03-14 15:09:09 +00:00
matt
c6f7e7c68c Add MTX_* and RW_* definitions 2008-02-23 19:34:53 +00:00
he
e96f213c26 Delete a now-unused local variable. 2008-01-22 11:49:54 +00:00
dyoung
b480b62270 Make many ethernet drivers share the common code for MII media
handling, ether_mediastatus() and ether_mediachange().  Check for
a non-ENXIO error return from mii_mediachg().  (ENXIO indicates
that a PHY is suspended.)

This patch shrinks the source code size by 979 lines.  There was
a 5100-byte savings on the NetBSD/i386 kernel configuration, ALL.

I have made a few miscellaneous changes, too:

gem(4): use LIST_EMPTY(), LIST_FOREACH().
mtd(4): handle media ioctls, for a change!
axe(4): do not track link status in sc->axe_link any longer
nfe(4), aue(4), axe(4), udav(4), url(4): do not reset all PHYs
        on a change of media

Except for the change to mtd(4), no functional changes are intended.

XXX This patch affects more architectures than I can feasibly
XXX compile and run.  I have compiled macppc, sparc64, i386.  I
XXX have run the patches on i386 boxen with bnx(4) and sip(4).
XXX Compiling and running on evbmips (MERAKI, ADM5120) is in
XXX progress.
2008-01-19 22:10:14 +00:00
simonb
a191b55bff Bump uvmexp.intrs when we get a clock or statclock interrupt. 2008-01-09 06:50:36 +00:00
joerg
a280711321 Mask is unsigned, add missing u. 2008-01-08 13:52:00 +00:00
joerg
18a5a8d13d Finish conversion of ppc and evbppc to timecounter.
Tested by simonb@ on WALNUT.
2008-01-08 13:47:49 +00:00
ad
4a780c9ae2 Merge vmlocking2 to head. 2008-01-02 11:48:20 +00:00
ad
065b6ba2fb lockmgr -> mutex 2007-12-06 17:00:31 +00:00
ad
4b293a84e1 Interrupt handling changes, in discussion since February:
- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
2007-12-03 15:33:00 +00:00
simonb
f717d58276 Use lswi/syswi instead of lwz/stw when doing loads/stores since we don't
know the alignment of data being copied.  403 cores have alignment
restrictions on lwz/stw that 405 cores don't have.  lswi/syswi benchmark
at the same speed as lwz/stw on a 405 Walnut.

Fixes problems reported by Juergen Hannken-Illjes on the Explora.
2007-11-28 12:22:28 +00:00
hpeyerl
078cd4b352 Optimize copyin/copyout to transfer as many words as possible before doing
residual bytes. This improves small transfers. As a result, we can avoid
doing bigcopyin/bigcopyout until len>1024 instead of len>256.

Reviewed by: simonb.

(everybody run, Herb's in the kernel again).
2007-11-22 13:33:08 +00:00
ad
2783731b63 Set curlwp for the boot CPU before entering main(). 2007-11-19 02:12:11 +00:00
ad
bd6663fc4d Don't set l_usrpri / spc_curpriority here. mi_userret() does it. 2007-11-05 20:37:48 +00:00
garbled
d974db0ada Merge the ppcoea-renovation branch to HEAD.
This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
2007-10-17 19:52:51 +00:00
dyoung
6f7649313f Constify. 2007-08-26 22:28:52 +00:00
hannken
40135c9d50 Handle IST_LEVEL interrupts better. Disable interrupt while it is
processed and enable afterwards.  Up to now IST_LEVEL interrupts always
fired again during processing leaving unnecessary pending interrupts.

Tested on EXPLORA451.

Ok: Simon Burge <simonb@netbsd.org>
2007-07-24 15:22:18 +00:00
hannken
6409dfa660 Use PR_NOWAIT in in pmap_enter_pv() and take care of PMAP_CANFAIL. Built
after powerpc/oea/pmap.c.  Now a LOCKDEBUG kernel runs on EXPLORA451.

Ok: Simon Burge <simonb@netbsd.org>
2007-07-24 15:19:09 +00:00
ad
88ab7da936 Merge some of the less invasive changes from the vmlocking branch:
- kthread, callout, devsw API changes
- select()/poll() improvements
- miscellaneous MT safety improvements
2007-07-09 20:51:58 +00:00
rjs
9b21104e57 Fix for yamt-idlelwp merge. 2007-05-22 20:06:33 +00:00
rjs
d42d58ab33 Fix for yamt-idlelwp merge. 2007-05-18 11:16:27 +00:00
yamt
f03010953f merge yamt-idlelwp branch. asked by core@. some ports still needs work.
from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.
2007-05-17 14:51:11 +00:00
ad
59d979c5f1 Pass an ipl argument to pool_init/POOL_INIT to be used when initializing
the pool's lock.
2007-03-12 18:18:22 +00:00
christos
53524e44ef Kill caddr_t; there will be some MI fallout, but it will be fixed shortly. 2007-03-04 05:59:00 +00:00
thorpej
c8daa94cb1 TRUE -> true, FALSE -> false 2007-02-22 16:57:56 +00:00
thorpej
712239e366 Replace the Mach-derived boolean_t type with the C99 bool type. A
future commit will replace use of TRUE and FALSE with true and false.
2007-02-21 22:59:35 +00:00
ad
216d01d042 Make these compile again. 2007-02-15 15:14:57 +00:00
ad
b07ec3fc38 Merge newlock2 to head. 2007-02-09 21:55:00 +00:00
simonb
1fc6e76755 Fix a tyop in a comment. 2007-02-06 04:48:15 +00:00
freza
e388b581bd Welcome to evbppc/virtex -- port to Xilinx Virtex series FPGA's with embedded
ibm405d5 core.

OK by Simon Burge
2006-12-02 22:18:47 +00:00
freza
e2db2efb2e Instead of mapping whole RAM with reserved TLB entries, map just enough
to ensure trap code will work (that is 0 upto ${endkernel}) and leave the
rest to pmap_tlbmiss(). Mapping whole physmem into the kernel wired way
too many TLB entries, see

  http://mail-index.netbsd.org/port-powerpc/2006/10/27/0000.html

for performance analysis. While there, be a bit more descriptive in
pmap_tlbmiss() comment and use macro instead of numeric constant.

OK by Simon Burge
2006-11-29 19:56:46 +00:00
kiyohara
e95a66da33 * convert ibm4xx-based evbppc from reserved-TLB entry allocation to recently
introduced ppc4xx_tlb_reserve() API.
2006-10-16 18:14:38 +00:00
kiyohara
d7e6f0e206 * convert ibm4xx-based evbppc from reserved-TLB entry allocation to recently
introduced ppc4xx_tlb_reserve() API.
* ibm405gp UART0 used to be linear mapped. The VA happens to be inside kernel
  segment, giving us the possibility of multiple VA matches in the TLB. This
  is considered "programming error" by 405 core and results in "undefined
  behaviour". We now avoid mapping peripherals in kernel segment.
* Some boards used to map hardwired RAM size. We now use the real size as
  passed in by boot firmware.
2006-10-16 18:14:37 +00:00
kiyohara
c38c755c41 do bus_space_map() to get bus space handle in emacs_attach() 2006-10-16 18:14:35 +00:00
tsutsui
931bfebdc1 Fix an obvious typo. Patch from seebs in PR port-powerpc/33107. 2006-10-07 14:44:22 +00:00
chs
33c1fd1917 add support for O_DIRECT (I/O directly to application memory,
bypassing any kernel caching for file data).
2006-10-05 14:48:32 +00:00
freza
19461b0a95 Make sure we mask statclock timer on ibm4xx systems. This avoids
pthread "related" panics like:

    panic: remrunqueue: bit 18 not set
    Stopped in pid 479.3 (exsprite) at      netbsd:cpu_Debugger+0x10:       lwz
    r
    0, r1, 0x14
    db> bt
    0x869abe00: at panic+0x1b4
    0x869abe50: at remrunqueue+0x80
    0x869abe60: at mi_switch+0x114
    0x869abea0: at sa_unblock_userret+0x4e8
    0x869abee0: at syscall_plain+0x224
    0x869abf40: user SC trap #93 by 0x41949810: srr1=0xc030
               r1=0x445fff40 cr=0x40000002 xer=0 ctr=0x41aae208 esr=0 pid=0x36

While there, cleanup IPL_ definitions somewhat and fix interrupt mask
calculation per spl(9).

OK by matt@
2006-09-27 09:11:47 +00:00
gdamore
825211a4f8 Conversion of evbppc to generic TODR. ok freza@ 2006-09-18 22:05:47 +00:00
gdamore
d87601b78b Remove unused todclock files -- these are left overs from pre-generic-TODR. 2006-09-17 04:11:55 +00:00
freza
ca97defaa7 * ppc4xx_tlb_reserve(): allocate "reserved" TLB entries dynamically
* ppc4xx_tlb_mapiodev(): resolve pa to va from reserved TLB entries

OK by matt@

XXX we'll keep TLB_NRESERVED defined until we fix explora to use new API
2006-08-31 22:13:51 +00:00
freza
60d1041835 * add PVR values for Xilinx 405 cores
* don't try to decode vendor-specific PVR, print raw value instead.
* panic() if we see cache wasn't probed, we'd crash later anyway.
* rework the way PVR gets translated to core name.
* while there, normalize printf format ("%s: ...", device_xname(self), ...).

OK by matt@
2006-08-31 21:32:27 +00:00
ad
f474dceb13 Use the LWP cached credentials where sane. 2006-07-23 22:06:03 +00:00
ad
2b79369c7e - Hold a reference to the process credentials in each struct lwp.
- Update the reference on syscall and user trap if p_cred has changed.
- Collect accounting flags in the LWP, and collate on LWP exit.
2006-07-19 21:11:37 +00:00
gdamore
34537908ab Add an option COM_REGMAP to allow com(4) to use an array of register indices.
This allows us to convert aucom to just another com attachment, and cleanup
some code in the com_arbus.c.

Additionally, we use a common com_cleanup routine rather than having a
zillion copies of it in the attachment points.

This has been tested on a number architectures, and it has been shown to get
close to comparable performance when COM_REGMAP is defined, and comparable
when it is not defined.

Approved by core@.  Fixes PR port-evbmips/32362.
2006-07-13 22:56:00 +00:00
simonb
cc85b518f1 Remove unused ppc4xx_tlb_unpin() function. 2006-07-12 06:22:17 +00:00
thorpej
55e8bbeb6e Put appropriate prefixes on property names to reduce chances of name
collisions.
2006-07-10 16:28:44 +00:00
freza
75998ff7ee Fix recent ibm4xx/intr.c rework:
- Recalculate masks _after_ new interrupt handler is enqueued, otherwise
  the very last one won't ever be enabled (from hannken@)

- We can't use splhigh() to protect intr_calculatemasks() since it would
  use soon-to-be-invalid mask. Instead, fiddle PSL_EE directly as we do
  in other places.

Reviewed and tested (evbppc/explora) by hannken@
2006-07-10 12:52:13 +00:00
simonb
78877867ee Remove some unused variables. 2006-07-04 06:25:50 +00:00
freza
78037d3f6d Bring ibm4xx interrupt code up to date:
- generic soft interrupts (ie. use powerpc/softintr.c)
- interrupt event counters (using the ones from powerpc/cpu.h:cpu_info
  where appropriate)
- cleanup ibm4xx_intr.h, move implementation details to intr.c

Convert all affected evbppc platforms.

OK by simonb@, some points discussed with matt@
2006-06-30 17:54:50 +00:00