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* convert ibm4xx-based evbppc from reserved-TLB entry allocation to recently

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introduced ppc4xx_tlb_reserve() API.
This commit is contained in:
kiyohara 2006-10-16 18:14:38 +00:00
parent d7e6f0e206
commit e95a66da33
2 changed files with 4 additions and 10 deletions
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10
sys/arch/powerpc/ibm4xx/pmap.c
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@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.42 2006/08/31 22:13:51 freza Exp $ */
/* $NetBSD: pmap.c,v 1.43 2006/10/16 18:14:38 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.42 2006/08/31 22:13:51 freza Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.43 2006/10/16 18:14:38 kiyohara Exp $");
#include <sys/param.h>
#include <sys/malloc.h>
@ -267,10 +267,6 @@ pmap_bootstrap(u_int kernelstart, u_int kernelend)
int cnt, i;
u_int s, e, sz;
/* XXXfreza: compat, we used to statically reserve 4 entries. */
if (tlb_nreserved == 0)
tlb_nreserved = TLB_NRESERVED;
tlbnext = tlb_nreserved;
/*
@ -1454,7 +1450,7 @@ ppc4xx_tlb_reserve(paddr_t pa, vaddr_t va, size_t size, int flags)
va &= ~(rsize - 1); /* EPN */
lo = pa | TLB_WR | flags;
hi = va | TLB_VALID | szmask | KERNEL_PID;
hi = va | TLB_VALID | szmask;
#ifdef PPC_4XX_NOCACHE
lo |= TLB_I;

4
sys/arch/powerpc/include/ibm4xx/tlb.h
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@ -1,4 +1,4 @@
/* $NetBSD: tlb.h,v 1.3 2006/08/31 22:13:51 freza Exp $ */
/* $NetBSD: tlb.h,v 1.4 2006/10/16 18:14:38 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -109,6 +109,4 @@ void *ppc4xx_tlb_mapiodev(paddr_t, psize_t);
#define TLB_PID_INVALID 0xFFFF
#define TLB_NRESERVED 4 /* XXXfreza: kill. */
#endif /* _IBM4XX_TLB_H_ */