* ppc4xx_tlb_reserve(): allocate "reserved" TLB entries dynamically
* ppc4xx_tlb_mapiodev(): resolve pa to va from reserved TLB entries OK by matt@ XXX we'll keep TLB_NRESERVED defined until we fix explora to use new API
This commit is contained in:
freza
parent
037fe176f0
commit
ca97defaa7
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.41 2006/07/12 06:22:17 simonb Exp $ */
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/* $NetBSD: pmap.c,v 1.42 2006/08/31 22:13:51 freza Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -67,7 +67,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.41 2006/07/12 06:22:17 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.42 2006/08/31 22:13:51 freza Exp $");
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#include <sys/param.h>
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#include <sys/malloc.h>
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@ -96,12 +96,14 @@ caddr_t kernmap;
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#define MINCTX 2
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#define NUMCTX 256
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volatile struct pmap *ctxbusy[NUMCTX];
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#define TLBF_USED 0x1
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#define TLBF_REF 0x2
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#define TLBF_LOCKED 0x4
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#define TLB_LOCKED(i) (tlb_info[(i)].ti_flags & TLBF_LOCKED)
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typedef struct tlb_info_s {
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char ti_flags;
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char ti_ctx; /* TLB_PID assiciated with the entry */
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@ -110,7 +112,10 @@ typedef struct tlb_info_s {
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volatile tlb_info_t tlb_info[NTLB];
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/* We'll use a modified FIFO replacement policy cause it's cheap */
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volatile int tlbnext = TLB_NRESERVED;
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volatile int tlbnext;
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static int tlb_nreserved = 0;
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static int pmap_bootstrap_done = 0;
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/* Event counters */
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struct evcnt tlbmiss_ev = EVCNT_INITIALIZER(EVCNT_TYPE_TRAP,
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@ -151,6 +156,18 @@ struct pv_entry {
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struct pmap *pv_pm;
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};
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/* Each index corresponds to TLB_SIZE_* value. */
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static size_t tlbsize[] = {
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1024, /* TLB_SIZE_1K */
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4096, /* TLB_SIZE_4K */
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16384, /* TLB_SIZE_16K */
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65536, /* TLB_SIZE_64K */
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262144, /* TLB_SIZE_256K */
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1048576, /* TLB_SIZE_1M */
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4194304, /* TLB_SIZE_4M */
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16777216, /* TLB_SIZE_16M */
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};
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struct pv_entry *pv_table;
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static struct pool pv_pool;
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@ -167,6 +184,8 @@ static inline int pte_enter(struct pmap *, vaddr_t, u_int);
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static inline int pmap_enter_pv(struct pmap *, vaddr_t, paddr_t, boolean_t);
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static void pmap_remove_pv(struct pmap *, vaddr_t, paddr_t);
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static int ppc4xx_tlb_size_mask(size_t, int *, int *);
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inline struct pv_entry *
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pa_to_pv(paddr_t pa)
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@ -248,6 +267,12 @@ pmap_bootstrap(u_int kernelstart, u_int kernelend)
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int cnt, i;
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u_int s, e, sz;
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/* XXXfreza: compat, we used to statically reserve 4 entries. */
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if (tlb_nreserved == 0)
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tlb_nreserved = TLB_NRESERVED;
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tlbnext = tlb_nreserved;
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/*
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* Allocate the kernel page table at the end of
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* kernel space so it's in the locked TTE.
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@ -391,11 +416,12 @@ pmap_bootstrap(u_int kernelstart, u_int kernelend)
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pmap_kernel()->pm_ctx = KERNEL_PID;
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nextavail = avail->start;
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evcnt_attach_static(&tlbmiss_ev);
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evcnt_attach_static(&tlbhit_ev);
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evcnt_attach_static(&tlbflush_ev);
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evcnt_attach_static(&tlbenter_ev);
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pmap_bootstrap_done = 1;
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}
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/*
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@ -1185,7 +1211,7 @@ ppc4xx_tlb_flush(vaddr_t va, int pid)
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if (!pid)
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return;
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__asm("mfpid %1;" /* Save PID */
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__asm( "mfpid %1;" /* Save PID */
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"mfmsr %2;" /* Save MSR */
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"li %0,0;" /* Now clear MSR */
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"mtmsr %0;"
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@ -1244,7 +1270,7 @@ ppc4xx_tlb_find_victim(void)
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for (;;) {
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if (++tlbnext >= NTLB)
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tlbnext = TLB_NRESERVED;
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tlbnext = tlb_nreserved;
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flags = tlb_info[tlbnext].ti_flags;
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if (!(flags & TLBF_USED) ||
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(flags & (TLBF_LOCKED | TLBF_REF)) == 0) {
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@ -1287,7 +1313,7 @@ ppc4xx_tlb_enter(int ctx, vaddr_t va, u_int pte)
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idx = ppc4xx_tlb_find_victim();
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#ifdef DIAGNOSTIC
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if ((idx < TLB_NRESERVED) || (idx >= NTLB)) {
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if ((idx < tlb_nreserved) || (idx >= NTLB)) {
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panic("ppc4xx_tlb_enter: replacing entry %ld", idx);
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}
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#endif
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@ -1323,7 +1349,7 @@ ppc4xx_tlb_init(void)
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int i;
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/* Mark reserved TLB entries */
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for (i = 0; i < TLB_NRESERVED; i++) {
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for (i = 0; i < tlb_nreserved; i++) {
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tlb_info[i].ti_flags = TLBF_LOCKED | TLBF_USED;
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tlb_info[i].ti_ctx = KERNEL_PID;
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}
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@ -1340,6 +1366,109 @@ ppc4xx_tlb_init(void)
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:: "K"(SPR_ZPR), "r" (0x1b000000));
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}
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/*
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* ppc4xx_tlb_size_mask:
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*
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* Roundup size to supported page size, return TLBHI mask and real size.
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*/
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static int
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ppc4xx_tlb_size_mask(size_t size, int *mask, int *rsiz)
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{
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int i;
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for (i = 0; i < __arraycount(tlbsize); i++)
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if (size <= tlbsize[i]) {
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*mask = (i << TLB_SIZE_SHFT);
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*rsiz = tlbsize[i];
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return (0);
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}
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return (EINVAL);
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}
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/*
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* ppc4xx_tlb_mapiodev:
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*
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* Lookup virtual address of mapping previously entered via
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* ppc4xx_tlb_reserve. Search TLB directly so that we don't
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* need to waste extra storage for reserved mappings. Note
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* that reading TLBHI also sets PID, but all reserved mappings
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* use KERNEL_PID, so the side effect is nil.
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*/
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void *
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ppc4xx_tlb_mapiodev(paddr_t base, psize_t len)
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{
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paddr_t pa;
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vaddr_t va;
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u_int lo, hi, sz;
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int i;
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/* tlb_nreserved is only allowed to grow, so this is safe. */
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for (i = 0; i < tlb_nreserved; i++) {
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__asm volatile (
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" tlbre %0,%2,1 \n" /* TLBLO */
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" tlbre %1,%2,0 \n" /* TLBHI */
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: "=&r" (lo), "=&r" (hi)
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: "r" (i));
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KASSERT(hi & TLB_VALID);
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KASSERT(mfspr(SPR_PID) == KERNEL_PID);
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pa = (lo & TLB_RPN_MASK);
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if (base < pa)
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continue;
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sz = tlbsize[(hi & TLB_SIZE_MASK) >> TLB_SIZE_SHFT];
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if ((base + len) > (pa + sz))
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continue;
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va = (hi & TLB_EPN_MASK) + (base & (sz - 1)); /* sz = 2^n */
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return (void *)(va);
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}
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return (NULL);
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}
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/*
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* ppc4xx_tlb_reserve:
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*
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* Map physical range to kernel virtual chunk via reserved TLB entry.
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*/
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void
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ppc4xx_tlb_reserve(paddr_t pa, vaddr_t va, size_t size, int flags)
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{
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u_int lo, hi;
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int szmask, rsize;
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/* Called before pmap_bootstrap(), va outside kernel space. */
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KASSERT(va < VM_MIN_KERNEL_ADDRESS || va >= VM_MAX_KERNEL_ADDRESS);
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KASSERT(! pmap_bootstrap_done);
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KASSERT(tlb_nreserved < NTLB);
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/* Resolve size. */
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if (ppc4xx_tlb_size_mask(size, &szmask, &rsize) != 0)
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panic("ppc4xx_tlb_reserve: entry %d, %zuB too large",
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size, tlb_nreserved);
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/* Real size will be power of two >= 1024, so this is OK. */
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pa &= ~(rsize - 1); /* RPN */
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va &= ~(rsize - 1); /* EPN */
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lo = pa | TLB_WR | flags;
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hi = va | TLB_VALID | szmask | KERNEL_PID;
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#ifdef PPC_4XX_NOCACHE
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lo |= TLB_I;
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#endif
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__asm volatile(
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" tlbwe %1,%0,1 \n" /* write TLBLO */
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" tlbwe %2,%0,0 \n" /* write TLBHI */
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" sync \n"
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" isync \n"
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: : "r" (tlb_nreserved), "r" (lo), "r" (hi));
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tlb_nreserved++;
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}
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/*
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* We should pass the ctx in from trap code.
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@ -1388,7 +1517,7 @@ ctx_flush(int cnum)
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int i;
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/* We gotta steal this context */
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for (i = TLB_NRESERVED; i < NTLB; i++) {
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for (i = tlb_nreserved; i < NTLB; i++) {
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if (tlb_info[i].ti_ctx == cnum) {
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/* Can't steal ctx if it has a locked entry. */
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if (TLB_LOCKED(i)) {
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@ -1403,7 +1532,7 @@ ctx_flush(int cnum)
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return (1);
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}
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#ifdef DIAGNOSTIC
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if (i < TLB_NRESERVED)
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if (i < tlb_nreserved)
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panic("TLB entry %d not locked", i);
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#endif
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/* Invalidate particular TLB entry regardless of locked status */
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@ -1,4 +1,4 @@
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/* $NetBSD: tlb.h,v 1.2 2006/07/12 06:22:17 simonb Exp $ */
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/* $NetBSD: tlb.h,v 1.3 2006/08/31 22:13:51 freza Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -58,14 +58,14 @@
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#define TLB_SIZE_4M 6
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#define TLB_SIZE_16M 7
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#define TLB_PG_1K (TLB_SIZE_1K<<TLB_SIZE_SHFT)
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#define TLB_PG_4K (TLB_SIZE_4K<<TLB_SIZE_SHFT)
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#define TLB_PG_16K (TLB_SIZE_16K<<TLB_SIZE_SHFT)
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#define TLB_PG_64K (TLB_SIZE_64K<<TLB_SIZE_SHFT)
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#define TLB_PG_256K (TLB_SIZE_256K<<TLB_SIZE_SHFT)
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#define TLB_PG_1M (TLB_SIZE_1M<<TLB_SIZE_SHFT)
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#define TLB_PG_4M (TLB_SIZE_4M<<TLB_SIZE_SHFT)
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#define TLB_PG_16M (TLB_SIZE_16M<<TLB_SIZE_SHFT)
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#define TLB_PG_1K (TLB_SIZE_1K << TLB_SIZE_SHFT)
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#define TLB_PG_4K (TLB_SIZE_4K << TLB_SIZE_SHFT)
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#define TLB_PG_16K (TLB_SIZE_16K << TLB_SIZE_SHFT)
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#define TLB_PG_64K (TLB_SIZE_64K << TLB_SIZE_SHFT)
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#define TLB_PG_256K (TLB_SIZE_256K << TLB_SIZE_SHFT)
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#define TLB_PG_1M (TLB_SIZE_1M << TLB_SIZE_SHFT)
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#define TLB_PG_4M (TLB_SIZE_4M << TLB_SIZE_SHFT)
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#define TLB_PG_16M (TLB_SIZE_16M << TLB_SIZE_SHFT)
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/* TLBLO entries */
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#define TLB_RPN_MASK 0xfffffc00 /* Real Page Number mask */
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@ -102,11 +102,13 @@ void ppc4xx_tlb_flush(vaddr_t, int);
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void ppc4xx_tlb_flush_all(void);
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void ppc4xx_tlb_init(void);
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int ppc4xx_tlb_new_pid(struct pmap *);
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void ppc4xx_tlb_reserve(paddr_t, vaddr_t, size_t, int);
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void *ppc4xx_tlb_mapiodev(paddr_t, psize_t);
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#endif
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#define TLB_PID_INVALID 0xFFFF
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#define TLB_NRESERVED 4 /* Reserve 4 TLB entries for kernel */
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#define TLB_NRESERVED 4 /* XXXfreza: kill. */
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#endif /* _IBM4XX_TLB_H_ */
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