* if the driver hasn't been properly initialized, spin for a bit in wait_fifo()
rather than try to access the local0 status register.
* allow interrupt sharing (from Steve Rumble; necessary for IP20 glass TTY
support).
interrupts and timer calibration yet is also attached at mainbus).
Introduce the INDY_R4600_CACHE config option, which more accurately describes
the code enabled by this option.
This renders #ifdef IPxx completely obsolete, thus we theoretically can unify
the GENERIC files if a workable load address relocation scheme can be found.
mace devices to their own mace/ directory. Alter conf/files.sgimips to
reflect this change in a sane manner (i.e., pull in dev/files.dev and
mace/files.mace when appropriate).
At the same time, allow crime_intr_establish() to fall through to
mace_intr_establish(). mace devices now call cpu_intr_establish().
The recommended workaround is a 5-10ms delay before and after accesses.
Therefore, move the affected bus_space_* operations from bus.h to bus.c
and special-case MACE accesses.
CRIME accesses are not affected, so introduce SGIMIPS_BUS_SPACE_CRIME and
use it as the CRIME tag.
My ip32 seems a little bit happier with this change, and my ip22 didn't
notice the change.
zs_get_chan_addr() to reflect this.
XXX hardcoded addresses are quite distasteful. This should be passed in
through consinit() -- to avoid conflicts with Ilpo's soon-to-be-committed
framebuffer driver, I'll hold off until his code hits the tree.
(with several cosmetic changes by me) which fixes O2 (IP32) support.
Now my R5000 O2 works fine in multiuser with on-board AIC7880 SCSIs
and several PCI network cards (but only on serial console yet).
L2 cache on R5000/Rm5200 is still disabled for now, but it will be
fixed later, hopefully.
See recent discussion on port-sgimips for details.
store absolute year rather than an offset -- this means the clock is now
consitent across the ARCS PROM, IRIX and NetBSD.
XXX: This attachment is now a mismoner, since it's a Dallas Semi RTC, not
a Motorola RTC. Should be renamed.
pass in an interrupt handle (which is currently to the CRIME interrupt the
device is attached to) so the interrupt handlers know which device was the
one looking for attention.
While here, fix up PCI interrupt routing for both the on-board devices and
the PCI slots -- even though there is only one PCI slot in the chasis, the
hardware can accomodate up to three and provides an interrupt mapping for
all the PCI interrupt pins for both the internal SCSI & PCI slot and the
two "extra" slots.
