Commit Graph

36 Commits

Author SHA1 Message Date
briggs 6017201500 Rename PCI_MAPREG_TYPE_ROM to PCI_MAPREG_ROM_ENABLE to keep up with pciconf.? 2001-08-30 02:53:56 +00:00
thorpej cf65d4738c Add a bunch of Vital Product Data definitions. 2001-07-06 20:20:55 +00:00
briggs 433553dc94 Deal with a lack of the proper type of memory. For example, if a bridge
only supports 16-bit I/O addresses, do not configure it with addresses
having the upper 16-bits non-zero.
2001-02-12 06:24:24 +00:00
briggs c6daae9b79 Add an option (defopt) PCI_NETBSD_CONFIGURE that provides PCI bus
configuration (assignment of bus numbers, BARs, timer values,
interrupt lines, etc.).
The interface must be called from m.d. code prior to probing the bus.
It is meant to be called once for each primary (bus == 0) PCI bus in
the system.  It will configure any busses behind PCI-PCI bridges.
Section 9 man page for pci_configure_bus() will come soon.
In the meantime, sample usage is in arch/sandpoint/sandpoint/mainbus.c.
[ Reviewed by thorpej ]
2001-02-09 14:33:15 +00:00
cgd a3dbabc67b Update for current PCI device class/subclass and capability codes.
(also, tweak the I2O subclass string to be "standard" -- the removal
of version info didn't extend that far.)
2000-10-07 18:58:13 +00:00
ad 903ae58e7b I2O subclasses currently have nothing to do with the protocol version. 2000-10-02 14:48:13 +00:00
castor 2d8994210a Add a bunch of macros of the form PCI_<regname>_CODE similar to
existing PCI_ID_CODE to create the PCI appropriate register from
parameters.

Avoid use of 'class' in macro -- it's a C++ reserved keyword.
2000-08-21 05:17:33 +00:00
soda c41ca10d33 add "#define PCI_INTERRUPT_PIN_MAX 0x04" 2000-07-18 10:59:04 +00:00
soda 77625cf7ec long long constant needs "LL" suffix. 2000-06-09 04:45:53 +00:00
jhawk 8d671b6292 Define some PCI power management CSR constants. 2000-05-12 03:35:34 +00:00
thorpej 5939e70ca3 Add support for mapping 64-bit PCI memory space. If the region
is mapped in a way that is inaccessible by a 32-bit bus_addr_t, then
print a message to that effect and return failure.

Original patches by Bill Studenmund, with a few small changes by me.
2000-05-10 16:58:42 +00:00
kleink 085ec82073 Add a register offset for the Capability List Pointer in header type 2.
XXX Ideally the PCI-Cardbus Bridge header should be restructured to just
XXX present standard register definitions, making it ~safe to be included.
2000-05-08 10:45:52 +00:00
uch bbb8c56fcb add PCI_MAPREG_PPB_END (PCI-PCI bridge) PCI_MAPREG_PCB_END (PCI-Cardbus bridge) 2000-04-28 17:12:45 +00:00
drochner 4f1e715248 use BUS_SPACE_MAP_PREFETCHABLE instead BUS_SPACE_MAP_CACHEABLE where the
PCI BAR bit is referred to
2000-01-25 22:30:04 +00:00
enami 7463c844a0 Make this file compile again; terminate the continuation line with backslash. 1999-11-16 02:13:02 +00:00
thorpej a49d3ecb33 Add a macro to generate a class code given class, subclass, and interface.
From UCHIYAMA Yasushi's PCI BIOS patches.
1999-11-15 23:41:10 +00:00
cgd 6146ed7db8 add classes/subclasses new in PCI 2.2. Needs a bit of cleanup, but then,
so does everything involving configuration space headers and if i don't
get this out of my source tree i'll go insane.
1999-09-27 03:20:47 +00:00
drochner ac7ba300c0 add two of the newer register definitions 1998-12-21 20:31:54 +00:00
drochner bbe9d71415 add support for "extended capabilities" (new in PCI spec 2.2) 1998-11-07 16:47:22 +00:00
mycroft 6d3d8a1350 Make copyright notices with my name consistent. 1998-08-15 03:02:31 +00:00
cgd 350942b30d according to the PCI 2.1 spec, the low _two_ bits of I/O BARs have
defined meaning/value other than specifying the address of the region.
(lowest bit is 1, meaning I/O space.  second-lowest bit is reserved.)
1998-06-01 17:48:13 +00:00
cgd 27b21a3a47 add a PCI_HDRTYPE_TYPE() macro, to get the 'type' portion of the
headertype register (i.e., not including the 'multifunction' bit).
1998-05-18 17:17:04 +00:00
thorpej ce28bee247 Add UDF and 66MHz capable bit definitions for the PCI status register.
From Zubin D. Dittia <zubin@clouseau.arl.wustl.edu>, PR #4249.
1998-04-14 21:22:44 +00:00
cgd db11467340 clean up some constants ([A-F]->[a-f] in hex constants 1997-04-11 05:24:40 +00:00
cgd 2cde9c6e69 fix multi-function device support, add new known classes/subclasses,
and clean up class/subclass printing.  From brb@brig.com via PR 3359.
1997-03-19 19:38:46 +00:00
mycroft 121dfd8f1b Change PCI_MAPREG_{MEM,IO}_SIZE() to use the standard `x & -x' trick to select
the lowest bit set.  This isn't any more or less valid according to the PCI
spec, but it deals with lame devices that don't implement all of the top
bits.
1996-08-10 15:42:33 +00:00
cgd f160e92962 revert PCI_MAPREG_IO_ADDR_MASK and PCI_MAPREG_IO_SIZE_MASK to their old
values, i.e. 0xfffffffe and 0xffffffff respectively.  The changed
definitions were incorrect, according to the PCI Local Bus Specification
(Revision 2.0).  Further rationale and a workaround for the broken
devices that instigated the change provided in a message to
current-users@netbsd.org, dated Mon, 05 Aug 1996 22:06:58 -0400,
message ID 16773.839297218@ux2.sp.cs.cmu.edu>.
1996-08-06 02:11:25 +00:00
mycroft a2aa46e1c4 Add PCI_MAPREG_{IO,MEM}_SIZE(), and use them. 1996-07-26 07:13:52 +00:00
mycroft 53f21c73fb Changes PCI_MAPREG_IO_ADDR_MASK to 0xfffe. 1996-07-26 06:35:35 +00:00
cgd 87328287b7 modify these to provide a new, better-specified PCI interface
(soon to be documented on mailing lists; eventually in section 9 manual
pages), most importantly:
	(1) support interrupt pin swizzling on non-i386 systems with
	    PCI-PCI bridges (per PPB spec; done, but meaningless, on i386).
	(2) provide pci_{io,mem}_find(), to determine what I/O or memory
	    space is described by a given PCI configuration space
	    mapping register.
	(3) provide pci_intr_map(), pci_intr_string(), and
	    pci_intr_{,dis}establish() to manipulate and print info about
	    PCI interrupts.
	(4) make pci functions take as an argument a machine-dependent
	    cookie, to allow more flexibility in implementation.
1996-03-27 04:08:24 +00:00
cgd 72060dc6fa add definitions for the BIST/Header Type/Latency Timer/Cache Line Size
configuration space register, and use it to determine whether or not
a given PCI device uses multiple functions.
1996-03-27 00:13:50 +00:00
cgd c8487c701e reorganize mapping register definitions 1996-03-04 19:30:50 +00:00
mycroft fc427776a7 Add stuff for I/O mapping. 1995-07-27 00:29:02 +00:00
cgd 4f7335a75a macros to split out various parts of PCI registers, adjust constants
to match.  (now, comparisons are comparisons, code doing them doesn't
have to mask.)  define types for the various parts of the registers'
contents, where practical.
1995-06-18 01:34:01 +00:00
cgd 022ee8f7fe new RCS ID format. 1994-10-27 04:14:23 +00:00
mycroft 6df721be97 Add PCI autoconfiguration support. 1994-08-09 00:47:46 +00:00