fix multi-function device support, add new known classes/subclasses,
and clean up class/subclass printing. From brb@brig.com via PR 3359.
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cgd
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2b72395bfc
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2cde9c6e69
@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.19 1996/10/13 01:38:29 christos Exp $ */
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/* $NetBSD: pci_subr.c,v 1.20 1997/03/19 19:38:46 cgd Exp $ */
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/*
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* Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
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@ -67,6 +67,7 @@ struct pci_class pci_subclass_mass_storage[] = {
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{ "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, },
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{ "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, },
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{ "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, },
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{ "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, },
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{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, },
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{ 0 },
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};
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@ -75,6 +76,7 @@ struct pci_class pci_subclass_network[] = {
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{ "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, },
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{ "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, },
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{ "FDDI", PCI_SUBCLASS_NETWORK_FDDI, },
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{ "ATM", PCI_SUBCLASS_NETWORK_ATM, },
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{ "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, },
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{ 0 },
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};
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@ -107,10 +109,61 @@ struct pci_class pci_subclass_bridge[] = {
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{ "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, },
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{ "PCI", PCI_SUBCLASS_BRIDGE_PCI, },
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{ "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, },
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{ "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, },
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{ "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, },
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{ "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, },
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{ 0 },
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};
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struct pci_class pci_subclass_communications[] = {
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{ "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, },
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{ "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, },
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{ "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, },
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{ 0 },
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};
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struct pci_class pci_subclass_system[] = {
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{ "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, },
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{ "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, },
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{ "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, },
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{ "RTC", PCI_SUBCLASS_SYSTEM_RTC, },
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{ "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, },
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{ 0 },
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};
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struct pci_class pci_subclass_input[] = {
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{ "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, },
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{ "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, },
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{ "mouse", PCI_SUBCLASS_INPUT_MOUSE, },
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{ "miscellaneous", PCI_SUBCLASS_INPUT_MISC, },
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{ 0 },
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};
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struct pci_class pci_subclass_dock[] = {
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{ "generic", PCI_SUBCLASS_DOCK_GENERIC, },
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{ "miscellaneous", PCI_SUBCLASS_DOCK_MISC, },
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{ 0 },
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};
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struct pci_class pci_subclass_processor[] = {
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{ "386", PCI_SUBCLASS_PROCESSOR_386, },
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{ "486", PCI_SUBCLASS_PROCESSOR_486, },
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{ "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, },
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{ "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, },
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{ "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, },
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{ "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, },
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{ 0 },
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};
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struct pci_class pci_subclass_serialbus[] = {
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{ "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, },
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{ "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, },
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{ "SSA", PCI_SUBCLASS_SERIALBUS_SSA, },
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{ "USB", PCI_SUBCLASS_SERIALBUS_USB, },
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{ "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, },
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{ 0 },
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};
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struct pci_class pci_class[] = {
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{ "prehistoric", PCI_CLASS_PREHISTORIC,
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pci_subclass_prehistoric, },
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@ -126,6 +179,18 @@ struct pci_class pci_class[] = {
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pci_subclass_memory, },
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{ "bridge", PCI_CLASS_BRIDGE,
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pci_subclass_bridge, },
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{ "communications", PCI_CLASS_COMMUNICATIONS,
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pci_subclass_communications, },
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{ "system", PCI_CLASS_SYSTEM,
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pci_subclass_system, },
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{ "input", PCI_CLASS_INPUT,
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pci_subclass_input, },
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{ "dock", PCI_CLASS_DOCK,
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pci_subclass_dock, },
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{ "processor", PCI_CLASS_PROCESSOR,
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pci_subclass_processor, },
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{ "serial bus", PCI_CLASS_SERIALBUS,
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pci_subclass_serialbus, },
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{ "undefined", PCI_CLASS_UNDEFINED,
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0, },
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{ 0 },
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@ -214,26 +279,26 @@ pci_devinfo(id_reg, class_reg, showclass, cp)
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else if (product_namep != NULL)
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cp += sprintf(cp, "%s %s", vendor_namep, product_namep);
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else
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cp += sprintf(cp, "vendor %s, unknown product 0x%x",
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cp += sprintf(cp, "%s product 0x%04x",
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vendor_namep, product);
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if (showclass) {
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cp += sprintf(cp, " (");
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if (classp->name == NULL)
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cp += sprintf(cp,
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"unknown class 0x%2x, subclass 0x%02x",
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cp += sprintf(cp, "class 0x%02x, subclass 0x%02x",
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class, subclass);
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else {
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cp += sprintf(cp, "class %s, ", classp->name);
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if (subclassp == NULL || subclassp->name == NULL)
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cp += sprintf(cp, "unknown subclass 0x%02x",
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subclass);
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cp += sprintf(cp,
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"%s subclass 0x%02x",
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classp->name, subclass);
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else
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cp += sprintf(cp, "subclass %s",
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subclassp->name);
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cp += sprintf(cp, "%s %s",
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subclassp->name, classp->name);
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}
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#if 0 /* not very useful */
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cp += sprintf(cp, ", interface 0x%02x", interface);
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#endif
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cp += sprintf(cp, ", revision 0x%02x)", revision);
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if (interface != 0)
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cp += sprintf(cp, ", interface 0x%02x", interface);
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if (revision != 0)
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cp += sprintf(cp, ", revision 0x%02x", revision);
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cp += sprintf(cp, ")");
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}
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: pcireg.h,v 1.11 1996/08/10 15:42:33 mycroft Exp $ */
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/* $NetBSD: pcireg.h,v 1.12 1997/03/19 19:38:47 cgd Exp $ */
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/*
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* Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
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@ -123,6 +123,12 @@ typedef u_int8_t pci_revision_t;
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#define PCI_CLASS_MULTIMEDIA 0x04
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#define PCI_CLASS_MEMORY 0x05
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#define PCI_CLASS_BRIDGE 0x06
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#define PCI_CLASS_COMMUNICATIONS 0x07
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#define PCI_CLASS_SYSTEM 0x08
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#define PCI_CLASS_INPUT 0x09
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#define PCI_CLASS_DOCK 0x0A
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#define PCI_CLASS_PROCESSOR 0x0B
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#define PCI_CLASS_SERIALBUS 0x0C
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#define PCI_CLASS_UNDEFINED 0xff
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/* 0x00 prehistoric subclasses */
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@ -134,12 +140,14 @@ typedef u_int8_t pci_revision_t;
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#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
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#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
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#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
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#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
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#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
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/* 0x02 network subclasses */
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#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
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#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
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#define PCI_SUBCLASS_NETWORK_FDDI 0x02
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#define PCI_SUBCLASS_NETWORK_ATM 0x03
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#define PCI_SUBCLASS_NETWORK_MISC 0x80
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/* 0x03 display subclasses */
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@ -164,8 +172,47 @@ typedef u_int8_t pci_revision_t;
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#define PCI_SUBCLASS_BRIDGE_MC 0x03
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#define PCI_SUBCLASS_BRIDGE_PCI 0x04
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#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
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#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
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#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
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#define PCI_SUBCLASS_BRIDGE_MISC 0x80
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/* 0x07 communications subclasses */
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#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
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#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
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#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
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/* 0x08 system subclasses */
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#define PCI_SUBCLASS_SYSTEM_PIC 0x00
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#define PCI_SUBCLASS_SYSTEM_DMA 0x01
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#define PCI_SUBCLASS_SYSTEM_TIMER 0x02
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#define PCI_SUBCLASS_SYSTEM_RTC 0x03
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#define PCI_SUBCLASS_SYSTEM_MISC 0x80
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/* 0x09 input subclasses */
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#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
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#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
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#define PCI_SUBCLASS_INPUT_MOUSE 0x02
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#define PCI_SUBCLASS_INPUT_MISC 0x80
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/* 0x0A dock subclasses */
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#define PCI_SUBCLASS_DOCK_GENERIC 0x00
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#define PCI_SUBCLASS_DOCK_MISC 0x80
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/* 0x0B processor subclasses */
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#define PCI_SUBCLASS_PROCESSOR_386 0x00
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#define PCI_SUBCLASS_PROCESSOR_486 0x01
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#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
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#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
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#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
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#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
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/* 0x0C serial bus subclasses */
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#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
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#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
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#define PCI_SUBCLASS_SERIALBUS_SSA 0x02
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#define PCI_SUBCLASS_SERIALBUS_USB 0x03
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#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04
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/*
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* PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
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*/
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@ -176,7 +223,7 @@ typedef u_int8_t pci_revision_t;
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#define PCI_BIST(bhlcr) \
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(((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
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#define PCI_HDRTYPE_SHIFT 24
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#define PCI_HDRTYPE_SHIFT 16
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#define PCI_HDRTYPE_MASK 0xff
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#define PCI_HDRTYPE(bhlcr) \
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(((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
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@ -184,12 +231,12 @@ typedef u_int8_t pci_revision_t;
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#define PCI_HDRTYPE_MULTIFN(bhlcr) \
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((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
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#define PCI_LATTIMER_SHIFT 24
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#define PCI_LATTIMER_SHIFT 8
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#define PCI_LATTIMER_MASK 0xff
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#define PCI_LATTIMER(bhlcr) \
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(((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
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#define PCI_CACHELINE_SHIFT 24
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#define PCI_CACHELINE_SHIFT 0
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#define PCI_CACHELINE_MASK 0xff
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#define PCI_CACHELINE(bhlcr) \
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(((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
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