Update for current PCI device class/subclass and capability codes.
(also, tweak the I2O subclass string to be "standard" -- the removal of version info didn't extend that far.)
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a3dbabc67b
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@ -1,8 +1,8 @@
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/* $NetBSD: pci_subr.c,v 1.39 2000/10/02 14:48:13 ad Exp $ */
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/* $NetBSD: pci_subr.c,v 1.40 2000/10/07 18:58:13 cgd Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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* Copyright (c) 1995, 1996, 1998
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* Copyright (c) 1995, 1996, 1998, 2000
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* Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
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*
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@ -87,6 +87,7 @@ struct pci_class pci_subclass_mass_storage[] = {
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{ "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, },
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{ "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, },
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{ "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, },
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{ "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, },
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{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, },
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{ 0 },
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};
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@ -97,6 +98,8 @@ struct pci_class pci_subclass_network[] = {
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{ "FDDI", PCI_SUBCLASS_NETWORK_FDDI, },
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{ "ATM", PCI_SUBCLASS_NETWORK_ATM, },
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{ "ISDN", PCI_SUBCLASS_NETWORK_ISDN, },
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{ "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, },
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{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, },
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{ "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, },
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{ 0 },
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};
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@ -134,6 +137,8 @@ struct pci_class pci_subclass_bridge[] = {
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{ "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, },
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{ "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, },
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{ "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, },
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{ "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, },
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{ "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, },
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{ "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, },
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{ 0 },
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};
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@ -192,6 +197,10 @@ struct pci_class pci_subclass_serialbus[] = {
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/* XXX Fiber Channel/_FIBRECHANNEL */
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{ "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, },
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{ "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, },
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{ "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, },
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{ "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, },
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{ "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, },
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{ "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, },
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{ 0 },
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};
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@ -204,7 +213,7 @@ struct pci_class pci_subclass_wireless[] = {
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};
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struct pci_class pci_subclass_i2o[] = {
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{ "1.0", PCI_SUBCLASS_I2O_STANDARD, },
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{ "standard", PCI_SUBCLASS_I2O_STANDARD, },
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{ 0 },
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};
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@ -225,6 +234,7 @@ struct pci_class pci_subclass_crypto[] = {
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struct pci_class pci_subclass_dasp[] = {
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{ "DPIO", PCI_SUBCLASS_DASP_DPIO, },
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{ "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, },
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{ "miscellaneous", PCI_SUBCLASS_DASP_MISC, },
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{ 0 },
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};
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@ -744,6 +754,9 @@ pci_conf_print_type0(pc, tag, regs, sizebars)
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printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval));
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switch (PCI_CAPLIST_CAP(rval)) {
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case PCI_CAP_RESERVED0:
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printf("reserved");
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break;
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case PCI_CAP_PWRMGMT:
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printf("Power Management, rev. %d.0",
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(rval >> 0) & 0x07); /* XXX not clear */
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@ -762,11 +775,29 @@ pci_conf_print_type0(pc, tag, regs, sizebars)
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case PCI_CAP_MBI:
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printf("MBI");
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break;
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case PCI_CAP_HOTSWAP:
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printf("Hot-swapping");
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case PCI_CAP_CPCI_HOTSWAP:
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printf("CompactPCI Hot-swapping");
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break;
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case PCI_CAP_PCIX:
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printf("PCI-X");
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break;
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case PCI_CAP_LDT:
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printf("LDT");
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break;
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case PCI_CAP_VENDSPEC:
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printf("Vendor-specific");
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break;
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case PCI_CAP_DEBUGPORT:
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printf("Debug Port");
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break;
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case PCI_CAP_CPCI_RSRCCTL:
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printf("CompactPCI Resource Control");
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break;
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case PCI_CAP_HOTPLUG:
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printf("Hot-Plug");
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break;
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default:
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printf("unknown/reserved");
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printf("unknown");
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}
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printf(")\n");
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}
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@ -1,7 +1,7 @@
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/* $NetBSD: pcireg.h,v 1.31 2000/10/02 14:48:13 ad Exp $ */
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/* $NetBSD: pcireg.h,v 1.32 2000/10/07 18:58:14 cgd Exp $ */
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/*
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* Copyright (c) 1995, 1996, 1999
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* Copyright (c) 1995, 1996, 1999, 2000
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* Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
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*
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@ -167,6 +167,7 @@ typedef u_int8_t pci_revision_t;
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#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
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#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
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#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
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#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05
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#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
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/* 0x02 network subclasses */
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@ -175,6 +176,8 @@ typedef u_int8_t pci_revision_t;
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#define PCI_SUBCLASS_NETWORK_FDDI 0x02
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#define PCI_SUBCLASS_NETWORK_ATM 0x03
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#define PCI_SUBCLASS_NETWORK_ISDN 0x04
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#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
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#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
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#define PCI_SUBCLASS_NETWORK_MISC 0x80
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/* 0x03 display subclasses */
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@ -204,6 +207,8 @@ typedef u_int8_t pci_revision_t;
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#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
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#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
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#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
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#define PCI_SUBCLASS_BRIDGE_STPCI 0x09
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#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
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#define PCI_SUBCLASS_BRIDGE_MISC 0x80
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/* 0x07 communications subclasses */
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@ -249,6 +254,10 @@ typedef u_int8_t pci_revision_t;
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#define PCI_SUBCLASS_SERIALBUS_USB 0x03
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#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */
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#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05
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#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06
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#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
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#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
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#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
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/* 0x0d wireless subclasses */
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#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
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@ -273,6 +282,7 @@ typedef u_int8_t pci_revision_t;
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/* 0x11 data acquisition and signal processing subclasses */
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#define PCI_SUBCLASS_DASP_DPIO 0x00
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#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01
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#define PCI_SUBCLASS_DASP_MISC 0x80
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/*
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@ -379,17 +389,25 @@ typedef u_int8_t pci_revision_t;
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/*
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* capabilities link list (PCI rev. 2.2)
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*/
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#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
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#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
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#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
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#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
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#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
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#define PCI_CAP_PWRMGMT 1
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#define PCI_CAP_AGP 2
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#define PCI_CAP_VPD 3
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#define PCI_CAP_SLOTID 4
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#define PCI_CAP_MBI 5
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#define PCI_CAP_HOTSWAP 6
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#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
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#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
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#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
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#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
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#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
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#define PCI_CAP_RESERVED0 0x00
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#define PCI_CAP_PWRMGMT 0x01
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#define PCI_CAP_AGP 0x02
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#define PCI_CAP_VPD 0x03
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#define PCI_CAP_SLOTID 0x04
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#define PCI_CAP_MBI 0x05
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#define PCI_CAP_CPCI_HOTSWAP 0x06
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#define PCI_CAP_PCIX 0x07
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#define PCI_CAP_LDT 0x08
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#define PCI_CAP_VENDSPEC 0x09
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#define PCI_CAP_DEBUGPORT 0x0a
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#define PCI_CAP_CPCI_RSRCCTL 0x0b
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#define PCI_CAP_HOTPLUG 0x0c
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/*
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* Power Management Control Status Register; access via capability pointer.
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