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Author SHA1 Message Date
pk
363e8b8dbc Build whatis.db and infodir-meta from the commands list of the afterinstall 
target. Remember: inserting `dummy' targets is not equivalent of some
convenient macro expansion; it has side effects!
 2002-03-05 16:17:06 +00:00
simonb
8b5599e7ce Remove HPCMIPS_FLUSHCACHE_XXX debug code. 2002-03-05 16:16:45 +00:00
simonb
0d0a449d80 mips/mips/fp.S is in mips/conf/files.mips now. 2002-03-05 16:16:03 +00:00
christos
3e7f0b7101 add updwtmpx(); requested by tron. 2002-03-05 16:16:02 +00:00
simonb
4c27f5f8f7 mips/mips/fp.S is in mips/conf/files.mips now. 2002-03-05 16:14:57 +00:00
simonb
fd77e40b6b Provide a L2 cache configuration function. 2002-03-05 16:12:35 +00:00
simonb
713adcd0e8 Use new cache coherency attribute macro. 2002-03-05 16:11:57 +00:00
christos
2e53a01f3e add a couple of XOPEN compatibility defines, and a non-xopen function that 
we are expected to have (updwtmpx). Requested by tron.
 2002-03-05 16:09:06 +00:00
simonb
f1dbc97679 Not used anymore. 2002-03-05 16:08:55 +00:00
simonb
811ee92532 Add support for MIPS32 and MIPS64 architectures: 
- Build mips3/5900/32/64 support subroutines.
 - Move arch/mips/mips/fp.S to central location.
 - Move NOFPU to opt_cputype.h.
 2002-03-05 16:08:00 +00:00
simonb
f340c57568 Values related to the MIPS32/MIPS64 Privileged Resource Architecture 
(from Broadcom Corp).
 2002-03-05 16:07:10 +00:00
simonb
9ac7c86a0f Adjust for 5900 include file changes. 2002-03-05 16:06:04 +00:00
simonb
3f2f4c9bf6 r5900_vector_init() is in mips_machdep.c now. 2002-03-05 16:05:26 +00:00
simonb
dd756c0ca5 Rename <mips/r5900/cpuregs.h> to <mips/r5900regs.h> and remove some 
content no longer needed.
 2002-03-05 16:04:57 +00:00
simonb
fcdc111c1a Cosmestic changes (more like the mips3+ code). 2002-03-05 16:03:22 +00:00
simonb
c5d34b4371 Remove the number of TLB entries for different rx39 CPUs - this info 
is in the table in mips_machdep.c now.
 2002-03-05 16:02:48 +00:00
simonb
c6bcfb2589 Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
 2002-03-05 16:01:25 +00:00
simonb
0f9c00fc2e Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - ANSIfy.
 2002-03-05 15:57:20 +00:00
simonb
fa9c08ab16 Remove HPCMIPS_FLUSHCACHE_XXX debug code. 
Remove old unused exception frame unwind code.
Change a MIPS3 check to a MIPS3_PLUS check.
ANSIfy.
 2002-03-05 15:55:41 +00:00
simonb
278bfc1c02 Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:54:33 +00:00
simonb
351c1c16a6 Add support for MIPS32 and MIPS64 architectures: 
- Use a table-driven CPU detection algorithm instead of multiple
   case statements.
 - Add MIPS32/64 feature detection using the architected CP0 registers
   (from Broadcom Corp).
 - Call MD mips_machdep_cache_config() function if
   __HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
   L2 cache on some ports.
 2002-03-05 15:53:00 +00:00
simonb
ba8e2e82e4 Add support for MIPS32 and MIPS64 architectures: 
- Remove all mmu-related code that may use 32 register on mips32-style
   implementatios and move them to mipsX_subr.S - which is then included
   from mips{3,32,64,5900}_subr.S with various control defines enabled.
 - Remove local cache instruction flags
 - Add badaddr64 (from Broadcom Corp).
 2002-03-05 15:50:59 +00:00
simonb
9ed4fd257f Change a MIPS3 check to a MIPS3_PLUS check. 
XXX: I'm not 100% sure of the intent of this code - it would seem that
 it needs a run-time check of CPU ISA to be completely correct...
 2002-03-05 15:48:31 +00:00
simonb
d62813603c Check userland address and address alignent as two separate checks. 
Fix for when mips_reg_t is 64-bits.
ANSIfy.
 2002-03-05 15:46:51 +00:00
simonb
fe86ad150e Change MIPS3 checks to MIPS3_PLUS checks (XXX - still bogus!). 2002-03-05 15:44:40 +00:00
simonb
c9a3bd8900 Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Add a command to dump cp0 state.
 2002-03-05 15:43:25 +00:00
simonb
9b785c48f3 Cache ops for MIPS32/64 cpus. 2002-03-05 15:42:50 +00:00
simonb
0446046fde Add MIPS32/64 cache setup code (from Broadcom Corp). 2002-03-05 15:42:21 +00:00
simonb
cae6e0e516 Prototypes for MIPS32/64 cache ops. 2002-03-05 15:41:48 +00:00
simonb
0ff59237ca Change a MIPS3 check to a MIPS3_PLUS check (XXX - still bogus!). 2002-03-05 15:41:14 +00:00
simonb
01422aae5c Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:40:10 +00:00
simonb
1d05db445d Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 2002-03-05 15:39:31 +00:00
simonb
934c4ba555 Add support for MIPS32 and MIPS64 architectures: 
Remove the unused PSL_USERCLR and BASEPRI macros.
 2002-03-05 15:38:33 +00:00
tv
c8e92c46c8 Put klen' and newk' back in local block so that their scope is limited. 
(Reduces 1.31 to a one-line diff from 1.30.)
 2002-03-05 15:37:35 +00:00
simonb
b255c47737 Add support for MIPS32 and MIPS64 architectures: 
Better cache coherency attribute macros (from Broadcom Corp).
 2002-03-05 15:37:32 +00:00
simonb
f38d391749 Add support for MIPS32 and MIPS64 architectures: 
- Add mips32 and mips64 locore function prototypes.
 - Add mips3_lw_a64() and mips3_sw_a64() for access data at any
   64bit address (from Broadcom Corp).
 - Add Broadcom and Sandcraft CPU company ids.
 2002-03-05 15:36:51 +00:00
simonb
2fab526863 Add support for MIPS32 and MIPS64 architectures: 
- Add XKPHYS macros (from Broadcom Corp).
 - Add some r5900 register bit definitions.
 - Add extra exception vector addresses for mips32/mips64 and r5900.
 - Make the mips cp0 register definitions available from both asm and C.
 - Add some Alchemy and Sandcraft CPU ids.
 - Add r3000, tx39xx and r4x00 CPU revision ids.
 - Remove defines for the number of TLBs on some CPUs.
 2002-03-05 15:35:22 +00:00
simonb
60fe625bd0 Add support for MIPS32 and MIPS64 architectures: 
- Clean up (somewhat) mips1 vs mips3+ configuration.
   XXX:  this is still quite messy.
 - Add cpu frequency info to struct cpu_info.
 - ANSIfy.
 2002-03-05 15:34:04 +00:00
simonb
ef0fcacb94 ANSIfy. 2002-03-05 15:12:58 +00:00
wiz
10d6eb080d Drop duplicate .Pp. 2002-03-05 15:09:26 +00:00
pk
583e840c0b Make $(OBJS) depend on the ufs headers link. 2002-03-05 15:08:27 +00:00
wiz
505d53c807 Clarify input source. Drop a duplicate .Pp while I am here. 2002-03-05 15:06:16 +00:00
pk
5f8328c032 Serialize gram.y -> gram.[ch] transformation. 2002-03-05 15:00:07 +00:00
simonb
8070cbd848 Add 4way 16/32-byte-line cache op primitives. 2002-03-05 14:32:26 +00:00
simonb
e8e49d677b Don't explicitly depend locore_*.S and fp.S on assym.h - this is done 
for all .S files in /sys/conf/Makefile.kern.inc.
 2002-03-05 14:28:31 +00:00
simonb
7bd5992f7a Fix for when we have 64 bit registers enabled for userland (but still 
using the o32 API).
 2002-03-05 14:23:50 +00:00
tron
a7422358e9 Include "sys/time.h" here to get the definition of "struct timeval". 2002-03-05 14:23:32 +00:00
simonb
4a931bedb8 KNF whitespace. 2002-03-05 14:21:32 +00:00
simonb
59f53aab95 The 64-bit safe, ILP32 o32 model is safe with the current stdarg 
implementation.
 2002-03-05 14:18:12 +00:00
agc
b66bb2992d Output @blddep directives properly when displaying PLISTs. 2002-03-05 14:18:07 +00:00