- Fix up usage of MBD_ISPID().
- Ensure that we never deal with a NULL proc, and if our proc has
no pcb, punt. Suggested by Gordon Ross.
- Eliminate some redundant NULL pointer checks in the T_MMUFLT cases;
proc0.p_addr is now initialized early, and we make a single test
for sanity at the top of trap() now.
- Initialize proc0.p_addr just after setting up the kernel stack, to avoid
getting NULL pointers in trap(). Change suggested by Gordon Ross.
- Panic if main() returns.
- Tidy up a couple of comments.
(remaps page read/write/cache-inhibit, does write, restores previous
mapping). Kernel text no longer needs to be read/write with DDB/KGDB
is in the kernel.
Based on a similar module written for the Sun3 port by Gordon Ross,
and modified somewhat by me.
- Offset kernel text one page. Stash the PA of this offset page for
use later.
- Add a few comments.
- Free up some registers earlier in the initialization process.
- Use a `prototc' to set the Translation Control register, rather
than relying on a2 pointing just past the MMU trampoline in the
high page. (Suggested by Charles Hannum.)
- Set VBR to the kernel vector table just before turning on the MMU.
- Just before rebooting, set VBR to 0, which is what the BOOTROM expects
it to be.
kernel setroot(). The device type for network boot is set like any
other device now. Also, call the punit entry point for device drivers
to properly set `bootdev'.
The "options GENERIC" entry in kernel config files is not longer necessary
for "swap generic" kernels. Uses new config constructs which work with
some glue in an old config environment. This code will support new config
with minimal changes.
an unrecognized keyboard produced garbage on keypresses in the kernel,
but worked in the boot program (which has this default). The bug is
that the keymap pointers are unitialized.
mips_r2000_, mips_R2000_ -> mips1_
mips_r4000_, mips_R4000_ -> mips3_
(which are also, for mnemonic reasons, consistent with gcc flag usage,
rather than using mipsI_ and mipsIII_).
Where CACHED_TO_HYS() is still needed for kernel-virtual-to-physical
or physical-to-uncached mapping (fb drivers), replace with
`#include <mips/cpuregs.h>'.
* dcparam() with normal tty t_param interface, which calls
* cold_dcparam() called with explicit dc7085 register address
and flags, which does the work and is also callable when cold,
to set up console (or kgdb) line parameters.
* use mips_round_page,mips_trunc_seg() instead of
pica_round_page(),pica_trunc_page().
* discard (unused) return value from TLBUpdate(), and delete
(unused) temporary variable used to hold it.
* Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
to mips/include/mips1_pte.h
* Move mips-III pte (TLBlo) definitions from pica/include/pte.h
to mips/include/mips3_pte.h
* Add new mips/include/pte.h, which includes exactly one of
mips1_pte.h or mips3_pte.h (which still have namespace collisions),
depending on "options MIPS1" or "options MIPS3". (hack).
Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h
* Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
when mapping from pte to physical address.
* Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
the kernel pmap.)
* Use macros (not direct TLB frobbing) in mips/trap.c, to make it
mips-1/mips-III indepenndet.
* Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
jump-table) locore entrypoints, so the stack traceback code can use
the end marker to handle entry points specially when doing tracebacks,
even if it doesn't know about them explicitly.
* fold in netBSD style changes:
``if (foo = bar)'' -> ``if ((foo = bar) != 0)''
* add mips1 vector as well as mips3 vector
* change vector names to make mips1 and mips3 locore entrpoints distinct
* add pmax additions (e.g., old fixes to ktrace code, kernel-TLB_miss
instrumentation)
* update stack traceback code to a newer version of the pmax code.
add catch-all case, with distinct mips1 and mips3 ranges for locore
entry points, cases to catch othewise-unknown locore entrypoints and
vector code (which have special entry sequences and require special
support to trace through). The relevant mips1 and mips3 functions are
of course now distinct.
NetBSD-current changes:
* change include paths to be relative to the kernel-source tree
(e.g., `/sys') instead of arch/pmax/conf.
* add explicit options for exec packages (EXEC_ELF32, EXEC_ECOFF
for COMPAT_ULTRIX)
* comment out references to still-unsuppoted MI scsi.
DEC dc503 cursor chip) into Decstation 2100,3100 cfattach front-end
and ``machine-independent'' back-end.
pm_ds.c: pmin/pmax cfattach front-end
pm.c: bt478, 503 back-end
pmvar.h: declarations of back-end normal and console attach
entry points.
screen geometry.
- Re-arrange et_loadmode() and et_inittextmode() to write into shadow
register set instead of writing to the card-registers directly.
- provide et_hwsave()/et_hwrest() functions to transfer the card-registers
to and from the shadow set.
* New patchable variable maxphysmem to limit physical memory.
That's useful to simulate small machines for testing install
kernels.
* Make debugging crashdumps with gdb -k work.
* microtime is moved to clock.c.
* Reserve memory for symbol table when ddb is configured.
* Move checks for RB_KDB into consinit.
* Fix a typo in delay().
* Disable generation of profiling prologue for proc_trampoline,
sigcode, idle, handle_trap, flush_icache, svc and interrupt.
* A few tweaks to make kgdb and ddb work nicer.
* Support for bpf added.
* Don't duplicate code, use ether_ifattach instead.
* Recode plipreceive and pliptransmit in assembler.
This improves performance from 40 kbyte/s to 50 kbyte/s
between a 30mhz pc532 and a 25mhz i386.
exceptions, which puts the address of the instruction we faulted
on in a different location. Copy it and handle as we normally would,
restoring the saved PC before returning.
The FPE should probably be reworked to take advantage of the 68LC040's
precalculated effective address, at some point.
to signal that the build is happening on a machine with an ELF
toolchain. This is temporary, until a better toolchain-recognition
scheme is worked out.
- Only pass user trace traps and breakpoints on to trap().
Gets rid of some hair in the trace/breakpoint trap cases.
- Before entering the debugger, switch to a temporary
stack so that the debugger can alter the stack pointer.
- Add glue for KGDB (still not complete).
Some other minor cleanup:
- Protect against some bad pointer derefs.
- Be more a little more verbose when a fatal trap
occurs to aid debugging.
- Only pass user trace traps and breakpoints on to trap().
- Before entering the debugger, switch to a temporary
stack so that the debugger can alter the stack pointer.
- Add glue for KGDB (still not complete).
Clearly mark the MMU enable trampoline code.
the keyboard to work. Fixes a bug where booting with `-d' worked
only on systems using a serial console.
While I'm here, eliminate some redundancy in the ite console intialization
code.
This fixes a critical bug where a clock interrupt would happen sometime
between the call to hp300_calibrate_delay() and when proc0 is initialized.
This ends up dereferencing a bad pointer in itimerdecr(), which scribbles
over the first page of kernel text, specifically vectors 46 and 47 (decimal).
To complicate matters, the way the bug manifested itself was different
depending on whether or not DDB was configured into the kernel. When
DDB is in the kernel, kernel text is mapped read/write. When DDB is not
in the kernel, kernel text is mapped read-only. Note that the kernel
scribble happens early, typically before the console is initialized.
In the non-DDB case, the kernel will hang as soon as it's loaded because
the access causes a fault (before the console is initialized, so you
don't see the trap).
In the DDB case, the access does _not_ cause a fault. However, the
mechanism used to enter the kernel debugger is to issue a "trap #15".
Conveniently, this is one of the corrupted vectors (47), thus rendering
DDB useless (it actually caused a recursive panic/trap loop).
This _WILL_ be in the first 1.2 official patch.
include files containing model-specific I/O device configuration.
Add more options and devices (ccd, LKM, etc), as appropriate for
documentation and as examples in a "template" GENERIC config file,
even though not all of these work completely yet.
- This driver supports the on-board mbus-based cgfourteen (sometimes referred
to as "SX") video hardware present on SS20-class machines.
- It does *not* support any of the SX acceleration features.
- It does support the 8-bit mode of the hardware, and looks to X like
a cgthree.
- It does support the cg6-style hardware cursor, even when running X in
cgthree emulation.
- It does support DPMS power-down of compatible displays on later-revision
cg14's.
- There is code to support the true color (32-bit) mode of the cg14 as
cg8 emulation, but it is disabled by default because it is most likely
broken. #define CG14_CG8 to turn it on.
The driver is not yet installed in the conf files, but I will do so
shortly...
Check only the IR bit of the CIAA Interrupt Control Register when testing
for a level 6 interrupt. An interrupt only occurs if IR is set, and IR is
only set if the individual mask bits are set. The individual interrupt
status bits can be set without causing an interrupt if the corresponding
enable bits are not set.
from arch/mips/mips/locore.S to arch/pmax/pmax/locore_machdep.S.
* Move ARC-specific locore code (vmstat -i counters) to
arch/pica/pica/locore_machdep.S.
* When the mips3 locore support is known to work, both ports can now use
arch/mips/mips/locore.S.
wrappers for:
gets.c getenv.c strcat.c strcpy.c
so they compile again (if _KERNEL is defined).
For bootblock space reasons it would be prereable to call the PROM entrypoints
directly, via the macro wappers in de_prom.h, rather than C function wrappers.
* Create arch/mips/Makefile.inc with source list of generic MIPS-cpu
files for tags
* Use mips/Makefile.inc and updated tag list in pmax/Makefile
* Try building bootblocks in arch/pmax/stand.
clock_attach() time (for now).
This removes our dependance on the DraCo ROM access timing and frees
the second CIA on Amigas.
b) support for DraCo rev. >= 4 native timer chips.
mark