- Initialize proc0.p_addr just after setting up the kernel stack, to avoid
getting NULL pointers in trap(). Change suggested by Gordon Ross.
- Panic if main() returns.
create an assembly label, and SYSCALLNUM to convert a syscall name into
the macro that's defined to be its number. Add a CALLSYS_NOERROR macro
which invokes the named system call. (CALLSYS_NOERROR is here since
it's used in locore, for sigcode.)
* kill scc_tty[] and needs-count.
* Add usable-when-cold version of sccparam().
* Add pre-autconf() console initialization entrypoint.
* remove lint for gcc -Wall
* wbflush() -> tc_mb()
all but the last of which have been fed through cgd and committed to the
Alpha scc driver.
code as video memory must be reserved from main memory for the display.
In addition this adds generic support for using DRAM for video memory
on all machines. All video memory accessing should use the video_memory_t
structure.
Added support for the RC7500 motherboard. The RC7500 support includes a
replacement init_arm() function. This also supports the RC7500 prom debug
monitor for debugging the kernel boot.
dumps now work so call dumpsys() following a panic.
Added support for the SA110. This mainly consists of making sure the data
cache is cleaned when appropriate and that the instruction cache is
kept in sync during the bootstrap and when signal handlers are built on
the stack.
Use a larger UND32 mode stack if we are configured for KGDB.
Remove KERNEL_PT_KSTACK references as these should have died with the
removal of double mapped kstacks eons ago.
Make sure we call doshutdownhooks() if boot is called while we are still
cold.
Cleaned up prototypes declarations.
Sorted out comment indentation.
autoconfiguration. It clears the RPB's per-cpu-slot BIP flag and
sets up the RPB's restore_term and restart vectors, etc. add a
console_restart() function, which causes a panic and system dump,
that is invoked (indirectly) via those vectors.
eventually, the restart HWRPB vector), which calls console_restart. This
is invoked when the console halt switch is used and the user enters 'c'
at the console prompt, and eventually causes a system crash dump to be
generated.
clean and tlb flush code along with write buffer drains that are
dependant on the definition of CPU_SA110.
The memory reserved for the L1 pagetables is now wired into the memory map
during the pmap_init rather than at L1 pagetable allocation time.
The L1 pages tables are zeroed during initialisation and when they are
released rather than when they are allocated.
When searching for a free L1 page table start search at the page table
after the last one allocated rather than always starting from the first one.
Added some extra DIAGNOSTIC checks for invalidate page index numbers.
Removed some old debugging code that escaped the last clean up.
Idented comments in line with code.
The irq delivery code has been rewritten. On entry to the irq vector the
processor is switched to SVC32 mode so all interrupt routines now run
in SVC32 mode rather than IRQ32 mode. This fixes lots of irq re-enabling
problems.
Interrupt latency times are now vastly improved for high priority interrupts.
Cleaned up calling ast() before returning to USR32 mode (don't need to
mess about with trapframe copying.
Cleaned up all the comments and sorted out their indentation.
Rewritten the soft interrupt delivery code.
Added generic ARM7500 support rather than just RC7500 support.
Added support for the SA110. This cpu does not need any register fix-ups
following a data abort.
Return valid signal code values on SEGV's. See machine/signal.h for
decoding SEGV signal codes.
required during pagemove() and vmapbuf() and vunmapbuf().
The kernel and undefined mode stack checks are now guarded with
#ifdef STACKCHECKS.
Tidied up comments.
cache needs to be cleans and the instruction and data caches need to
be invalidate along with the instruction and data tlbs when
the TTB is reloaded during a context switch.
if CPU_SA110 is defined. Cache cleaning is different on the SA110 as
the cache is a write back virtual cache and is split for data and instruction.
Also the cache and tlb control instructions use different coprocessor #15
registers.
Removed suspect FPA probing code, instead use the ARM FPE to probe the FPA.
Neatened up the FPE attachment code.
Recognise StrongARM class of cpu.
Updated the fpa instruction bounce handler to expect a 4th argument
when called on an undefined trap to match recent changes made to
undefined handlers.
Add acknowledgement records to the buffer following origin or bounding
box changes.
Removed prototype for strncmp().
Added support for switch mouse reports between absolute and relative
positions.
This, in conjunction with the trap.c changes, solve the crashes when
referencing illegal addresses in the debugger. Thanks Jason for providing
the trigger and solution ;-)
- Re-write panictrap() so that faults generated by the debugger can be
handled by the debugger.
- Add a small bit of extra checking to the MMU_FAULT case, to make it more
robust against pieces of the proc-structure being NULL (Jason Thorpe)
- If p == NULL at the entry of trap(), assign proc0 to it. Fixes a *lot* of
NULL-pointer dereferences. (Gordon Ross)
immediately reasserted before we get a chance to process the interrupt,
we can inadvertantly get stuck with zs_tx_stopped set. Move the delta
detection to the hard zs interrupt handler; the softint handler
will notice that something has happened with CTS and restart the
transmitter if it's asserted.
brings us closer to basic operation.
- Verified/updated ROM vector entries for many systems, and new vector
table entries for LC 520, LC 575/577/578, and Quadra 950
- Implement a new machine class (MACH_CLASSQ2) for the LC 575 series
- Use the ptest040() helper function in get_physical().
Also, in straytrap(), only enter the debugger #ifdef DDB.
earlier stages of the NetBSD/arm32 development.
Added support for the architecture defined SWI's. Currently
The IMB and IMB-range architecture defined SWI's for the ARM810 are
currently recognised.
Various comments cleaned up.
Added the functions atmoic_set_bit() and atomic_clear_bit() that
can be used for setting and clearings bits atomically (need interrupts
to be turned off).
GPROF and PROFILE_ASM are defined.
Register usage has been changed to avoid using r11. This means we have
one less register to save during this function.
booting.
After assembling the post FP processing callback branch call
sync_icache() if CPU_SA110 is defined.
Return a valid signal code when raising a SIGFPE exception so
the cause of the SIGFPE can be determined.
Added the functions arm_fpe_getcontext() and arm_fpe_setcontext()
to obtain the FP context in a FPE independant form for the ptrace()
syscall.
In db_write_text() call sync_caches() after modifing the text area
if CPU_SA110 is defined.
Added a new machine command "frame" to print out a trapframe.
Trap the kernel break point instruction specifically and panic on
any other undefined instruction being executed in SVC mode.
scottr