failed and the current goal is to enumerate all PCI bus and this is the
first PCI host bridge, just assume it is bus 0 and ignore the error.
When querying the bus number, assume that the system paniced earlier if
an error happened and this is not the first/only PCI host bridge and
override the BBN as 0 in that case.
_BBN is 0, check if the _ADR field is also 0. If it is, assume that the
_BBN really should be 0. Otherwise, try to extract the _BBN from the
bridge itself using pchb logic and panic only, if that fails as well.
Reported and tested by Martin Husemann as interrupt issue.
and drop all but the first. This is the behaviour Windows seems to
implement and some BIOSes depend on that due to broken dups.
This should fix PR 37001.
Also output any detected errata at verbose, rather than debug, level so
they can be seen with dmesg, and at least have a clue if a BIOS update
would fix the errata.
errata:
254: Internal Resource Livelock Involving Cached TLB Reload
261: Processor May Stall Entering Stop-Grant Due to Pending Data
Cache Scrub
298: L2 Eviction May Occur During Processor Operation To Set
Accessed or Dirty Bit
309: Processor Core May Execute Incorrect Instructions on
Concurrent L2 and Northbridge Response
initialize APs. We need the lapic set up and the boot processor may
not be attached first.
- mp_cpu_start: write back and invalidate the data cache before starting the
init IPI sequence. If a buggy BIOS has left the AP with cache disabled,
it might not be able to participate in the cache coherency protocol.
send out for testing. The wrong version ended up in the commit.
Original description:
Don't use the legacy interrupt when deciding how to route IOAPIC pins.
On some modern systems not all devices have the PCI interrupt line
set, typically the cardbus bridge is affected and it would result in
different interrupt vectors used for the same IOAPIC pin.
To allow this, simplify the code by checking for an existing match first
and only allocate a new entry if that doesn't exist. For the IOAPIC case
don't bother with the reserveration on the primary CPU for ISA
interrupts, just use them.
hardware where it is mapped. At least one ACPI implementation seems to lie
about the physical address of the lapic.
- lapic_initclocks: be paranoid and issue an EOI.
