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53832 Commits

Author SHA1 Message Date
simonb
86cb239e4f Add a "clkread" function to the systemsw. 2002-03-06 07:35:13 +00:00
simonb
465e846051 Calculate the reciprocal of the divisor delay. From the comments: 
To implement a more accurate microtime using the CP0 COUNT
	register we need to divide that register by the number of
	cycles per MHz.  But...

	DIV and DIVU are expensive on MIPS (eg 75 clocks on the
	R4000).  MULT and MULTU are only 12 clocks on the same CPU.
	On the SB1 these appear to be 40-72 clocks for DIV/DIVU and 3
	clocks for MUL/MULTU.

	The strategy we use to to calculate the reciprical of cycles
	per MHz, scaled by 1<<32.  Then we can simply issue a MULTU
	and pluck of the HI register and have the results of the
	division.
 2002-03-06 07:34:36 +00:00
simonb
feb24029e7 Add the offset of ci_divisor_delay in struct cpu_info. 2002-03-06 07:32:15 +00:00
simonb
78c9211fca Add a field for the reciprocal of the divisor delay for use by microtime. 2002-03-06 07:31:38 +00:00
itohy
1990961dc9 Fix ADPCM playback/recording. 2002-03-06 07:12:02 +00:00
nathanw
3be9fbe42e Move #include <dev/sysmon/sysmonvar.h> inside #ifdef _KERNEL. 2002-03-06 06:37:17 +00:00
nathanw
2a72ef3147 Remove a variable that is unused after the previous ALTQ commit. 2002-03-06 05:33:05 +00:00
simonb
be6459cce6 Use the divisor delay from curcpu() in the implementation of delay(). 2002-03-06 03:29:16 +00:00
simonb
8eb960909e Determine and display the CPU clock frequency from the "System 
Identification and Revision Register", and set the frequency
related variables in curcpu info structure.
 2002-03-06 03:27:34 +00:00
simonb
3fe666190f Wrap long line and remove a bogus XXX comment. 2002-03-06 03:25:09 +00:00
simonb
f3e2fe6731 Add entry for sbmips. 2002-03-06 02:42:30 +00:00
simonb
4b7a128684 A basic port to the Broadcom/SiByte SB1250 evaluation board (the 
"swarm").  Other SB-cpu boards will be supported by this port in
the future.

Includes support for on-chip ethernet and serial.  Many features
still missing - notably SMP, PCI/LDT and IDE.

This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
 2002-03-06 02:13:37 +00:00
simonb
2c68c156c5 Only include <sys/exec_ecoff.h> if EXEC_ECOFF is defined. 
Note that ELF is mandatory.
 2002-03-06 00:22:09 +00:00
simonb
3ab34324e9 Remove a few unneeded include files. 2002-03-06 00:05:06 +00:00
simonb
1b5ddfe411 Add support for the on-chip peripherals on the Broadcom SiByte SB1250 CPU 
and support routines for the Broadcom CFE (Common Firmware Environment).

This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
 2002-03-05 23:46:40 +00:00
nathanw
3f0d660168 Make the debugging printfs compile: 
- printf format checking doesn't like %x for pointers; use %p like we should.
 - LP64 fixes.
 2002-03-05 23:28:58 +00:00
eeh
2f0ba3e1a2 More walnut-isms. 2002-03-05 22:02:25 +00:00
thorpej
84be4d4719 Fix size/padding of .data. From Nick. 2002-03-05 21:26:11 +00:00
briggs
257f8fe26f Add BAT_G for EUMB (incl. I/O) space. Per matt@netbsd.org's macppc change. 2002-03-05 19:06:38 +00:00
shiba
081fae3ddb Fix up a bug which PB150 shuts down when one boots up in progress. 
PB150 will work with SCSI disk. But we cannot use an internal IDE
disk yet.

Reviewed by briggs
 2002-03-05 17:39:25 +00:00
simonb
8b5599e7ce Remove HPCMIPS_FLUSHCACHE_XXX debug code. 2002-03-05 16:16:45 +00:00
simonb
0d0a449d80 mips/mips/fp.S is in mips/conf/files.mips now. 2002-03-05 16:16:03 +00:00
simonb
4c27f5f8f7 mips/mips/fp.S is in mips/conf/files.mips now. 2002-03-05 16:14:57 +00:00
simonb
fd77e40b6b Provide a L2 cache configuration function. 2002-03-05 16:12:35 +00:00
simonb
713adcd0e8 Use new cache coherency attribute macro. 2002-03-05 16:11:57 +00:00
simonb
f1dbc97679 Not used anymore. 2002-03-05 16:08:55 +00:00
simonb
811ee92532 Add support for MIPS32 and MIPS64 architectures: 
- Build mips3/5900/32/64 support subroutines.
 - Move arch/mips/mips/fp.S to central location.
 - Move NOFPU to opt_cputype.h.
 2002-03-05 16:08:00 +00:00
simonb
f340c57568 Values related to the MIPS32/MIPS64 Privileged Resource Architecture 
(from Broadcom Corp).
 2002-03-05 16:07:10 +00:00
simonb
9ac7c86a0f Adjust for 5900 include file changes. 2002-03-05 16:06:04 +00:00
simonb
3f2f4c9bf6 r5900_vector_init() is in mips_machdep.c now. 2002-03-05 16:05:26 +00:00
simonb
dd756c0ca5 Rename <mips/r5900/cpuregs.h> to <mips/r5900regs.h> and remove some 
content no longer needed.
 2002-03-05 16:04:57 +00:00
simonb
fcdc111c1a Cosmestic changes (more like the mips3+ code). 2002-03-05 16:03:22 +00:00
simonb
c5d34b4371 Remove the number of TLB entries for different rx39 CPUs - this info 
is in the table in mips_machdep.c now.
 2002-03-05 16:02:48 +00:00
simonb
c6bcfb2589 Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
 2002-03-05 16:01:25 +00:00
simonb
0f9c00fc2e Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - ANSIfy.
 2002-03-05 15:57:20 +00:00
simonb
fa9c08ab16 Remove HPCMIPS_FLUSHCACHE_XXX debug code. 
Remove old unused exception frame unwind code.
Change a MIPS3 check to a MIPS3_PLUS check.
ANSIfy.
 2002-03-05 15:55:41 +00:00
simonb
278bfc1c02 Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:54:33 +00:00
simonb
351c1c16a6 Add support for MIPS32 and MIPS64 architectures: 
- Use a table-driven CPU detection algorithm instead of multiple
   case statements.
 - Add MIPS32/64 feature detection using the architected CP0 registers
   (from Broadcom Corp).
 - Call MD mips_machdep_cache_config() function if
   __HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
   L2 cache on some ports.
 2002-03-05 15:53:00 +00:00
simonb
ba8e2e82e4 Add support for MIPS32 and MIPS64 architectures: 
- Remove all mmu-related code that may use 32 register on mips32-style
   implementatios and move them to mipsX_subr.S - which is then included
   from mips{3,32,64,5900}_subr.S with various control defines enabled.
 - Remove local cache instruction flags
 - Add badaddr64 (from Broadcom Corp).
 2002-03-05 15:50:59 +00:00
simonb
9ed4fd257f Change a MIPS3 check to a MIPS3_PLUS check. 
XXX: I'm not 100% sure of the intent of this code - it would seem that
 it needs a run-time check of CPU ISA to be completely correct...
 2002-03-05 15:48:31 +00:00
simonb
d62813603c Check userland address and address alignent as two separate checks. 
Fix for when mips_reg_t is 64-bits.
ANSIfy.
 2002-03-05 15:46:51 +00:00
simonb
fe86ad150e Change MIPS3 checks to MIPS3_PLUS checks (XXX - still bogus!). 2002-03-05 15:44:40 +00:00
simonb
c9a3bd8900 Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Add a command to dump cp0 state.
 2002-03-05 15:43:25 +00:00
simonb
9b785c48f3 Cache ops for MIPS32/64 cpus. 2002-03-05 15:42:50 +00:00
simonb
0446046fde Add MIPS32/64 cache setup code (from Broadcom Corp). 2002-03-05 15:42:21 +00:00
simonb
cae6e0e516 Prototypes for MIPS32/64 cache ops. 2002-03-05 15:41:48 +00:00
simonb
0ff59237ca Change a MIPS3 check to a MIPS3_PLUS check (XXX - still bogus!). 2002-03-05 15:41:14 +00:00
simonb
01422aae5c Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:40:10 +00:00
simonb
1d05db445d Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 2002-03-05 15:39:31 +00:00
simonb
934c4ba555 Add support for MIPS32 and MIPS64 architectures: 
Remove the unused PSL_USERCLR and BASEPRI macros.
 2002-03-05 15:38:33 +00:00