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2415 Commits

Author SHA1 Message Date
jym
325494fe33 Modify *ASSERTMSG() so they are now used as variadic macros. The main goal 
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html
 2011-09-27 01:02:33 +00:00
macallan
e841961c7a the cached/not cached stuff doesn't build when both MIPS1 and MIPS3 are 
defined so put it back to #if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
there is no good reason why it can't work on MIPS1 though.
 2011-09-23 23:02:23 +00:00
macallan
a84e510199 make this build again with 32bit paddr_t 
from he@
 2011-09-23 12:42:15 +00:00
macallan
a1ae3c591a remove accidentially committed debug output 2011-09-23 12:34:52 +00:00
macallan
9320bc4780 support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and 
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs
 2011-09-22 05:08:52 +00:00
macallan
f0e7336a90 make the code that deals with mapping regular memory non-cached work again: 
- honour PMAP_NOCACHE
- move the PGC_NOCACHE stuff out of #ifdef PARANOIADIAG
we need this to mmap DMA buffers non-cached on sgimips
 2011-09-21 16:37:54 +00:00
matt
8f6531abed Use UVM_KMF_COLORMATCH and switch to pmap_kenter_pa for vmapbuf/vunmapbuf. 2011-09-01 06:41:38 +00:00
bouyer
b133a35393 There are non-writable bits in MIPS_COP_0_TLB_HI between ASID and VPN, so 
mips3_cp0_tlb_entry_hi_probe() returns a value with some 0 in the low 12 bits.
Thus the computed mips_vm_maxuser_address is wrong. Fix by oring PAGE_MASK to
return value of mips3_cp0_tlb_entry_hi_probe().
 2011-08-27 16:54:14 +00:00
bouyer
62c4d5a467 Add pmon (firmware used by loongson2-based systems and maybe others) support, 
from OpenBSD.
This includes code to call back pmon routines from a 64bit kernel,
as well code to read pmon arguments and variables.
 2011-08-27 13:34:29 +00:00
bouyer
4c44c335c5 loongson2f support: 
- Add some loongson2 definitions to cpuregs.h, from OpenBSD
- Make sure that the at register is useable before every jump register
  instruction (exept when register is k0 or k1) because -mfix-loongson2f-btb
  needs the at register for its workaround
- add code to mips_fixup.c to handle the instructions added by
  -mfix-loongson2f-btb
- Add a ls2-specific tlb miss handler: it doesn't have separate handler
  for the xtlbmiss exeption.
- Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong
  register)
 2011-08-27 13:23:52 +00:00
bouyer
ad05e3fb85 Loongson2f support: 
- make the 'struct bonito_config' const, so that it can be in kernel
  text instead of data.
- Add a bc_attach_hook to struct bonito_config, to be used as pc_attach_hook
  if not NULL.
- Add some LS2-specific register defines (LS2f uses a modified bonito64).
 2011-08-27 12:59:16 +00:00
dyoung
bf9e39452b Use humanize_number() instead of the buggy code that GCC 4.5 caught. 
Compiles.  Not tested.
 2011-08-25 02:36:03 +00:00
matt
b6945981e5 When using 16KB pages in a 64 bit kernel, the amount of address space our page 
table can address can be larger than the amount of address space the CPU
implementation supports.  This change limits the amount address space to what
the CPU implementation provides.
 2011-08-24 16:01:53 +00:00
matt
e4980d209b On N32 kernels, cast offset to (intptr_t) to shrink it back to 32-bits. 2011-08-24 15:11:52 +00:00
oki
a69c375f9d make compile with options RT3050. 2011-08-23 08:10:08 +00:00
matt
42dd23afed Change bcond/BCOND to regimm/REGIMM to better match the MIPS nomenclature. 2011-08-18 21:04:23 +00:00
matt
f82a28e694 Redo mips_fixup so that it can handle indirect loads and deal with loongson2 
extra instructions.
 2011-08-17 14:39:59 +00:00
matt
47d9241c1a emulate the special3 opcode LX (lwx, ldx, lhx, lbux) instructions. 2011-08-17 06:59:28 +00:00
matt
f35867174b Add support for the MIPS DSP ASE (as a second PCU). 2011-08-16 06:58:15 +00:00
matt
6c946bd00a Only jump through t9/ra (or k0) to help avoid hitting 
the Loongson2 jump problem.
 2011-08-16 06:55:11 +00:00
matt
22c9b287d1 Deal with RTMEMSIZE no longer being defined 2011-08-03 17:34:27 +00:00
matt
e99aca1b8b Add some defintions for SYSCTL_CFG0 2011-08-03 16:27:15 +00:00
matt
df230b318d Deal with RA_CONSOLE_EARLY a little more sanely 2011-08-03 16:26:53 +00:00
matt
cd13c53f92 Clear the BTB on user->kernel entry on Loongson2 2011-08-02 05:13:21 +00:00
matt
c55f1d7523 Add Loongson2 DIAG register definitions (partial) 2011-08-02 05:12:32 +00:00
cliff
136422be68 CFI NOR support for mips/ralink 2011-08-02 03:38:48 +00:00
matt
0fb6e91c9f Use <sys/ for bus.h and intr.h 2011-08-01 23:01:40 +00:00
matt
1a16d9577d Support using MEMSIZE 2011-07-31 23:10:58 +00:00
matt
30893a9102 Add support for a loongson2_subr.S. This is needed since that chip needs 
special handling to manually flush the ITLB on TLB updates.
 2011-07-31 15:39:28 +00:00
matt
e642dbad13 Add CPU_MIPS_LOONGSON2 flag (rather defining a CPU_ARCH_MIPS3_LOONGSON2). 
This is much less intrusive and disruptive.
 2011-07-31 15:36:28 +00:00
matt
8610b72b32 Add define for loongson2 DIAG register 2011-07-31 15:35:04 +00:00
matt
0062f2f291 Bring forward from matt-nb5-mips64. Support for Ralink RT3883 MIPS 74K SoC 
from CradlePoint Technology.
 2011-07-28 15:38:48 +00:00
dyoung
75ccda5a51 Don't set the iobase and iosize members of pcmciabus_attach_args because 
they're not used in any meaningful way.
 2011-07-26 22:52:47 +00:00
macallan
01485d66fb #include "opt_cputype.h" 
for ENABLE_MIPS_16KB_PAGE
 2011-07-21 23:03:39 +00:00
joerg
3eb244d801 Retire varargs.h support. Move machine/stdarg.h logic into MI 
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.
 2011-07-17 20:54:30 +00:00
dyoung
0e0deeb06f Switch MIPS and MIPS-ish architectures to new-style <sys/bus.h>. This 
involves moving some inline bus_space(9) implementation into .c files.
 2011-07-17 01:36:50 +00:00
dyoung
e72ff6f361 Repair device_t/softc so that this compiles. 2011-07-17 01:29:25 +00:00
matt
d897a1e969 Remove out-of-date KASSERT 2011-07-14 22:31:22 +00:00
matt
d1cae3a2f6 cleanup <machine/*.h> includes 2011-07-10 23:32:03 +00:00
matt
9636e80449 More <machine/ include cleanup 2011-07-10 23:21:58 +00:00
matt
b6185cbde2 Fix machine/ includes 2011-07-10 23:13:22 +00:00
matt
31586d2cd5 Add athers_get_uart_freq() (since AR7240 uses the ref_clk, not the bus_clk). 
Add little endian bus_space_tag for arbus.
Add EHCI attachment for arbus.
 2011-07-10 06:26:02 +00:00
matt
fa40faf65a Cleanup machine includes 2011-07-10 06:24:18 +00:00
matt
d218a6ab0a Default to DB_ELF_SYMBOLS and DB_ELFSIZE 32 2011-07-09 16:58:04 +00:00
matt
47e061265c Add a common version of this for those port which use the generic mips 
<machine/pci_machdep.h>
 2011-07-09 15:57:39 +00:00
dyoung
6b796b19da Just #include <sys/bus.h> instead of <machine/bus_dma.h>, which is going 
away, soon.
 2011-07-08 19:10:14 +00:00
dyoung
a8f6593d47 Use <sys/bus.h> not <machine/bus.h>. 2011-07-08 18:49:27 +00:00
matt
729b0b87d7 Add extu_fraclm and extu_frachm 2011-07-08 05:55:23 +00:00
matt
81af42b2d5 Include <sys/cdefs.h> to get __GNUC_PREREQ__ 2011-07-07 22:52:48 +00:00
matt
2be346e54d If GCC 4.1 or newer (or clang), use __LDBL__*__ builtins otherwise if C99 
use hex floating point.
 2011-07-07 17:29:31 +00:00