Add support for the MIPS DSP ASE (as a second PCU).
This commit is contained in:
matt
parent
6c946bd00a
commit
f35867174b
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@ -1,4 +1,4 @@
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# $NetBSD: files.mips,v 1.71 2011/07/31 15:39:28 matt Exp $
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# $NetBSD: files.mips,v 1.72 2011/08/16 06:58:15 matt Exp $
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#
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defflag opt_cputype.h NOFPU FPEMUL
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@ -47,6 +47,7 @@ file arch/mips/mips/pmap_segtab.c
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file arch/mips/mips/pmap_tlb.c
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file arch/mips/mips/trap.c # trap handlers
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file arch/mips/mips/syscall.c # syscall entries
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file arch/mips/mips/mips_dsp.c mips32r2 | mips64r2
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file arch/mips/mips/mips_fixup.c
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file arch/mips/mips/mips_fpu.c
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file arch/mips/mips/mips_machdep.c
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.104 2011/07/31 15:36:28 matt Exp $ */
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/* $NetBSD: cpu.h,v 1.105 2011/08/16 06:58:15 matt Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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@ -104,6 +104,8 @@ struct cpu_info {
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volatile u_int ci_softints;
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struct evcnt ci_ev_fpu_loads; /* fpu load counter */
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struct evcnt ci_ev_fpu_saves; /* fpu save counter */
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struct evcnt ci_ev_dsp_loads; /* dsp load counter */
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struct evcnt ci_ev_dsp_saves; /* dsp save counter */
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struct evcnt ci_ev_tlbmisses;
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/*
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@ -282,6 +284,7 @@ extern struct mips_options mips_options;
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#define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */
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#define CPU_MIPS_LOONGSON2 0x4000
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#define MIPS_NOT_SUPP 0x8000
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#define CPU_MIPS_HAVE_DSP 0x10000
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#endif /* !_LOCORE */
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@ -300,6 +303,7 @@ extern struct mips_options mips_options;
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# define MIPS_HAS_CLOCK 0
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# define MIPS_HAS_LLSC 0
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# define MIPS_HAS_LLADDR 0
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# define MIPS_HAS_DSP 0
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#elif defined(MIPS3) || defined(MIPS4)
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@ -322,6 +326,7 @@ extern struct mips_options mips_options;
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# define MIPS_HAS_LLSC (mips_options.mips_has_llsc)
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# endif /* _LOCORE */
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# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
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# define MIPS_HAS_DSP 0
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#elif defined(MIPS32)
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@ -336,6 +341,7 @@ extern struct mips_options mips_options;
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# define MIPS_HAS_CLOCK 1
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# define MIPS_HAS_LLSC 1
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# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
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# define MIPS_HAS_DSP 0
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#elif defined(MIPS32R2)
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@ -350,6 +356,7 @@ extern struct mips_options mips_options;
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# define MIPS_HAS_CLOCK 1
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# define MIPS_HAS_LLSC 1
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# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
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# define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
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#elif defined(MIPS64)
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@ -364,6 +371,7 @@ extern struct mips_options mips_options;
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# define MIPS_HAS_CLOCK 1
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# define MIPS_HAS_LLSC 1
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# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
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# define MIPS_HAS_DSP 0
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#elif defined(MIPS64R2)
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@ -378,6 +386,7 @@ extern struct mips_options mips_options;
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# define MIPS_HAS_CLOCK 1
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# define MIPS_HAS_LLSC 1
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# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
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# define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
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#endif
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@ -388,6 +397,7 @@ extern struct mips_options mips_options;
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#define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu)
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#define MIPS_HAS_LLSC (mips_options.mips_has_llsc)
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#define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
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# define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
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/* This test is ... rather bogus */
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#define CPUISMIPS3 ((mips_options.mips_cpu_arch & \
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@ -621,12 +631,21 @@ int ustore_uint32_isync(void *, uint32_t);
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void netintr(void);
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int kdbpeek(vaddr_t);
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/* mips_dsp.c */
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void dsp_init(void);
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void dsp_discard(void);
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void dsp_load(void);
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void dsp_save(void);
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bool dsp_used_p(void);
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extern const pcu_ops_t mips_dsp_ops;
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/* mips_fpu.c */
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void fpu_init(void);
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void fpu_discard(void);
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void fpu_load(void);
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void fpu_save(void);
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bool fpu_used_p(void);
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extern const pcu_ops_t mips_fpu_ops;
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/* mips_machdep.c */
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void dumpsys(void);
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@ -1,4 +1,4 @@
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/* $NetBSD: mipsNN.h,v 1.4 2006/03/20 18:31:29 gdamore Exp $ */
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/* $NetBSD: mipsNN.h,v 1.5 2011/08/16 06:58:15 matt Exp $ */
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/*
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* Copyright 2000, 2001
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@ -233,7 +233,13 @@
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/* "M" (R): Configuration Register 4 present. */
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#define MIPSNN_CFG3_M 0x80000000
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/* "DSPP" (R): DSPP ASE extension present. */
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/* "ULRP" (R): UserLocal register is implemented. */
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#define MIPSNN_CFG3_ULRP 0x00002000
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/* "DSP2P" (R): DSP v2 ASE extension present. */
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#define MIPSNN_CFG3_DSP2P 0x00000800
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/* "DSPP" (R): DSP ASE extension present. */
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#define MIPSNN_CFG3_DSPP 0x00000400
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/* "LPA" (R): Large physical addresses implemented. (MIPS64 rev 2 only). */
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@ -1,4 +1,4 @@
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/* $NetBSD: pcb.h,v 1.23 2011/02/20 07:45:47 matt Exp $ */
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/* $NetBSD: pcb.h,v 1.24 2011/08/16 06:58:15 matt Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -60,6 +60,7 @@ struct pcb {
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void * pcb_onfault; /* for copyin/copyout faults */
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uint32_t pcb_ppl; /* previous priority level */
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struct fpreg pcb_fpregs; /* saved floating point registers */
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struct dspreg pcb_dspregs; /* saved DSP registers */
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struct pcb_faultinfo pcb_faultinfo;
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};
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@ -1,4 +1,4 @@
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/* $NetBSD: reg.h,v 1.14 2011/02/08 20:20:19 rmind Exp $ */
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/* $NetBSD: reg.h,v 1.15 2011/08/16 06:58:15 matt Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -50,6 +50,10 @@ struct fpreg {
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mips_fpreg_t r_regs[33];
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};
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struct dspreg {
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mips_reg_t r_regs[8];
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};
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#if defined(__mips_n32) || defined(__mips_n64)
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struct fpreg_oabi {
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int32_t r_regs[33];
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@ -1,4 +1,4 @@
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/* $NetBSD: regnum.h,v 1.10 2011/02/08 20:20:19 rmind Exp $ */
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/* $NetBSD: regnum.h,v 1.11 2011/08/16 06:58:15 matt Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -108,7 +108,7 @@
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#define _R_CAUSE 36
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#define _R_PC 37
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#define _FPBASE 38
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#define _FPBASE (_R_PC + 1)
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#define _R_F0 (_FPBASE+0)
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#define _R_F1 (_FPBASE+1)
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#define _R_F2 (_FPBASE+2)
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@ -142,3 +142,12 @@
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#define _R_F30 (_FPBASE+30)
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#define _R_F31 (_FPBASE+31)
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#define _R_FSR (_FPBASE+32)
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#define _R_DSPBASE (_R_FSR + 1)
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#define _R_MULLO1 (_R_DSPBASE + 0)
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#define _R_MULHI1 (_R_DSPBASE + 1)
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#define _R_MULLO2 (_R_DSPBASE + 2)
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#define _R_MULHI2 (_R_DSPBASE + 3)
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#define _R_MULLO3 (_R_DSPBASE + 4)
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#define _R_MULHI3 (_R_DSPBASE + 5)
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#define _R_DSPCTL (_R_DSPBASE + 6)
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.h,v 1.17 2011/02/20 07:45:47 matt Exp $ */
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/* $NetBSD: trap.h,v 1.18 2011/08/16 06:58:15 matt Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -66,6 +66,7 @@
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#define T_VCEI 14 /* Virtual coherency exception */
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#define T_FPE 15 /* Floating point exception */
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#define T_WATCH 23 /* Watch address reference */
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#define T_DSP 26 /* DSP exception */
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#define T_VCED 31 /* Virtual coherency data */
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#define T_USER 0x20 /* user-mode flag or'ed with type */
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@ -1,4 +1,4 @@
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/* $NetBSD: types.h,v 1.52 2011/06/12 03:35:44 rmind Exp $ */
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/* $NetBSD: types.h,v 1.53 2011/08/16 06:58:15 matt Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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@ -127,7 +127,8 @@ typedef struct label_t {
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#if defined(_KERNEL) || defined(_KMEMUSER)
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#define PCU_FPU 0
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#define PCU_UNIT_COUNT 1
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#define PCU_DSP 1
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#define PCU_UNIT_COUNT 2
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#endif
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typedef __uint64_t __cpuset_t;
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/* $NetBSD: cpu_subr.c,v 1.13 2011/05/02 00:29:54 rmind Exp $ */
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/* $NetBSD: cpu_subr.c,v 1.14 2011/08/16 06:58:15 matt Exp $ */
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/*-
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* Copyright (c) 2010 The NetBSD Foundation, Inc.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.13 2011/05/02 00:29:54 rmind Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.14 2011/08/16 06:58:15 matt Exp $");
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#include "opt_ddb.h"
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#include "opt_multiprocessor.h"
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@ -90,6 +90,13 @@ struct cpu_info cpu_info_store
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#endif
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};
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const pcu_ops_t * const pcu_ops_md_defs[PCU_UNIT_COUNT] = {
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[PCU_FPU] = &mips_fpu_ops,
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#if (MIPS32R2 + MIPS64R2) > 0
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[PCU_DSP] = &mips_dsp_ops,
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#endif
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};
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#ifdef MULTIPROCESSOR
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volatile __cpuset_t cpus_running = 1;
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@ -231,6 +238,12 @@ cpu_attach_common(device_t self, struct cpu_info *ci)
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evcnt_attach_dynamic(&ci->ci_ev_fpu_saves,
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EVCNT_TYPE_MISC, NULL, xname,
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"fpu saves");
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evcnt_attach_dynamic(&ci->ci_ev_dsp_loads,
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EVCNT_TYPE_MISC, NULL, xname,
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"dsp loads");
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evcnt_attach_dynamic(&ci->ci_ev_dsp_saves,
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EVCNT_TYPE_MISC, NULL, xname,
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"dsp saves");
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evcnt_attach_dynamic(&ci->ci_ev_tlbmisses,
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EVCNT_TYPE_TRAP, NULL, xname,
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"tlb misses");
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@ -0,0 +1,200 @@
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/* $NetBSD: mips_dsp.c,v 1.1 2011/08/16 06:58:15 matt Exp $ */
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/*-
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* Copyright (c) 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mips_dsp.c,v 1.1 2011/08/16 06:58:15 matt Exp $");
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#include "opt_multiprocessor.h"
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#include <sys/param.h>
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#include <sys/mutex.h>
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#include <sys/condvar.h>
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#include <sys/cpu.h>
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#include <sys/proc.h>
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#include <sys/lwp.h>
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#include <sys/pcu.h>
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#include <mips/locore.h>
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#include <mips/regnum.h>
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#include <mips/pcb.h>
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static void mips_dsp_state_save(lwp_t *);
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static void mips_dsp_state_load(lwp_t *, bool);
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static void mips_dsp_state_release(lwp_t *);
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const pcu_ops_t mips_dsp_ops = {
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.pcu_id = PCU_DSP,
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.pcu_state_save = mips_dsp_state_save,
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.pcu_state_load = mips_dsp_state_load,
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.pcu_state_release = mips_dsp_state_release
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};
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void
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dsp_discard(void)
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{
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pcu_discard(&mips_dsp_ops);
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}
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void
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dsp_load(void)
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{
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pcu_load(&mips_dsp_ops);
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}
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void
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dsp_save(void)
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{
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pcu_save(&mips_dsp_ops);
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}
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bool
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dsp_used_p(void)
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{
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return pcu_used_p(&mips_dsp_ops);
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}
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void
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mips_dsp_state_save(lwp_t *l)
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{
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struct trapframe * const tf = l->l_md.md_utf;
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struct pcb * const pcb = lwp_getpcb(l);
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mips_reg_t * const dsp = pcb->pcb_dspregs.r_regs;
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uint32_t status;
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/*
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* Don't do anything if the DSP is already off.
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*/
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if ((tf->tf_regs[_R_SR] & MIPS_SR_MX) == 0)
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return;
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l->l_cpu->ci_ev_dsp_saves.ev_count++;
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/*
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* load DSP registers and establish lwp's DSP context.
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*/
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__asm volatile (
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".set push" "\n\t"
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".set mips32r2" "\n\t"
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".set dspr2" "\n\t"
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".set noat" "\n\t"
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".set noreorder" "\n\t"
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"mfc0 %[status], $%[cp0_status]" "\n\t"
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"or %[status], %[mips_sr_mx]" "\n\t"
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"mtc0 %[status], $%[cp0_status]" "\n\t"
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"ehb" "\n\t"
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"mflo %[mullo1], $ac1" "\n\t"
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"mfhi %[mulhi1], $ac1" "\n\t"
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"mflo %[mullo2], $ac2" "\n\t"
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"mfhi %[mulhi2], $ac2" "\n\t"
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"mflo %[mullo3], $ac3" "\n\t"
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"mfhi %[mulhi3], $ac3" "\n\t"
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"rddsp %[dspctl]" "\n\t"
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"xor %[status], %[mips_sr_mx]" "\n\t"
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"mtc0 %[status], $%[cp0_status]" "\n\t"
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"ehb" "\n\t"
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||||
".set pop"
|
||||
: [status] "=&r" (status),
|
||||
[mullo1] "=r"(dsp[_R_MULLO1 - _R_DSPBASE]),
|
||||
[mulhi1] "=r"(dsp[_R_MULHI1 - _R_DSPBASE]),
|
||||
[mullo2] "=r"(dsp[_R_MULLO2 - _R_DSPBASE]),
|
||||
[mulhi2] "=r"(dsp[_R_MULHI2 - _R_DSPBASE]),
|
||||
[mullo3] "=r"(dsp[_R_MULLO3 - _R_DSPBASE]),
|
||||
[mulhi3] "=r"(dsp[_R_MULHI3 - _R_DSPBASE]),
|
||||
[dspctl] "=r"(dsp[_R_DSPCTL - _R_DSPBASE])
|
||||
: [mips_sr_mx] "r"(MIPS_SR_MX),
|
||||
[cp0_status] "n"(MIPS_COP_0_STATUS));
|
||||
}
|
||||
|
||||
void
|
||||
mips_dsp_state_load(lwp_t *l, bool used)
|
||||
{
|
||||
struct trapframe * const tf = l->l_md.md_utf;
|
||||
struct pcb * const pcb = lwp_getpcb(l);
|
||||
mips_reg_t * const dsp = pcb->pcb_dspregs.r_regs;
|
||||
uint32_t status;
|
||||
|
||||
l->l_cpu->ci_ev_dsp_loads.ev_count++;
|
||||
|
||||
/*
|
||||
* If this is the first time the state is being loaded, zero it first.
|
||||
*/
|
||||
if (__predict_false(!used)) {
|
||||
memset(&pcb->pcb_dspregs, 0, sizeof(pcb->pcb_dspregs));
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the DSP when this lwp return to userspace.
|
||||
*/
|
||||
tf->tf_regs[_R_SR] |= MIPS_SR_MX;
|
||||
|
||||
/*
|
||||
* load DSP registers and establish lwp's DSP context.
|
||||
*/
|
||||
__asm volatile (
|
||||
".set push" "\n\t"
|
||||
".set mips32r2" "\n\t"
|
||||
".set dspr2" "\n\t"
|
||||
".set noat" "\n\t"
|
||||
".set noreorder" "\n\t"
|
||||
"mfc0 %[status], $%[cp0_status]" "\n\t"
|
||||
"or %[status], %[mips_sr_mx]" "\n\t"
|
||||
"mtc0 %[status], $%[cp0_status]" "\n\t"
|
||||
"ehb" "\n\t"
|
||||
"mtlo %[mullo1], $ac1" "\n\t"
|
||||
"mthi %[mulhi1], $ac1" "\n\t"
|
||||
"mtlo %[mullo2], $ac2" "\n\t"
|
||||
"mthi %[mulhi2], $ac2" "\n\t"
|
||||
"mtlo %[mullo3], $ac3" "\n\t"
|
||||
"mthi %[mulhi3], $ac3" "\n\t"
|
||||
"wrdsp %[dspctl]" "\n\t"
|
||||
"xor %[status], %[mips_sr_mx]" "\n\t"
|
||||
"mtc0 %[status], $%[cp0_status]" "\n\t"
|
||||
"ehb" "\n\t"
|
||||
".set pop"
|
||||
: [status] "=&r" (status)
|
||||
: [mullo1] "r"(dsp[_R_MULLO1 - _R_DSPBASE]),
|
||||
[mulhi1] "r"(dsp[_R_MULHI1 - _R_DSPBASE]),
|
||||
[mullo2] "r"(dsp[_R_MULLO2 - _R_DSPBASE]),
|
||||
[mulhi2] "r"(dsp[_R_MULHI2 - _R_DSPBASE]),
|
||||
[mullo3] "r"(dsp[_R_MULLO3 - _R_DSPBASE]),
|
||||
[mulhi3] "r"(dsp[_R_MULHI3 - _R_DSPBASE]),
|
||||
[dspctl] "r"(dsp[_R_DSPCTL - _R_DSPBASE]),
|
||||
[mips_sr_mx] "r"(MIPS_SR_MX),
|
||||
[cp0_status] "n"(MIPS_COP_0_STATUS));
|
||||
}
|
||||
|
||||
void
|
||||
mips_dsp_state_release(lwp_t *l)
|
||||
{
|
||||
|
||||
KASSERT(l == curlwp);
|
||||
l->l_md.md_utf->tf_regs[_R_SR] &= ~MIPS_SR_MX;
|
||||
}
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: mips_fpu.c,v 1.5 2011/05/02 00:29:54 rmind Exp $ */
|
||||
/* $NetBSD: mips_fpu.c,v 1.6 2011/08/16 06:58:15 matt Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2010 The NetBSD Foundation, Inc.
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: mips_fpu.c,v 1.5 2011/05/02 00:29:54 rmind Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: mips_fpu.c,v 1.6 2011/08/16 06:58:15 matt Exp $");
|
||||
|
||||
#include "opt_multiprocessor.h"
|
||||
|
||||
|
|
@ -50,18 +50,13 @@ static void mips_fpu_state_save(lwp_t *);
|
|||
static void mips_fpu_state_load(lwp_t *, bool);
|
||||
static void mips_fpu_state_release(lwp_t *);
|
||||
|
||||
static const pcu_ops_t mips_fpu_ops = {
|
||||
const pcu_ops_t mips_fpu_ops = {
|
||||
.pcu_id = PCU_FPU,
|
||||
.pcu_state_save = mips_fpu_state_save,
|
||||
.pcu_state_load = mips_fpu_state_load,
|
||||
.pcu_state_release = mips_fpu_state_release
|
||||
};
|
||||
|
||||
/* XXX */
|
||||
const pcu_ops_t * const pcu_ops_md_defs[PCU_UNIT_COUNT] = {
|
||||
[PCU_FPU] = &mips_fpu_ops
|
||||
};
|
||||
|
||||
void
|
||||
fpu_discard(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: mips_machdep.c,v 1.245 2011/07/31 15:39:29 matt Exp $ */
|
||||
/* $NetBSD: mips_machdep.c,v 1.246 2011/08/16 06:58:15 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 2002 Wasabi Systems, Inc.
|
||||
|
|
@ -112,7 +112,7 @@
|
|||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.245 2011/07/31 15:39:29 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.246 2011/08/16 06:58:15 matt Exp $");
|
||||
|
||||
#define __INTR_PRIVATE
|
||||
#include "opt_cputype.h"
|
||||
|
|
@ -882,11 +882,24 @@ mips32r2_vector_init(const struct splsw *splsw)
|
|||
memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips32r2_tlb_miss,
|
||||
mips32r2_intr_end - mips32r2_tlb_miss);
|
||||
|
||||
/*
|
||||
* Let see if this cpu has DSP V2 ASE...
|
||||
*/
|
||||
uint32_t cp0flags = mips_options.mips_cpu->cpu_cp0flags;
|
||||
if (mipsNN_cp0_config2_read() & MIPSNN_CFG2_M) {
|
||||
const uint32_t cfg3 = mipsNN_cp0_config3_read();
|
||||
if (cfg3 & MIPSNN_CFG3_ULRP) {
|
||||
cp0flags |= MIPS_CP0FL_USERLOCAL;
|
||||
}
|
||||
if (cfg3 & MIPSNN_CFG3_DSP2P) {
|
||||
mips_options.mips_cpu_flags |= CPU_MIPS_HAVE_DSP;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* If this CPU doesn't have a COP0 USERLOCAL register, at the end
|
||||
* of cpu_switch resume overwrite the instructions which update it.
|
||||
*/
|
||||
if (!(mips_options.mips_cpu->cpu_cp0flags & MIPS_CP0FL_USERLOCAL)) {
|
||||
if (!(cp0flags & MIPS_CP0FL_USERLOCAL)) {
|
||||
extern uint32_t mips32r2_cpu_switch_resume[];
|
||||
for (uint32_t *insnp = mips32r2_cpu_switch_resume;; insnp++) {
|
||||
KASSERT(insnp[0] != JR_RA);
|
||||
|
|
@ -1009,11 +1022,25 @@ mips64r2_vector_init(const struct splsw *splsw)
|
|||
memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips64r2_tlb_miss,
|
||||
mips64r2_intr_end - mips64r2_tlb_miss);
|
||||
|
||||
/*
|
||||
* Let see if this cpu has DSP V2 ASE...
|
||||
*/
|
||||
uint32_t cp0flags = mips_options.mips_cpu->cpu_cp0flags;
|
||||
if (mipsNN_cp0_config2_read() & MIPSNN_CFG2_M) {
|
||||
const uint32_t cfg3 = mipsNN_cp0_config3_read();
|
||||
if (cfg3 & MIPSNN_CFG3_ULRP) {
|
||||
cp0flags |= MIPS_CP0FL_USERLOCAL;
|
||||
}
|
||||
if (cfg3 & MIPSNN_CFG3_DSP2P) {
|
||||
mips_options.mips_cpu_flags |= CPU_MIPS_HAVE_DSP;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If this CPU doesn't have a COP0 USERLOCAL register, at the end
|
||||
* of cpu_switch resume overwrite the instructions which update it.
|
||||
*/
|
||||
if (!(mips_options.mips_cpu->cpu_cp0flags & MIPS_CP0FL_USERLOCAL)) {
|
||||
if (!(cp0flags & MIPS_CP0FL_USERLOCAL)) {
|
||||
extern uint32_t mips64r2_cpu_switch_resume[];
|
||||
for (uint32_t *insnp = mips64r2_cpu_switch_resume;; insnp++) {
|
||||
KASSERT(insnp[0] != JR_RA);
|
||||
|
|
@ -1409,6 +1436,9 @@ cpu_identify(device_t dev)
|
|||
else
|
||||
aprint_normal(" Rev. %d", MIPS_PRID_REV(fpu_id));
|
||||
}
|
||||
if (opts->mips_cpu_flags & MIPS_HAS_DSP) {
|
||||
aprint_normal(" and DSPv2");
|
||||
}
|
||||
aprint_normal("\n");
|
||||
|
||||
if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC &&
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: trap.c,v 1.231 2011/04/29 22:08:17 matt Exp $ */
|
||||
/* $NetBSD: trap.c,v 1.232 2011/08/16 06:58:15 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
|
|
@ -39,7 +39,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.231 2011/04/29 22:08:17 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.232 2011/08/16 06:58:15 matt Exp $");
|
||||
|
||||
#include "opt_cputype.h" /* which mips CPU levels do we support? */
|
||||
#include "opt_ddb.h"
|
||||
|
|
@ -111,7 +111,7 @@ const char * const trap_names[] = {
|
|||
"r4k watch",
|
||||
"mipsNN machine check",
|
||||
"reserved 25",
|
||||
"reserved 26",
|
||||
"DSP exception",
|
||||
"reserved 27",
|
||||
"reserved 28",
|
||||
"reserved 29",
|
||||
|
|
@ -599,6 +599,15 @@ trap(uint32_t status, uint32_t cause, vaddr_t vaddr, vaddr_t pc,
|
|||
ksi.ksi_code = TRAP_BRKPT;
|
||||
break; /* SIGNAL */
|
||||
}
|
||||
case T_DSP+T_USER:
|
||||
#if (MIPS32R2 + MIPS64R2) > 0
|
||||
if (MIPS_HAS_DSP) {
|
||||
dsp_load();
|
||||
userret(l);
|
||||
return; /* GEN */
|
||||
}
|
||||
#endif /* (MIPS32R3 + MIPS64R2) > 0 */
|
||||
/* FALLTHROUGH */
|
||||
case T_RES_INST+T_USER:
|
||||
case T_COP_UNUSABLE+T_USER:
|
||||
#if !defined(FPEMUL) && !defined(NOFPU)
|
||||
|
|
|
|||
Loading…
Reference in New Issue