Only jump through t9/ra (or k0) to help avoid hitting
the Loongson2 jump problem.
This commit is contained in:
matt
parent
058f310f02
commit
6c946bd00a
@ -1,4 +1,4 @@
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/* $NetBSD: bds_emul.S,v 1.4 2011/02/26 11:27:59 tsutsui Exp $ */
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/* $NetBSD: bds_emul.S,v 1.5 2011/08/16 06:55:11 matt Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -66,8 +66,8 @@ LEAF(mips_emul_branchdelayslot)
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srl t0, a0, 26-PTR_SCALESHIFT
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andi t0, 0x3F << PTR_SCALESHIFT
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PTR_L t0, bcemul_optbl(t0)
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j t0
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PTR_L t9, bcemul_optbl(t0)
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jr t9
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.rdata
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bcemul_optbl:
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@ -173,7 +173,7 @@ bcemul_immed_prologue:
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REG_PROLOGUE
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REG_L v0, TF_REG_ZERO(t1) # load source
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REG_EPILOGUE
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j ra # execute the instruction
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jr ra # execute the instruction
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bcemul_uimmed_prologue:
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srl t1, a0, 21-REG_SCALESHIFT # rs (source)
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@ -186,7 +186,7 @@ bcemul_uimmed_prologue:
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REG_PROLOGUE
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REG_L v0, TF_REG_ZERO(t1) # load source
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REG_EPILOGUE
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j ra
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jr ra
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#ifndef __mips_o32
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bcemul_daddi:
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@ -441,11 +441,12 @@ bcemul_special:
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andi t0, a0, 0x3f # get special code
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sll t1, t0, 3 # calculate index in specialop
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sll t0, PTR_SCALESHIFT
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PTR_LA t9, bcemul_special_op(t1)
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PTR_L t0, bcemul_specialtbl(t0)
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j t0
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PTR_LA t0, bcemul_special_op(t1)
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PTR_L t9, bcemul_specialtbl(t0)
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jr t9
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bcemul_special_3op_prologue:
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move t9, t0
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srl t0, a0, 21-REG_SCALESHIFT # rs (source1)
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srl t1, a0, 16-REG_SCALESHIFT # rt (source2)
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srl t2, a0, 11-REG_SCALESHIFT # rd (dest)
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@ -459,9 +460,10 @@ bcemul_special_3op_prologue:
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REG_L v0, TF_REG_ZERO(t0) # load source1
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REG_L v1, TF_REG_ZERO(t1) # load source2
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REG_EPILOGUE
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j t9
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jr t9
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bcemul_special_2src_prologue:
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move t9, t0
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srl t0, a0, 21-REG_SCALESHIFT # rs (source1)
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srl t1, a0, 16-REG_SCALESHIFT # rt (source2)
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andi t0, REG_REGMASK
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@ -472,9 +474,10 @@ bcemul_special_2src_prologue:
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REG_L v0, TF_REG_ZERO(t0) # load source1
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REG_L v1, TF_REG_ZERO(t1) # load source2
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REG_EPILOGUE
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j t9
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jr t9
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bcemul_special_genshift:
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move t9, t0
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srl t1, a0, 16-REG_SCALESHIFT # rt (source)
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srl t2, a0, 11-REG_SCALESHIFT # rd (dest)
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srl v1, a0, 6 # sa
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@ -606,7 +609,7 @@ bcemul_done:
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REG_L ra, CALLFRAME_RA(sp)
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REG_L s0, CALLFRAME_S0(sp)
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PTR_ADDU sp, CALLFRAME_SIZ
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j ra
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jr ra
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/*
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* Send SIGILL, SIGFPE.
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@ -1,4 +1,4 @@
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/* $NetBSD: copy.S,v 1.14 2011/07/06 09:27:35 matt Exp $ */
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/* $NetBSD: copy.S,v 1.15 2011/08/16 06:55:11 matt Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -499,9 +499,9 @@ LEAF(ustore_uint32_isync)
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PTR_S v0, PCB_ONFAULT(v1)
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INT_S a1, 0(a0) # store word
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PTR_S zero, PCB_ONFAULT(v1)
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PTR_L v1, _C_LABEL(mips_cache_ops) + MIPSX_FLUSHICACHE
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PTR_L t9, _C_LABEL(mips_cache_ops) + MIPSX_FLUSHICACHE
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move v0, zero
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j v1 # NOTE: must not clobber v0!
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j t9 # NOTE: must not clobber v0!
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li a1, 4 # size of word
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END(ustore_uint32_isync)
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@ -1,4 +1,4 @@
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/* $NetBSD: fp.S,v 1.43 2011/02/26 15:41:32 tsutsui Exp $ */
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/* $NetBSD: fp.S,v 1.44 2011/08/16 06:55:11 matt Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -151,29 +151,29 @@ NESTED(mips_emul_fp, CALLFRAME_SIZ, ra)
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single_op:
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andi v0, a0, 0x3F # get FUNC field
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sll v0, v0, PTR_SCALESHIFT
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PTR_L v0, func_single_tbl(v0)
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j v0
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PTR_L t9, func_single_tbl(v0)
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j t9
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double_op:
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andi v0, a0, 0x3F # get FUNC field
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sll v0, v0, PTR_SCALESHIFT
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PTR_L v0, func_double_tbl(v0)
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j v0
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PTR_L t9, func_double_tbl(v0)
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j t9
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single_fixed_op:
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andi v0, a0, 0x3F # get FUNC field
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sll v0, v0, PTR_SCALESHIFT
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PTR_L v0, func_single_fixed_tbl(v0)
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j v0
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PTR_L t9, func_single_fixed_tbl(v0)
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j t9
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long_fixed_op:
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andi v0, a0, 0x3F # get FUNC field
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sll v0, v0, PTR_SCALESHIFT
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PTR_L v0, func_long_fixed_tbl(v0)
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j v0
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PTR_L t9, func_long_fixed_tbl(v0)
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j t9
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#if (defined(__mips_n32) || defined(__mips_n64)) && 0
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paired_single_op:
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andi v0, a0, 0x3F # get FUNC field
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sll v0, v0, PTR_SCALESHIFT
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PTR_L v0, func_paired_single_tbl(v0)
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j v0
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PTR_L t9, func_paired_single_tbl(v0)
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j t9
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#else
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#define paired_single_op ill
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#endif
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@ -766,8 +766,8 @@ ctoc1:
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branchc1:
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srl v0, a0, 16 - PTR_SCALESHIFT
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andi v0, v0, 0x1f << PTR_SCALESHIFT
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PTR_L v0, branchc1_tbl(v0)
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j v0
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PTR_L t9, branchc1_tbl(v0)
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j t9
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.rdata
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branchc1_tbl:
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.S,v 1.187 2011/04/06 13:30:33 tsutsui Exp $ */
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/* $NetBSD: locore.S,v 1.188 2011/08/16 06:55:12 matt Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -332,7 +332,7 @@ softint_cleanup:
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#if IPL_SCHED != IPL_HIGH
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j _C_LABEL(splhigh_noprof)
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#else
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j ra
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jr ra
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#endif
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PTR_ADDU sp, CALLFRAME_SIZ
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@ -412,7 +412,7 @@ NESTED(softint_fast_dispatch, CALLFRAME_SIZ, ra)
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/*
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* Almost everything (all except sp) is restored so we can return.
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*/
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j ra
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jr ra
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PTR_ADDU sp, CALLFRAME_SIZ
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END(softint_fast_dispatch)
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#endif /* __HAVE_FAST_SOFTINTS */
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@ -435,7 +435,7 @@ LEAF(lwp_oncpu)
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li v0, 0 # load success
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1:
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PTR_S zero, PCB_ONFAULT(t0) # reset fault handler
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j ra # and return.
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jr ra # and return.
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nop
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END(lwp_oncpu)
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@ -468,7 +468,7 @@ LEAF(savectx)
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REG_S ra, PCB_CONTEXT+SF_REG_RA(a0)
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REG_S v0, PCB_CONTEXT+SF_REG_SR(a0)
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REG_EPILOGUE
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j ra
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jr ra
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move v0, zero
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END(savectx)
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@ -497,7 +497,7 @@ LEAF(setjmp)
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REG_S ra, SF_REG_RA(a0)
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REG_S v0, SF_REG_SR(a0)
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REG_EPILOGUE
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j ra
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jr ra
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move v0, zero
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END(setjmp)
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@ -523,7 +523,7 @@ LEAF(longjmp)
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REG_EPILOGUE
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mtc0 v0, MIPS_COP_0_STATUS
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COP0_SYNC
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j ra
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jr ra
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li v0, 1
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END(longjmp)
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#endif
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@ -538,7 +538,7 @@ END(longjmp)
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*/
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LEAF_NOPROFILE(mips_cp0_cause_read)
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mfc0 v0, MIPS_COP_0_CAUSE
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j ra
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jr ra
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nop
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END(mips_cp0_cause_read)
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@ -560,7 +560,7 @@ END(mips_cp0_cause_write)
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*/
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LEAF(mips_cp0_status_read)
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mfc0 v0, MIPS_COP_0_STATUS
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j ra
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jr ra
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nop
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END(mips_cp0_status_read)
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@ -731,7 +731,7 @@ LEAF(mips_pagecopy)
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bgtz a2, 1b
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PTR_ADDU a0, 8*SZREG
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.set pop
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j ra
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jr ra
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nop
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END(mips_pagecopy)
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@ -755,7 +755,7 @@ LEAF(mips_pagezero)
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bgtz a1,1b
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PTR_ADDU a0, 8*SZREG
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.set pop
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j ra
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jr ra
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nop
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END(mips_pagezero)
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@ -813,7 +813,7 @@ XNESTED(logstacktrace)
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REG_L ra, XCALLFRAME_RA(sp)
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PTR_ADDU sp, XCALLFRAME_SIZ
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j ra
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jr ra
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nop
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#undef XCALLFRAME_RA
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#undef XCALLFRAME_SIZ
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_mips3.S,v 1.101 2011/07/31 15:39:29 matt Exp $ */
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/* $NetBSD: locore_mips3.S,v 1.102 2011/08/16 06:55:11 matt Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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@ -158,7 +158,7 @@ XLEAF(mips64_wbflush)
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XLEAF(mips64r2_wbflush)
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nop
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sync
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j ra
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jr ra
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nop
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END(mips3_wbflush)
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@ -185,7 +185,7 @@ LEAF(mips_wait_idle)
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nop
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nop
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nop
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j ra
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jr ra
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nop
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END(mips_wait_idle)
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@ -196,7 +196,7 @@ END(mips_wait_idle)
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*/
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LEAF(mips3_cp0_compare_read)
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mfc0 v0, MIPS_COP_0_COMPARE
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j ra
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jr ra
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nop
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END(mips3_cp0_compare_read)
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@ -217,7 +217,7 @@ END(mips3_cp0_compare_write)
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*/
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LEAF(mips3_cp0_config_read)
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mfc0 v0, MIPS_COP_0_CONFIG
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j ra
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jr ra
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nop
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END(mips3_cp0_config_read)
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@ -245,7 +245,7 @@ END(mips3_cp0_config_write)
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*/
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LEAF(mipsNN_cp0_config1_read)
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mfc0 v0, MIPS_COP_0_CONFIG, 1
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j ra
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jr ra
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nop
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END(mipsNN_cp0_config1_read)
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@ -266,7 +266,7 @@ END(mipsNN_cp0_config1_write)
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*/
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LEAF(mipsNN_cp0_config2_read)
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mfc0 v0, MIPS_COP_0_CONFIG, 2
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j ra
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jr ra
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nop
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END(mipsNN_cp0_config2_read)
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@ -277,7 +277,7 @@ END(mipsNN_cp0_config2_read)
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*/
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LEAF(mipsNN_cp0_config3_read)
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mfc0 v0, MIPS_COP_0_CONFIG, 3
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j ra
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jr ra
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nop
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END(mipsNN_cp0_config3_read)
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@ -407,7 +407,7 @@ END(mipsNN_cp0_watchhi_write)
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* Set the value of the CP0 USERLOCAL (TLB_CONTEXT, select 2) register.
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*/
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LEAF(mipsNN_cp0_hwrena_write)
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j ra
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jr ra
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mtc0 a0, MIPS_COP_0_HWRENA
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END(mipsNN_cp0_hwrena_write)
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@ -416,7 +416,7 @@ END(mipsNN_cp0_hwrena_write)
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* Set the value of the CP0 USERLOCAL (TLB_CONTEXT, select 2) register.
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*/
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LEAF(mipsNN_cp0_userlocal_write)
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j ra
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jr ra
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_MTC0 a0, MIPS_COP_0_TLB_CONTEXT, 2
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END(mipsNN_cp0_userlocal_write)
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#endif /* (MIPS32R2 + MIPS64R2) > 0 */
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@ -430,7 +430,7 @@ END(mipsNN_cp0_userlocal_write)
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*/
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LEAF(mips3_cp0_count_read)
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mfc0 v0, MIPS_COP_0_COUNT
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j ra
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jr ra
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nop
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END(mips3_cp0_count_read)
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WEAK_ALIAS(cpu_counter32, mips3_cp0_count_read)
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@ -452,7 +452,7 @@ END(mips3_cp0_count_write)
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*/
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LEAF(mips3_cp0_wired_read)
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mfc0 v0, MIPS_COP_0_TLB_WIRED
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j ra
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jr ra
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nop
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END(mips3_cp0_wired_read)
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@ -598,7 +598,7 @@ LEAF(badaddr64)
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mtc0 t0, MIPS_COP_0_STATUS # Restore KX
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COP0_SYNC
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PTR_S zero, PCB_ONFAULT(v1)
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j ra
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jr ra
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move v0, zero # made it w/o errors
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END(badaddr64)
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@ -606,7 +606,7 @@ LEAF(baderr64)
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mtc0 t0, MIPS_COP_0_STATUS # Restore KX
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COP0_SYNC
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PTR_S zero, PCB_ONFAULT(v1)
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j ra
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jr ra
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li v0, -1
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END(baderr64)
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@ -638,7 +638,7 @@ LEAF(mips3_cp0_tlb_entry_hi_probe)
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srl v0, v0, 0
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#endif
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#endif /* __mips_o32 */
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j ra
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jr ra
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nop
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END(mips3_cp0_tlb_entry_hi_probe)
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@ -666,7 +666,7 @@ LEAF(mips3_cp0_tlb_entry_lo_probe)
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srl v0, v0, 0
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#endif
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#endif /* __mips_o32 */
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j ra
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jr ra
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nop
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END(mips3_cp0_tlb_entry_lo_probe)
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@ -1,4 +1,4 @@
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/* $NetBSD: mipsX_subr.S,v 1.52 2011/08/02 05:13:21 matt Exp $ */
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/* $NetBSD: mipsX_subr.S,v 1.53 2011/08/16 06:55:12 matt Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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@ -334,6 +334,10 @@
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*/
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VECTOR(MIPSX(tlb_miss), unknown)
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.set noat
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#ifdef MIPS3_LOONGSON2
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li k0, MIPS_DIAG_BTB_CLEAR
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mtc0 k0, MIPS_COP_0_DIAG
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#endif
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_MFC0 k0, MIPS_COP_0_BAD_VADDR #00: k0=bad address
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lui k1, %hi(CPUVAR(PMAP_SEG0TAB)) #01: k1=hi of seg0tab
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bltz k0, MIPSX(kernelfault) #02: k0<0 -> 4f (kernel fault)
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@ -360,9 +364,11 @@ MIPSX(tlb_miss_common):
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_SLL k1, WIRED_SHIFT #14: chop top 2 bits (part 2a)
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_SRL k1, WIRED_SHIFT #15: chop top 2 bits (part 2b)
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_MTC0 k1, MIPS_COP_0_TLB_LO1 #16: lo1 is loaded
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#ifndef MIPS3_LOONGSON2
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sll $0, $0, 3 #17: standard nop (ehb)
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#ifdef MIPS3
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nop #18: extra nop for QED5230
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#endif
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#endif
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tlbwr #19: write to tlb
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sll $0, $0, 3 #1a: standard nop (ehb)
|
||||
@ -434,7 +440,7 @@ VECTOR(MIPSX(cache), unknown)
|
||||
li k1, MIPS_KSEG1_START #04
|
||||
or k0, k1 #05
|
||||
lui k1, %hi(CPUVAR(CURLWP)) #06: k1=hi of curlwp
|
||||
j k0 #07
|
||||
jr k0 #07
|
||||
PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #08: k1=lo of curlwp
|
||||
_VECTOR_END(MIPSX(cache))
|
||||
|
||||
@ -475,7 +481,7 @@ VECTOR(MIPSX(exception), unknown)
|
||||
# we dont have to shift.
|
||||
PTR_L k0, 0(k0) #09: get the function address
|
||||
lui k1, %hi(CPUVAR(CURLWP)) #0a: k1=hi of curlwp
|
||||
j k0 #0b: jump to the function
|
||||
jr k0 #0b: jump to the function
|
||||
PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #0c: k1=lo of curlwp
|
||||
nop #0d
|
||||
nop #0e
|
||||
@ -510,7 +516,7 @@ VECTOR(MIPSX(intr), unknown)
|
||||
PTR_LA k0, MIPSX(kern_intr) #07: nope, kernel intr
|
||||
1:
|
||||
lui k1, %hi(CPUVAR(CURLWP)) #09: k1=hi of curlwp
|
||||
j k0 #0a: jump to the function
|
||||
jr k0 #0a: jump to the function
|
||||
PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #0b: k1=lo of curlwp
|
||||
.set at
|
||||
_VECTOR_END(MIPSX(intr))
|
||||
@ -995,6 +1001,10 @@ NESTED_NOPROFILE(MIPSX(user_reserved_insn), CALLFRAME_SIZ, ra)
|
||||
/*
|
||||
* Save a minimum of registers to see if this is rdhwr $3,$29
|
||||
*/
|
||||
#ifdef MIPS3_LOONGSON2
|
||||
li k0, MIPS_DIAG_BTB_CLEAR
|
||||
mtc0 k0, MIPS_COP_0_DIAG
|
||||
#endif
|
||||
/* K1 already has CURLWP */
|
||||
PTR_L k0, L_PCB(k1) # XXXuvm_lwp_getuarea
|
||||
PTR_ADDU k0, USPACE - TF_SIZ - CALLFRAME_SIZ
|
||||
@ -1091,13 +1101,13 @@ MIPSX(user_gen_exception_common):
|
||||
_MFC0 a3, MIPS_COP_0_EXC_PC # 4th arg is exception PC
|
||||
REG_S t8, CALLFRAME_SIZ+TF_REG_T8(k0) # will be MIPS_CURLWP
|
||||
REG_S t9, CALLFRAME_SIZ+TF_REG_T9(k0)
|
||||
REG_S v0, CALLFRAME_SIZ+TF_REG_MULLO(k0)
|
||||
REG_S v1, CALLFRAME_SIZ+TF_REG_MULHI(k0)
|
||||
REG_S gp, CALLFRAME_SIZ+TF_REG_GP(k0)
|
||||
REG_S sp, CALLFRAME_SIZ+TF_REG_SP(k0)
|
||||
REG_S s8, CALLFRAME_SIZ+TF_REG_S8(k0)
|
||||
REG_S ra, CALLFRAME_SIZ+TF_REG_RA(k0)
|
||||
REG_S a0, CALLFRAME_SIZ+TF_REG_SR(k0)
|
||||
REG_S v0, CALLFRAME_SIZ+TF_REG_MULLO(k0)
|
||||
REG_S v1, CALLFRAME_SIZ+TF_REG_MULHI(k0)
|
||||
REG_S a3, CALLFRAME_SIZ+TF_REG_EPC(k0)
|
||||
#ifdef __GP_SUPPORT__
|
||||
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
|
||||
@ -1873,7 +1883,7 @@ LEAF(MIPSX(tlb_read_indexed))
|
||||
PTR_S t3, TLBMASK_HI(a1)
|
||||
INT_S ta0, TLBMASK_LO0(a1)
|
||||
INT_S ta1, TLBMASK_LO1(a1)
|
||||
j ra
|
||||
jr ra
|
||||
INT_S t2, TLBMASK_MASK(a1)
|
||||
END(MIPSX(tlb_read_indexed))
|
||||
|
||||
@ -2299,6 +2309,10 @@ MIPSX(user_return):
|
||||
REG_L s6, CALLFRAME_SIZ+TF_REG_S6(sp) # $22
|
||||
REG_L s7, CALLFRAME_SIZ+TF_REG_S7(sp) # $23
|
||||
REG_L s8, CALLFRAME_SIZ+TF_REG_S8(sp) # $30
|
||||
#ifdef MIPS3_LOONGSON2
|
||||
li t0, (MIPS_DIAG_BTB_CLEAR|MIPS_DIAG_ITLB_CLEAR)
|
||||
mtc0 t0, MIPS_COP_0_DIAG
|
||||
#endif
|
||||
MIPSX(user_intr_return):
|
||||
#ifdef PARANOIA
|
||||
PTR_L t0, L_CPU(MIPS_CURLWP)
|
||||
@ -2355,7 +2369,8 @@ LEAF(MIPSX(setfunc_trampoline))
|
||||
# Call the routine specified by cpu_setfunc()
|
||||
# and return directly to user_return
|
||||
PTR_LA ra, MIPSX(user_return)
|
||||
jr s0
|
||||
move t9, s0
|
||||
jr t9
|
||||
move a0, s1
|
||||
END(MIPSX(setfunc_trampoline))
|
||||
|
||||
@ -2437,7 +2452,7 @@ MIPSX(resume):
|
||||
PTR_L v0, L_PRIVATE(a0) # get lwp private
|
||||
_MTC0 v0, MIPS_COP_0_TLB_CONTEXT, 4 # make available for rdhwr
|
||||
#endif
|
||||
j ra
|
||||
jr ra
|
||||
nop
|
||||
END(MIPSX(cpu_switch_resume))
|
||||
|
||||
@ -2604,7 +2619,7 @@ LEAF(MIPSX(pagezero))
|
||||
bgtz a1, 1b
|
||||
addu a0, 64
|
||||
|
||||
j ra
|
||||
jr ra
|
||||
nop
|
||||
END(MIPSX(pagezero))
|
||||
#endif /* USE_64BIT_INSTRUCTIONS */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user